4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
14 #include <linux/sched.h>
15 #include <linux/cache.h>
16 #include <linux/mmu_context.h>
17 #include <linux/syscalls.h>
18 #include <linux/uaccess.h>
19 #include <linux/pagemap.h>
20 #include <asm/cacheflush.h>
21 #include <asm/cachectl.h>
22 #include <asm/setup.h>
24 static int l2_line_sz;
26 volatile int slc_enable = 1, ioc_enable = 1;
28 void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr,
29 unsigned long sz, const int cacheop);
31 void (*__dma_cache_wback_inv)(unsigned long start, unsigned long sz);
32 void (*__dma_cache_inv)(unsigned long start, unsigned long sz);
33 void (*__dma_cache_wback)(unsigned long start, unsigned long sz);
35 char *arc_cache_mumbojumbo(int c, char *buf, int len)
38 struct cpuinfo_arc_cache *p;
40 #define PR_CACHE(p, cfg, str) \
42 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
44 n += scnprintf(buf + n, len - n, \
45 str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \
46 (p)->sz_k, (p)->assoc, (p)->line_len, \
47 (p)->vipt ? "VIPT" : "PIPT", \
48 (p)->alias ? " aliasing" : "", \
51 PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache");
52 PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache");
57 p = &cpuinfo_arc700[c].slc;
59 n += scnprintf(buf + n, len - n,
60 "SLC\t\t: %uK, %uB Line%s\n",
61 p->sz_k, p->line_len, IS_USED_RUN(slc_enable));
64 n += scnprintf(buf + n, len - n, "IOC\t\t:%s\n",
65 IS_DISABLED_RUN(ioc_enable));
71 * Read the Cache Build Confuration Registers, Decode them and save into
72 * the cpuinfo structure for later use.
73 * No Validation done here, simply read/convert the BCRs
75 static void read_decode_cache_bcr_arcv2(int cpu)
77 struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc;
78 struct bcr_generic sbcr;
81 #ifdef CONFIG_CPU_BIG_ENDIAN
82 unsigned int pad:24, way:2, lsz:2, sz:4;
84 unsigned int sz:4, lsz:2, way:2, pad:24;
88 struct bcr_clust_cfg {
89 #ifdef CONFIG_CPU_BIG_ENDIAN
90 unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
92 unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
96 READ_BCR(ARC_REG_SLC_BCR, sbcr);
98 READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
99 p_slc->ver = sbcr.ver;
100 p_slc->sz_k = 128 << slc_cfg.sz;
101 l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64;
104 READ_BCR(ARC_REG_CLUSTER_BCR, cbcr);
105 if (cbcr.c && ioc_enable)
109 void read_decode_cache_bcr(void)
111 struct cpuinfo_arc_cache *p_ic, *p_dc;
112 unsigned int cpu = smp_processor_id();
114 #ifdef CONFIG_CPU_BIG_ENDIAN
115 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
117 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
121 p_ic = &cpuinfo_arc700[cpu].icache;
122 READ_BCR(ARC_REG_IC_BCR, ibcr);
128 BUG_ON(ibcr.config != 3);
129 p_ic->assoc = 2; /* Fixed to 2w set assoc */
130 } else if (ibcr.ver >= 4) {
131 p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */
134 p_ic->line_len = 8 << ibcr.line_len;
135 p_ic->sz_k = 1 << (ibcr.sz - 1);
136 p_ic->ver = ibcr.ver;
138 p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1;
141 p_dc = &cpuinfo_arc700[cpu].dcache;
142 READ_BCR(ARC_REG_DC_BCR, dbcr);
148 BUG_ON(dbcr.config != 2);
149 p_dc->assoc = 4; /* Fixed to 4w set assoc */
151 p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1;
152 } else if (dbcr.ver >= 4) {
153 p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */
155 p_dc->alias = 0; /* PIPT so can't VIPT alias */
158 p_dc->line_len = 16 << dbcr.line_len;
159 p_dc->sz_k = 1 << (dbcr.sz - 1);
160 p_dc->ver = dbcr.ver;
164 read_decode_cache_bcr_arcv2(cpu);
168 * Line Operation on {I,D}-Cache
173 #define OP_FLUSH_N_INV 0x3
174 #define OP_INV_IC 0x4
177 * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3)
179 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
180 * The orig Cache Management Module "CDU" only required paddr to invalidate a
181 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
182 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
183 * the exact same line.
185 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
186 * paddr alone could not be used to correctly index the cache.
189 * MMU v1/v2 (Fixed Page Size 8k)
191 * The solution was to provide CDU with these additonal vaddr bits. These
192 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
193 * standard page size of 8k.
194 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
195 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
196 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
197 * represent the offset within cache-line. The adv of using this "clumsy"
198 * interface for additional info was no new reg was needed in CDU programming
201 * 17:13 represented the max num of bits passable, actual bits needed were
202 * fewer, based on the num-of-aliases possible.
203 * -for 2 alias possibility, only bit 13 needed (32K cache)
204 * -for 4 alias possibility, bits 14:13 needed (64K cache)
209 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
210 * only support 8k (default), 16k and 4k.
211 * However from hardware perspective, smaller page sizes aggrevate aliasing
212 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
213 * the existing scheme of piggybacking won't work for certain configurations.
214 * Two new registers IC_PTAG and DC_PTAG inttoduced.
215 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
219 void __cache_line_loop_v2(unsigned long paddr, unsigned long vaddr,
220 unsigned long sz, const int op)
222 unsigned int aux_cmd;
224 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
226 if (op == OP_INV_IC) {
227 aux_cmd = ARC_REG_IC_IVIL;
229 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
230 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
233 /* Ensure we properly floor/ceil the non-line aligned/sized requests
234 * and have @paddr - aligned to cache line and integral @num_lines.
235 * This however can be avoided for page sized since:
236 * -@paddr will be cache-line aligned already (being page aligned)
237 * -@sz will be integral multiple of line size (being page sized).
240 sz += paddr & ~CACHE_LINE_MASK;
241 paddr &= CACHE_LINE_MASK;
242 vaddr &= CACHE_LINE_MASK;
245 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
247 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
248 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
250 while (num_lines-- > 0) {
251 write_aux_reg(aux_cmd, paddr);
252 paddr += L1_CACHE_BYTES;
257 void __cache_line_loop_v3(unsigned long paddr, unsigned long vaddr,
258 unsigned long sz, const int op)
260 unsigned int aux_cmd, aux_tag;
262 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
264 if (op == OP_INV_IC) {
265 aux_cmd = ARC_REG_IC_IVIL;
266 aux_tag = ARC_REG_IC_PTAG;
268 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
269 aux_tag = ARC_REG_DC_PTAG;
272 /* Ensure we properly floor/ceil the non-line aligned/sized requests
273 * and have @paddr - aligned to cache line and integral @num_lines.
274 * This however can be avoided for page sized since:
275 * -@paddr will be cache-line aligned already (being page aligned)
276 * -@sz will be integral multiple of line size (being page sized).
279 sz += paddr & ~CACHE_LINE_MASK;
280 paddr &= CACHE_LINE_MASK;
281 vaddr &= CACHE_LINE_MASK;
283 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
286 * MMUv3, cache ops require paddr in PTAG reg
287 * if V-P const for loop, PTAG can be written once outside loop
290 write_aux_reg(aux_tag, paddr);
292 while (num_lines-- > 0) {
294 write_aux_reg(aux_tag, paddr);
295 paddr += L1_CACHE_BYTES;
298 write_aux_reg(aux_cmd, vaddr);
299 vaddr += L1_CACHE_BYTES;
304 * In HS38x (MMU v4), although icache is VIPT, only paddr is needed for cache
305 * maintenance ops (in IVIL reg), as long as icache doesn't alias.
307 * For Aliasing icache, vaddr is also needed (in IVIL), while paddr is
308 * specified in PTAG (similar to MMU v3)
311 void __cache_line_loop_v4(unsigned long paddr, unsigned long vaddr,
312 unsigned long sz, const int cacheop)
314 unsigned int aux_cmd;
316 const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
318 if (cacheop == OP_INV_IC) {
319 aux_cmd = ARC_REG_IC_IVIL;
321 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
322 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
325 /* Ensure we properly floor/ceil the non-line aligned/sized requests
326 * and have @paddr - aligned to cache line and integral @num_lines.
327 * This however can be avoided for page sized since:
328 * -@paddr will be cache-line aligned already (being page aligned)
329 * -@sz will be integral multiple of line size (being page sized).
332 sz += paddr & ~CACHE_LINE_MASK;
333 paddr &= CACHE_LINE_MASK;
336 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
338 while (num_lines-- > 0) {
339 write_aux_reg(aux_cmd, paddr);
340 paddr += L1_CACHE_BYTES;
344 #if (CONFIG_ARC_MMU_VER < 3)
345 #define __cache_line_loop __cache_line_loop_v2
346 #elif (CONFIG_ARC_MMU_VER == 3)
347 #define __cache_line_loop __cache_line_loop_v3
348 #elif (CONFIG_ARC_MMU_VER > 3)
349 #define __cache_line_loop __cache_line_loop_v4
352 #ifdef CONFIG_ARC_HAS_DCACHE
354 /***************************************************************
355 * Machine specific helpers for Entire D-Cache or Per Line ops
358 static inline void __before_dc_op(const int op)
360 if (op == OP_FLUSH_N_INV) {
361 /* Dcache provides 2 cmd: FLUSH or INV
362 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
363 * flush-n-inv is achieved by INV cmd but with IM=1
364 * So toggle INV sub-mode depending on op request and default
366 const unsigned int ctl = ARC_REG_DC_CTRL;
367 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);
371 static inline void __after_dc_op(const int op)
374 const unsigned int ctl = ARC_REG_DC_CTRL;
377 /* flush / flush-n-inv both wait */
378 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS)
381 /* Switch back to default Invalidate mode */
382 if (op == OP_FLUSH_N_INV)
383 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);
388 * Operation on Entire D-Cache
389 * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
390 * Note that constant propagation ensures all the checks are gone
393 static inline void __dc_entire_op(const int op)
399 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
400 aux = ARC_REG_DC_IVDC;
402 aux = ARC_REG_DC_FLSH;
404 write_aux_reg(aux, 0x1);
409 /* For kernel mappings cache operation: index is same as paddr */
410 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
413 * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback)
415 static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
416 unsigned long sz, const int op)
420 local_irq_save(flags);
424 __cache_line_loop(paddr, vaddr, sz, op);
428 local_irq_restore(flags);
433 #define __dc_entire_op(op)
434 #define __dc_line_op(paddr, vaddr, sz, op)
435 #define __dc_line_op_k(paddr, sz, op)
437 #endif /* CONFIG_ARC_HAS_DCACHE */
439 #ifdef CONFIG_ARC_HAS_ICACHE
441 static inline void __ic_entire_inv(void)
443 write_aux_reg(ARC_REG_IC_IVIC, 1);
444 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */
448 __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr,
453 local_irq_save(flags);
454 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);
455 local_irq_restore(flags);
460 #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s)
465 unsigned long paddr, vaddr;
469 static void __ic_line_inv_vaddr_helper(void *info)
471 struct ic_inv_args *ic_inv = info;
473 __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz);
476 static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
479 struct ic_inv_args ic_inv = {
485 on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1);
488 #endif /* CONFIG_SMP */
490 #else /* !CONFIG_ARC_HAS_ICACHE */
492 #define __ic_entire_inv()
493 #define __ic_line_inv_vaddr(pstart, vstart, sz)
495 #endif /* CONFIG_ARC_HAS_ICACHE */
497 noinline void slc_op(unsigned long paddr, unsigned long sz, const int op)
499 #ifdef CONFIG_ISA_ARCV2
501 * SLC is shared between all cores and concurrent aux operations from
502 * multiple cores need to be serialized using a spinlock
503 * A concurrent operation can be silently ignored and/or the old/new
504 * operation can remain incomplete forever (lockup in SLC_CTRL_BUSY loop
507 static DEFINE_SPINLOCK(lock);
511 spin_lock_irqsave(&lock, flags);
514 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
515 * - b'000 (default) is Flush,
516 * - b'001 is Invalidate if CTRL.IM == 0
517 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
519 ctrl = read_aux_reg(ARC_REG_SLC_CTRL);
521 /* Don't rely on default value of IM bit */
522 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
523 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
528 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
530 ctrl &= ~SLC_CTRL_RGN_OP_INV;
532 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
535 * Lower bits are ignored, no need to clip
536 * END needs to be setup before START (latter triggers the operation)
537 * END can't be same as START, so add (l2_line_sz - 1) to sz
539 write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
540 write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
542 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
544 spin_unlock_irqrestore(&lock, flags);
548 /***********************************************************
553 * Handle cache congruency of kernel and userspace mappings of page when kernel
554 * writes-to/reads-from
556 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
557 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
558 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
559 * -In SMP, if hardware caches are coherent
561 * There's a corollary case, where kernel READs from a userspace mapped page.
562 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
564 void flush_dcache_page(struct page *page)
566 struct address_space *mapping;
568 if (!cache_is_vipt_aliasing()) {
569 clear_bit(PG_dc_clean, &page->flags);
573 /* don't handle anon pages here */
574 mapping = page_mapping(page);
579 * pagecache page, file not yet mapped to userspace
580 * Make a note that K-mapping is dirty
582 if (!mapping_mapped(mapping)) {
583 clear_bit(PG_dc_clean, &page->flags);
584 } else if (page_mapped(page)) {
586 /* kernel reading from page with U-mapping */
587 unsigned long paddr = (unsigned long)page_address(page);
588 unsigned long vaddr = page->index << PAGE_CACHE_SHIFT;
590 if (addr_not_cache_congruent(paddr, vaddr))
591 __flush_dcache_page(paddr, vaddr);
594 EXPORT_SYMBOL(flush_dcache_page);
597 * DMA ops for systems with L1 cache only
598 * Make memory coherent with L1 cache by flushing/invalidating L1 lines
600 static void __dma_cache_wback_inv_l1(unsigned long start, unsigned long sz)
602 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
605 static void __dma_cache_inv_l1(unsigned long start, unsigned long sz)
607 __dc_line_op_k(start, sz, OP_INV);
610 static void __dma_cache_wback_l1(unsigned long start, unsigned long sz)
612 __dc_line_op_k(start, sz, OP_FLUSH);
616 * DMA ops for systems with both L1 and L2 caches, but without IOC
617 * Both L1 and L2 lines need to be explicity flushed/invalidated
619 static void __dma_cache_wback_inv_slc(unsigned long start, unsigned long sz)
621 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
622 slc_op(start, sz, OP_FLUSH_N_INV);
625 static void __dma_cache_inv_slc(unsigned long start, unsigned long sz)
627 __dc_line_op_k(start, sz, OP_INV);
628 slc_op(start, sz, OP_INV);
631 static void __dma_cache_wback_slc(unsigned long start, unsigned long sz)
633 __dc_line_op_k(start, sz, OP_FLUSH);
634 slc_op(start, sz, OP_FLUSH);
638 * DMA ops for systems with IOC
639 * IOC hardware snoops all DMA traffic keeping the caches consistent with
640 * memory - eliding need for any explicit cache maintenance of DMA buffers
642 static void __dma_cache_wback_inv_ioc(unsigned long start, unsigned long sz) {}
643 static void __dma_cache_inv_ioc(unsigned long start, unsigned long sz) {}
644 static void __dma_cache_wback_ioc(unsigned long start, unsigned long sz) {}
649 void dma_cache_wback_inv(unsigned long start, unsigned long sz)
651 __dma_cache_wback_inv(start, sz);
653 EXPORT_SYMBOL(dma_cache_wback_inv);
655 void dma_cache_inv(unsigned long start, unsigned long sz)
657 __dma_cache_inv(start, sz);
659 EXPORT_SYMBOL(dma_cache_inv);
661 void dma_cache_wback(unsigned long start, unsigned long sz)
663 __dma_cache_wback(start, sz);
665 EXPORT_SYMBOL(dma_cache_wback);
668 * This is API for making I/D Caches consistent when modifying
669 * kernel code (loadable modules, kprobes, kgdb...)
670 * This is called on insmod, with kernel virtual address for CODE of
671 * the module. ARC cache maintenance ops require PHY address thus we
672 * need to convert vmalloc addr to PHY addr
674 void flush_icache_range(unsigned long kstart, unsigned long kend)
678 WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__);
680 /* Shortcut for bigger flush ranges.
681 * Here we don't care if this was kernel virtual or phy addr
683 tot_sz = kend - kstart;
684 if (tot_sz > PAGE_SIZE) {
689 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
690 if (likely(kstart > PAGE_OFFSET)) {
692 * The 2nd arg despite being paddr will be used to index icache
693 * This is OK since no alternate virtual mappings will exist
694 * given the callers for this case: kprobe/kgdb in built-in
697 __sync_icache_dcache(kstart, kstart, kend - kstart);
702 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
703 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
704 * handling of kernel vaddr.
706 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
707 * it still needs to handle a 2 page scenario, where the range
708 * straddles across 2 virtual pages and hence need for loop
711 unsigned int off, sz;
712 unsigned long phy, pfn;
714 off = kstart % PAGE_SIZE;
715 pfn = vmalloc_to_pfn((void *)kstart);
716 phy = (pfn << PAGE_SHIFT) + off;
717 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
718 __sync_icache_dcache(phy, kstart, sz);
723 EXPORT_SYMBOL(flush_icache_range);
726 * General purpose helper to make I and D cache lines consistent.
727 * @paddr is phy addr of region
728 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
729 * However in one instance, when called by kprobe (for a breakpt in
730 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
731 * use a paddr to index the cache (despite VIPT). This is fine since since a
732 * builtin kernel page will not have any virtual mappings.
733 * kprobe on loadable module will be kernel vaddr.
735 void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
737 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
738 __ic_line_inv_vaddr(paddr, vaddr, len);
741 /* wrapper to compile time eliminate alignment checks in flush loop */
742 void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
744 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
748 * wrapper to clearout kernel or userspace mappings of a page
749 * For kernel mappings @vaddr == @paddr
751 void __flush_dcache_page(unsigned long paddr, unsigned long vaddr)
753 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
756 noinline void flush_cache_all(void)
760 local_irq_save(flags);
763 __dc_entire_op(OP_FLUSH_N_INV);
765 local_irq_restore(flags);
769 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
771 void flush_cache_mm(struct mm_struct *mm)
776 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
779 unsigned int paddr = pfn << PAGE_SHIFT;
781 u_vaddr &= PAGE_MASK;
783 __flush_dcache_page(paddr, u_vaddr);
785 if (vma->vm_flags & VM_EXEC)
786 __inv_icache_page(paddr, u_vaddr);
789 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
795 void flush_anon_page(struct vm_area_struct *vma, struct page *page,
796 unsigned long u_vaddr)
798 /* TBD: do we really need to clear the kernel mapping */
799 __flush_dcache_page(page_address(page), u_vaddr);
800 __flush_dcache_page(page_address(page), page_address(page));
806 void copy_user_highpage(struct page *to, struct page *from,
807 unsigned long u_vaddr, struct vm_area_struct *vma)
809 unsigned long kfrom = (unsigned long)page_address(from);
810 unsigned long kto = (unsigned long)page_address(to);
811 int clean_src_k_mappings = 0;
814 * If SRC page was already mapped in userspace AND it's U-mapping is
815 * not congruent with K-mapping, sync former to physical page so that
816 * K-mapping in memcpy below, sees the right data
818 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
819 * equally valid for SRC page as well
821 if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) {
822 __flush_dcache_page(kfrom, u_vaddr);
823 clean_src_k_mappings = 1;
826 copy_page((void *)kto, (void *)kfrom);
829 * Mark DST page K-mapping as dirty for a later finalization by
830 * update_mmu_cache(). Although the finalization could have been done
831 * here as well (given that both vaddr/paddr are available).
832 * But update_mmu_cache() already has code to do that for other
833 * non copied user pages (e.g. read faults which wire in pagecache page
836 clear_bit(PG_dc_clean, &to->flags);
839 * if SRC was already usermapped and non-congruent to kernel mapping
840 * sync the kernel mapping back to physical page
842 if (clean_src_k_mappings) {
843 __flush_dcache_page(kfrom, kfrom);
844 set_bit(PG_dc_clean, &from->flags);
846 clear_bit(PG_dc_clean, &from->flags);
850 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
853 clear_bit(PG_dc_clean, &page->flags);
857 /**********************************************************************
858 * Explicit Cache flush request from user space via syscall
859 * Needed for JITs which generate code on the fly
861 SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
863 /* TBD: optimize this */
868 void arc_cache_init(void)
870 unsigned int __maybe_unused cpu = smp_processor_id();
873 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
875 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
876 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
879 panic("cache support enabled but non-existent cache\n");
881 if (ic->line_len != L1_CACHE_BYTES)
882 panic("ICache line [%d] != kernel Config [%d]",
883 ic->line_len, L1_CACHE_BYTES);
885 if (ic->ver != CONFIG_ARC_MMU_VER)
886 panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
887 ic->ver, CONFIG_ARC_MMU_VER);
890 * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG
891 * pair to provide vaddr/paddr respectively, just as in MMU v3
893 if (is_isa_arcv2() && ic->alias)
894 _cache_line_loop_ic_fn = __cache_line_loop_v3;
896 _cache_line_loop_ic_fn = __cache_line_loop;
899 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {
900 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
903 panic("cache support enabled but non-existent cache\n");
905 if (dc->line_len != L1_CACHE_BYTES)
906 panic("DCache line [%d] != kernel Config [%d]",
907 dc->line_len, L1_CACHE_BYTES);
909 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */
910 if (is_isa_arcompact()) {
911 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
913 if (dc->alias && !handled)
914 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
915 else if (!dc->alias && handled)
916 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
920 if (is_isa_arcv2() && l2_line_sz && !slc_enable) {
922 /* IM set : flush before invalidate */
923 write_aux_reg(ARC_REG_SLC_CTRL,
924 read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_IM);
926 write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
928 /* Important to wait for flush to complete */
929 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
930 write_aux_reg(ARC_REG_SLC_CTRL,
931 read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE);
934 if (is_isa_arcv2() && ioc_exists) {
935 /* IO coherency base - 0x8z */
936 write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
937 /* IO coherency aperture size - 512Mb: 0x8z-0xAz */
938 write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11);
939 /* Enable partial writes */
940 write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
941 /* Enable IO coherency */
942 write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
944 __dma_cache_wback_inv = __dma_cache_wback_inv_ioc;
945 __dma_cache_inv = __dma_cache_inv_ioc;
946 __dma_cache_wback = __dma_cache_wback_ioc;
947 } else if (is_isa_arcv2() && l2_line_sz && slc_enable) {
948 __dma_cache_wback_inv = __dma_cache_wback_inv_slc;
949 __dma_cache_inv = __dma_cache_inv_slc;
950 __dma_cache_wback = __dma_cache_wback_slc;
952 __dma_cache_wback_inv = __dma_cache_wback_inv_l1;
953 __dma_cache_inv = __dma_cache_inv_l1;
954 __dma_cache_wback = __dma_cache_wback_l1;