arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #define MAX_SOURCES 400
  14
  15 / {
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         compatible = "ti,dra7xx";
  20         interrupt-parent = <&crossbar_mpu>;
  21         chosen { };
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35                 serial6 = &uart7;
  36                 serial7 = &uart8;
  37                 serial8 = &uart9;
  38                 serial9 = &uart10;
  39                 ethernet0 = &cpsw_emac0;
  40                 ethernet1 = &cpsw_emac1;
  41                 d_can0 = &dcan1;
  42                 d_can1 = &dcan2;
  43                 spi0 = &qspi;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&gic>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x0 0x48211000 0x0 0x1000>,
  60                       <0x0 0x48212000 0x0 0x2000>,
  61                       <0x0 0x48214000 0x0 0x2000>,
  62                       <0x0 0x48216000 0x0 0x2000>;
  63                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  64                 interrupt-parent = <&gic>;
  65         };
  66
  67         wakeupgen: interrupt-controller@48281000 {
  68                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  69                 interrupt-controller;
  70                 #interrupt-cells = <3>;
  71                 reg = <0x0 0x48281000 0x0 0x1000>;
  72                 interrupt-parent = <&gic>;
  73         };
  74
  75         cpus {
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78
  79                 cpu0: cpu@0 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a15";
  82                         reg = <0>;
  83
  84                         operating-points = <
  85                                 /* kHz    uV */
  86                                 1000000 1060000
  87                                 1176000 1160000
  88                                 >;
  89
  90                         clocks = <&dpll_mpu_ck>;
  91                         clock-names = "cpu";
  92
  93                         clock-latency = <300000>; /* From omap-cpufreq driver */
  94
  95                         /* cooling options */
  96                         cooling-min-level = <0>;
  97                         cooling-max-level = <2>;
  98                         #cooling-cells = <2>; /* min followed by max */
  99                 };
 100         };
 101
 102         /*
 103          * The soc node represents the soc top level view. It is used for IPs
 104          * that are not memory mapped in the MPU view or for the MPU itself.
 105          */
 106         soc {
 107                 compatible = "ti,omap-infra";
 108                 mpu {
 109                         compatible = "ti,omap5-mpu";
 110                         ti,hwmods = "mpu";
 111                 };
 112         };
 113
 114         /*
 115          * XXX: Use a flat representation of the SOC interconnect.
 116          * The real OMAP interconnect network is quite complex.
 117          * Since it will not bring real advantage to represent that in DT for
 118          * the moment, just use a fake OCP bus entry to represent the whole bus
 119          * hierarchy.
 120          */
 121         ocp {
 122                 compatible = "ti,dra7-l3-noc", "simple-bus";
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 ranges = <0x0 0x0 0x0 0xc0000000>;
 126                 ti,hwmods = "l3_main_1", "l3_main_2";
 127                 reg = <0x0 0x44000000 0x0 0x1000000>,
 128                       <0x0 0x45000000 0x0 0x1000>;
 129                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 130                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 131
 132                 l4_cfg: l4@4a000000 {
 133                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 134                         #address-cells = <1>;
 135                         #size-cells = <1>;
 136                         ranges = <0 0x4a000000 0x22c000>;
 137
 138                         scm: scm@2000 {
 139                                 compatible = "ti,dra7-scm-core", "simple-bus";
 140                                 reg = <0x2000 0x2000>;
 141                                 #address-cells = <1>;
 142                                 #size-cells = <1>;
 143                                 ranges = <0 0x2000 0x2000>;
 144
 145                                 scm_conf: scm_conf@0 {
 146                                         compatible = "syscon", "simple-bus";
 147                                         reg = <0x0 0x1400>;
 148                                         #address-cells = <1>;
 149                                         #size-cells = <1>;
 150                                         ranges = <0 0x0 0x1400>;
 151
 152                                         pbias_regulator: pbias_regulator@e00 {
 153                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
 154                                                 reg = <0xe00 0x4>;
 155                                                 syscon = <&scm_conf>;
 156                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 157                                                         regulator-name = "pbias_mmc_omap5";
 158                                                         regulator-min-microvolt = <1800000>;
 159                                                         regulator-max-microvolt = <3000000>;
 160                                                 };
 161                                         };
 162
 163                                         scm_conf_clocks: clocks {
 164                                                 #address-cells = <1>;
 165                                                 #size-cells = <0>;
 166                                         };
 167                                 };
 168
 169                                 dra7_pmx_core: pinmux@1400 {
 170                                         compatible = "ti,dra7-padconf",
 171                                                      "pinctrl-single";
 172                                         reg = <0x1400 0x0468>;
 173                                         #address-cells = <1>;
 174                                         #size-cells = <0>;
 175                                         #pinctrl-cells = <1>;
 176                                         #interrupt-cells = <1>;
 177                                         interrupt-controller;
 178                                         pinctrl-single,register-width = <32>;
 179                                         pinctrl-single,function-mask = <0x3fffffff>;
 180                                 };
 181
 182                                 scm_conf1: scm_conf@1c04 {
 183                                         compatible = "syscon";
 184                                         reg = <0x1c04 0x0020>;
 185                                 };
 186
 187                                 scm_conf_pcie: scm_conf@1c24 {
 188                                         compatible = "syscon";
 189                                         reg = <0x1c24 0x0024>;
 190                                 };
 191
 192                                 sdma_xbar: dma-router@b78 {
 193                                         compatible = "ti,dra7-dma-crossbar";
 194                                         reg = <0xb78 0xfc>;
 195                                         #dma-cells = <1>;
 196                                         dma-requests = <205>;
 197                                         ti,dma-safe-map = <0>;
 198                                         dma-masters = <&sdma>;
 199                                 };
 200
 201                                 edma_xbar: dma-router@c78 {
 202                                         compatible = "ti,dra7-dma-crossbar";
 203                                         reg = <0xc78 0x7c>;
 204                                         #dma-cells = <2>;
 205                                         dma-requests = <204>;
 206                                         ti,dma-safe-map = <0>;
 207                                         dma-masters = <&edma>;
 208                                 };
 209                         };
 210
 211                         cm_core_aon: cm_core_aon@5000 {
 212                                 compatible = "ti,dra7-cm-core-aon";
 213                                 reg = <0x5000 0x2000>;
 214
 215                                 cm_core_aon_clocks: clocks {
 216                                         #address-cells = <1>;
 217                                         #size-cells = <0>;
 218                                 };
 219
 220                                 cm_core_aon_clockdomains: clockdomains {
 221                                 };
 222                         };
 223
 224                         cm_core: cm_core@8000 {
 225                                 compatible = "ti,dra7-cm-core";
 226                                 reg = <0x8000 0x3000>;
 227
 228                                 cm_core_clocks: clocks {
 229                                         #address-cells = <1>;
 230                                         #size-cells = <0>;
 231                                 };
 232
 233                                 cm_core_clockdomains: clockdomains {
 234                                 };
 235                         };
 236                 };
 237
 238                 l4_wkup: l4@4ae00000 {
 239                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 240                         #address-cells = <1>;
 241                         #size-cells = <1>;
 242                         ranges = <0 0x4ae00000 0x3f000>;
 243
 244                         counter32k: counter@4000 {
 245                                 compatible = "ti,omap-counter32k";
 246                                 reg = <0x4000 0x40>;
 247                                 ti,hwmods = "counter_32k";
 248                         };
 249
 250                         prm: prm@6000 {
 251                                 compatible = "ti,dra7-prm";
 252                                 reg = <0x6000 0x3000>;
 253                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 254
 255                                 prm_clocks: clocks {
 256                                         #address-cells = <1>;
 257                                         #size-cells = <0>;
 258                                 };
 259
 260                                 prm_clockdomains: clockdomains {
 261                                 };
 262                         };
 263
 264                         scm_wkup: scm_conf@c000 {
 265                                 compatible = "syscon";
 266                                 reg = <0xc000 0x1000>;
 267                         };
 268                 };
 269
 270                 axi@0 {
 271                         compatible = "simple-bus";
 272                         #size-cells = <1>;
 273                         #address-cells = <1>;
 274                         ranges = <0x51000000 0x51000000 0x3000
 275                                   0x0        0x20000000 0x10000000>;
 276                         pcie1: pcie@51000000 {
 277                                 compatible = "ti,dra7-pcie";
 278                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 279                                 reg-names = "rc_dbics", "ti_conf", "config";
 280                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 281                                 #address-cells = <3>;
 282                                 #size-cells = <2>;
 283                                 device_type = "pci";
 284                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 285                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 286                                 #interrupt-cells = <1>;
 287                                 num-lanes = <1>;
 288                                 linux,pci-domain = <0>;
 289                                 ti,hwmods = "pcie1";
 290                                 phys = <&pcie1_phy>;
 291                                 phy-names = "pcie-phy0";
 292                                 interrupt-map-mask = <0 0 0 7>;
 293                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 294                                                 <0 0 0 2 &pcie1_intc 2>,
 295                                                 <0 0 0 3 &pcie1_intc 3>,
 296                                                 <0 0 0 4 &pcie1_intc 4>;
 297                                 pcie1_intc: interrupt-controller {
 298                                         interrupt-controller;
 299                                         #address-cells = <0>;
 300                                         #interrupt-cells = <1>;
 301                                 };
 302                         };
 303                 };
 304
 305                 axi@1 {
 306                         compatible = "simple-bus";
 307                         #size-cells = <1>;
 308                         #address-cells = <1>;
 309                         ranges = <0x51800000 0x51800000 0x3000
 310                                   0x0        0x30000000 0x10000000>;
 311                         status = "disabled";
 312                         pcie@51800000 {
 313                                 compatible = "ti,dra7-pcie";
 314                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 315                                 reg-names = "rc_dbics", "ti_conf", "config";
 316                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 317                                 #address-cells = <3>;
 318                                 #size-cells = <2>;
 319                                 device_type = "pci";
 320                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 321                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 322                                 #interrupt-cells = <1>;
 323                                 num-lanes = <1>;
 324                                 linux,pci-domain = <1>;
 325                                 ti,hwmods = "pcie2";
 326                                 phys = <&pcie2_phy>;
 327                                 phy-names = "pcie-phy0";
 328                                 interrupt-map-mask = <0 0 0 7>;
 329                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 330                                                 <0 0 0 2 &pcie2_intc 2>,
 331                                                 <0 0 0 3 &pcie2_intc 3>,
 332                                                 <0 0 0 4 &pcie2_intc 4>;
 333                                 pcie2_intc: interrupt-controller {
 334                                         interrupt-controller;
 335                                         #address-cells = <0>;
 336                                         #interrupt-cells = <1>;
 337                                 };
 338                         };
 339                 };
 340
 341                 ocmcram1: ocmcram@40300000 {
 342                         compatible = "mmio-sram";
 343                         reg = <0x40300000 0x80000>;
 344                         ranges = <0x0 0x40300000 0x80000>;
 345                         #address-cells = <1>;
 346                         #size-cells = <1>;
 347                         /*
 348                          * This is a placeholder for an optional reserved
 349                          * region for use by secure software. The size
 350                          * of this region is not known until runtime so it
 351                          * is set as zero to either be updated to reserve
 352                          * space or left unchanged to leave all SRAM for use.
 353                          * On HS parts that that require the reserved region
 354                          * either the bootloader can update the size to
 355                          * the required amount or the node can be overridden
 356                          * from the board dts file for the secure platform.
 357                          */
 358                         sram-hs@0 {
 359                                 compatible = "ti,secure-ram";
 360                                 reg = <0x0 0x0>;
 361                         };
 362                 };
 363
 364                 /*
 365                  * NOTE: ocmcram2 and ocmcram3 are not available on all
 366                  * DRA7xx and AM57xx variants. Confirm availability in
 367                  * the data manual for the exact part number in use
 368                  * before enabling these nodes in the board dts file.
 369                  */
 370                 ocmcram2: ocmcram@40400000 {
 371                         status = "disabled";
 372                         compatible = "mmio-sram";
 373                         reg = <0x40400000 0x100000>;
 374                         ranges = <0x0 0x40400000 0x100000>;
 375                         #address-cells = <1>;
 376                         #size-cells = <1>;
 377                 };
 378
 379                 ocmcram3: ocmcram@40500000 {
 380                         status = "disabled";
 381                         compatible = "mmio-sram";
 382                         reg = <0x40500000 0x100000>;
 383                         ranges = <0x0 0x40500000 0x100000>;
 384                         #address-cells = <1>;
 385                         #size-cells = <1>;
 386                 };
 387
 388                 bandgap: bandgap@4a0021e0 {
 389                         reg = <0x4a0021e0 0xc
 390                                 0x4a00232c 0xc
 391                                 0x4a002380 0x2c
 392                                 0x4a0023C0 0x3c
 393                                 0x4a002564 0x8
 394                                 0x4a002574 0x50>;
 395                                 compatible = "ti,dra752-bandgap";
 396                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 397                                 #thermal-sensor-cells = <1>;
 398                 };
 399
 400                 dsp1_system: dsp_system@40d00000 {
 401                         compatible = "syscon";
 402                         reg = <0x40d00000 0x100>;
 403                 };
 404
 405                 sdma: dma-controller@4a056000 {
 406                         compatible = "ti,omap4430-sdma";
 407                         reg = <0x4a056000 0x1000>;
 408                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 409                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 410                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 411                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 412                         #dma-cells = <1>;
 413                         dma-channels = <32>;
 414                         dma-requests = <127>;
 415                 };
 416
 417                 edma: edma@43300000 {
 418                         compatible = "ti,edma3-tpcc";
 419                         ti,hwmods = "tpcc";
 420                         reg = <0x43300000 0x100000>;
 421                         reg-names = "edma3_cc";
 422                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 423                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 424                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 425                         interrupt-names = "edma3_ccint", "edma3_mperr",
 426                                           "edma3_ccerrint";
 427                         dma-requests = <64>;
 428                         #dma-cells = <2>;
 429
 430                         ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
 431
 432                         /*
 433                          * memcpy is disabled, can be enabled with:
 434                          * ti,edma-memcpy-channels = <20 21>;
 435                          * for example. Note that these channels need to be
 436                          * masked in the xbar as well.
 437                          */
 438                 };
 439
 440                 edma_tptc0: tptc@43400000 {
 441                         compatible = "ti,edma3-tptc";
 442                         ti,hwmods = "tptc0";
 443                         reg =   <0x43400000 0x100000>;
 444                         interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 445                         interrupt-names = "edma3_tcerrint";
 446                 };
 447
 448                 edma_tptc1: tptc@43500000 {
 449                         compatible = "ti,edma3-tptc";
 450                         ti,hwmods = "tptc1";
 451                         reg =   <0x43500000 0x100000>;
 452                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 453                         interrupt-names = "edma3_tcerrint";
 454                 };
 455
 456                 gpio1: gpio@4ae10000 {
 457                         compatible = "ti,omap4-gpio";
 458                         reg = <0x4ae10000 0x200>;
 459                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 460                         ti,hwmods = "gpio1";
 461                         gpio-controller;
 462                         #gpio-cells = <2>;
 463                         interrupt-controller;
 464                         #interrupt-cells = <2>;
 465                 };
 466
 467                 gpio2: gpio@48055000 {
 468                         compatible = "ti,omap4-gpio";
 469                         reg = <0x48055000 0x200>;
 470                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 471                         ti,hwmods = "gpio2";
 472                         gpio-controller;
 473                         #gpio-cells = <2>;
 474                         interrupt-controller;
 475                         #interrupt-cells = <2>;
 476                 };
 477
 478                 gpio3: gpio@48057000 {
 479                         compatible = "ti,omap4-gpio";
 480                         reg = <0x48057000 0x200>;
 481                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 482                         ti,hwmods = "gpio3";
 483                         gpio-controller;
 484                         #gpio-cells = <2>;
 485                         interrupt-controller;
 486                         #interrupt-cells = <2>;
 487                 };
 488
 489                 gpio4: gpio@48059000 {
 490                         compatible = "ti,omap4-gpio";
 491                         reg = <0x48059000 0x200>;
 492                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 493                         ti,hwmods = "gpio4";
 494                         gpio-controller;
 495                         #gpio-cells = <2>;
 496                         interrupt-controller;
 497                         #interrupt-cells = <2>;
 498                 };
 499
 500                 gpio5: gpio@4805b000 {
 501                         compatible = "ti,omap4-gpio";
 502                         reg = <0x4805b000 0x200>;
 503                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 504                         ti,hwmods = "gpio5";
 505                         gpio-controller;
 506                         #gpio-cells = <2>;
 507                         interrupt-controller;
 508                         #interrupt-cells = <2>;
 509                 };
 510
 511                 gpio6: gpio@4805d000 {
 512                         compatible = "ti,omap4-gpio";
 513                         reg = <0x4805d000 0x200>;
 514                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 515                         ti,hwmods = "gpio6";
 516                         gpio-controller;
 517                         #gpio-cells = <2>;
 518                         interrupt-controller;
 519                         #interrupt-cells = <2>;
 520                 };
 521
 522                 gpio7: gpio@48051000 {
 523                         compatible = "ti,omap4-gpio";
 524                         reg = <0x48051000 0x200>;
 525                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 526                         ti,hwmods = "gpio7";
 527                         gpio-controller;
 528                         #gpio-cells = <2>;
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                 };
 532
 533                 gpio8: gpio@48053000 {
 534                         compatible = "ti,omap4-gpio";
 535                         reg = <0x48053000 0x200>;
 536                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 537                         ti,hwmods = "gpio8";
 538                         gpio-controller;
 539                         #gpio-cells = <2>;
 540                         interrupt-controller;
 541                         #interrupt-cells = <2>;
 542                 };
 543
 544                 uart1: serial@4806a000 {
 545                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 546                         reg = <0x4806a000 0x100>;
 547                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 548                         ti,hwmods = "uart1";
 549                         clock-frequency = <48000000>;
 550                         status = "disabled";
 551                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 552                         dma-names = "tx", "rx";
 553                 };
 554
 555                 uart2: serial@4806c000 {
 556                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 557                         reg = <0x4806c000 0x100>;
 558                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 559                         ti,hwmods = "uart2";
 560                         clock-frequency = <48000000>;
 561                         status = "disabled";
 562                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 563                         dma-names = "tx", "rx";
 564                 };
 565
 566                 uart3: serial@48020000 {
 567                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 568                         reg = <0x48020000 0x100>;
 569                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 570                         ti,hwmods = "uart3";
 571                         clock-frequency = <48000000>;
 572                         status = "disabled";
 573                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 574                         dma-names = "tx", "rx";
 575                 };
 576
 577                 uart4: serial@4806e000 {
 578                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 579                         reg = <0x4806e000 0x100>;
 580                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 581                         ti,hwmods = "uart4";
 582                         clock-frequency = <48000000>;
 583                         status = "disabled";
 584                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 585                         dma-names = "tx", "rx";
 586                 };
 587
 588                 uart5: serial@48066000 {
 589                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 590                         reg = <0x48066000 0x100>;
 591                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 592                         ti,hwmods = "uart5";
 593                         clock-frequency = <48000000>;
 594                         status = "disabled";
 595                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 596                         dma-names = "tx", "rx";
 597                 };
 598
 599                 uart6: serial@48068000 {
 600                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 601                         reg = <0x48068000 0x100>;
 602                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 603                         ti,hwmods = "uart6";
 604                         clock-frequency = <48000000>;
 605                         status = "disabled";
 606                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 607                         dma-names = "tx", "rx";
 608                 };
 609
 610                 uart7: serial@48420000 {
 611                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 612                         reg = <0x48420000 0x100>;
 613                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 614                         ti,hwmods = "uart7";
 615                         clock-frequency = <48000000>;
 616                         status = "disabled";
 617                 };
 618
 619                 uart8: serial@48422000 {
 620                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 621                         reg = <0x48422000 0x100>;
 622                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 623                         ti,hwmods = "uart8";
 624                         clock-frequency = <48000000>;
 625                         status = "disabled";
 626                 };
 627
 628                 uart9: serial@48424000 {
 629                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 630                         reg = <0x48424000 0x100>;
 631                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 632                         ti,hwmods = "uart9";
 633                         clock-frequency = <48000000>;
 634                         status = "disabled";
 635                 };
 636
 637                 uart10: serial@4ae2b000 {
 638                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 639                         reg = <0x4ae2b000 0x100>;
 640                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 641                         ti,hwmods = "uart10";
 642                         clock-frequency = <48000000>;
 643                         status = "disabled";
 644                 };
 645
 646                 mailbox1: mailbox@4a0f4000 {
 647                         compatible = "ti,omap4-mailbox";
 648                         reg = <0x4a0f4000 0x200>;
 649                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 652                         ti,hwmods = "mailbox1";
 653                         #mbox-cells = <1>;
 654                         ti,mbox-num-users = <3>;
 655                         ti,mbox-num-fifos = <8>;
 656                         status = "disabled";
 657                 };
 658
 659                 mailbox2: mailbox@4883a000 {
 660                         compatible = "ti,omap4-mailbox";
 661                         reg = <0x4883a000 0x200>;
 662                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 664                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 665                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 666                         ti,hwmods = "mailbox2";
 667                         #mbox-cells = <1>;
 668                         ti,mbox-num-users = <4>;
 669                         ti,mbox-num-fifos = <12>;
 670                         status = "disabled";
 671                 };
 672
 673                 mailbox3: mailbox@4883c000 {
 674                         compatible = "ti,omap4-mailbox";
 675                         reg = <0x4883c000 0x200>;
 676                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 680                         ti,hwmods = "mailbox3";
 681                         #mbox-cells = <1>;
 682                         ti,mbox-num-users = <4>;
 683                         ti,mbox-num-fifos = <12>;
 684                         status = "disabled";
 685                 };
 686
 687                 mailbox4: mailbox@4883e000 {
 688                         compatible = "ti,omap4-mailbox";
 689                         reg = <0x4883e000 0x200>;
 690                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 694                         ti,hwmods = "mailbox4";
 695                         #mbox-cells = <1>;
 696                         ti,mbox-num-users = <4>;
 697                         ti,mbox-num-fifos = <12>;
 698                         status = "disabled";
 699                 };
 700
 701                 mailbox5: mailbox@48840000 {
 702                         compatible = "ti,omap4-mailbox";
 703                         reg = <0x48840000 0x200>;
 704                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 708                         ti,hwmods = "mailbox5";
 709                         #mbox-cells = <1>;
 710                         ti,mbox-num-users = <4>;
 711                         ti,mbox-num-fifos = <12>;
 712                         status = "disabled";
 713                 };
 714
 715                 mailbox6: mailbox@48842000 {
 716                         compatible = "ti,omap4-mailbox";
 717                         reg = <0x48842000 0x200>;
 718                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 719                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 721                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 722                         ti,hwmods = "mailbox6";
 723                         #mbox-cells = <1>;
 724                         ti,mbox-num-users = <4>;
 725                         ti,mbox-num-fifos = <12>;
 726                         status = "disabled";
 727                 };
 728
 729                 mailbox7: mailbox@48844000 {
 730                         compatible = "ti,omap4-mailbox";
 731                         reg = <0x48844000 0x200>;
 732                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 735                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 736                         ti,hwmods = "mailbox7";
 737                         #mbox-cells = <1>;
 738                         ti,mbox-num-users = <4>;
 739                         ti,mbox-num-fifos = <12>;
 740                         status = "disabled";
 741                 };
 742
 743                 mailbox8: mailbox@48846000 {
 744                         compatible = "ti,omap4-mailbox";
 745                         reg = <0x48846000 0x200>;
 746                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 750                         ti,hwmods = "mailbox8";
 751                         #mbox-cells = <1>;
 752                         ti,mbox-num-users = <4>;
 753                         ti,mbox-num-fifos = <12>;
 754                         status = "disabled";
 755                 };
 756
 757                 mailbox9: mailbox@4885e000 {
 758                         compatible = "ti,omap4-mailbox";
 759                         reg = <0x4885e000 0x200>;
 760                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 761                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 762                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 763                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 764                         ti,hwmods = "mailbox9";
 765                         #mbox-cells = <1>;
 766                         ti,mbox-num-users = <4>;
 767                         ti,mbox-num-fifos = <12>;
 768                         status = "disabled";
 769                 };
 770
 771                 mailbox10: mailbox@48860000 {
 772                         compatible = "ti,omap4-mailbox";
 773                         reg = <0x48860000 0x200>;
 774                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 775                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 776                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 777                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 778                         ti,hwmods = "mailbox10";
 779                         #mbox-cells = <1>;
 780                         ti,mbox-num-users = <4>;
 781                         ti,mbox-num-fifos = <12>;
 782                         status = "disabled";
 783                 };
 784
 785                 mailbox11: mailbox@48862000 {
 786                         compatible = "ti,omap4-mailbox";
 787                         reg = <0x48862000 0x200>;
 788                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 789                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 790                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 791                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 792                         ti,hwmods = "mailbox11";
 793                         #mbox-cells = <1>;
 794                         ti,mbox-num-users = <4>;
 795                         ti,mbox-num-fifos = <12>;
 796                         status = "disabled";
 797                 };
 798
 799                 mailbox12: mailbox@48864000 {
 800                         compatible = "ti,omap4-mailbox";
 801                         reg = <0x48864000 0x200>;
 802                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 803                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 804                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 805                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 806                         ti,hwmods = "mailbox12";
 807                         #mbox-cells = <1>;
 808                         ti,mbox-num-users = <4>;
 809                         ti,mbox-num-fifos = <12>;
 810                         status = "disabled";
 811                 };
 812
 813                 mailbox13: mailbox@48802000 {
 814                         compatible = "ti,omap4-mailbox";
 815                         reg = <0x48802000 0x200>;
 816                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 817                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 818                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 819                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 820                         ti,hwmods = "mailbox13";
 821                         #mbox-cells = <1>;
 822                         ti,mbox-num-users = <4>;
 823                         ti,mbox-num-fifos = <12>;
 824                         status = "disabled";
 825                 };
 826
 827                 timer1: timer@4ae18000 {
 828                         compatible = "ti,omap5430-timer";
 829                         reg = <0x4ae18000 0x80>;
 830                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 831                         ti,hwmods = "timer1";
 832                         ti,timer-alwon;
 833                 };
 834
 835                 timer2: timer@48032000 {
 836                         compatible = "ti,omap5430-timer";
 837                         reg = <0x48032000 0x80>;
 838                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 839                         ti,hwmods = "timer2";
 840                 };
 841
 842                 timer3: timer@48034000 {
 843                         compatible = "ti,omap5430-timer";
 844                         reg = <0x48034000 0x80>;
 845                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 846                         ti,hwmods = "timer3";
 847                 };
 848
 849                 timer4: timer@48036000 {
 850                         compatible = "ti,omap5430-timer";
 851                         reg = <0x48036000 0x80>;
 852                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 853                         ti,hwmods = "timer4";
 854                 };
 855
 856                 timer5: timer@48820000 {
 857                         compatible = "ti,omap5430-timer";
 858                         reg = <0x48820000 0x80>;
 859                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 860                         ti,hwmods = "timer5";
 861                 };
 862
 863                 timer6: timer@48822000 {
 864                         compatible = "ti,omap5430-timer";
 865                         reg = <0x48822000 0x80>;
 866                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 867                         ti,hwmods = "timer6";
 868                 };
 869
 870                 timer7: timer@48824000 {
 871                         compatible = "ti,omap5430-timer";
 872                         reg = <0x48824000 0x80>;
 873                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 874                         ti,hwmods = "timer7";
 875                 };
 876
 877                 timer8: timer@48826000 {
 878                         compatible = "ti,omap5430-timer";
 879                         reg = <0x48826000 0x80>;
 880                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 881                         ti,hwmods = "timer8";
 882                 };
 883
 884                 timer9: timer@4803e000 {
 885                         compatible = "ti,omap5430-timer";
 886                         reg = <0x4803e000 0x80>;
 887                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 888                         ti,hwmods = "timer9";
 889                 };
 890
 891                 timer10: timer@48086000 {
 892                         compatible = "ti,omap5430-timer";
 893                         reg = <0x48086000 0x80>;
 894                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 895                         ti,hwmods = "timer10";
 896                 };
 897
 898                 timer11: timer@48088000 {
 899                         compatible = "ti,omap5430-timer";
 900                         reg = <0x48088000 0x80>;
 901                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 902                         ti,hwmods = "timer11";
 903                 };
 904
 905                 timer12: timer@4ae20000 {
 906                         compatible = "ti,omap5430-timer";
 907                         reg = <0x4ae20000 0x80>;
 908                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 909                         ti,hwmods = "timer12";
 910                         ti,timer-alwon;
 911                         ti,timer-secure;
 912                 };
 913
 914                 timer13: timer@48828000 {
 915                         compatible = "ti,omap5430-timer";
 916                         reg = <0x48828000 0x80>;
 917                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 918                         ti,hwmods = "timer13";
 919                 };
 920
 921                 timer14: timer@4882a000 {
 922                         compatible = "ti,omap5430-timer";
 923                         reg = <0x4882a000 0x80>;
 924                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 925                         ti,hwmods = "timer14";
 926                 };
 927
 928                 timer15: timer@4882c000 {
 929                         compatible = "ti,omap5430-timer";
 930                         reg = <0x4882c000 0x80>;
 931                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 932                         ti,hwmods = "timer15";
 933                 };
 934
 935                 timer16: timer@4882e000 {
 936                         compatible = "ti,omap5430-timer";
 937                         reg = <0x4882e000 0x80>;
 938                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 939                         ti,hwmods = "timer16";
 940                 };
 941
 942                 wdt2: wdt@4ae14000 {
 943                         compatible = "ti,omap3-wdt";
 944                         reg = <0x4ae14000 0x80>;
 945                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 946                         ti,hwmods = "wd_timer2";
 947                 };
 948
 949                 hwspinlock: spinlock@4a0f6000 {
 950                         compatible = "ti,omap4-hwspinlock";
 951                         reg = <0x4a0f6000 0x1000>;
 952                         ti,hwmods = "spinlock";
 953                         #hwlock-cells = <1>;
 954                 };
 955
 956                 dmm@4e000000 {
 957                         compatible = "ti,omap5-dmm";
 958                         reg = <0x4e000000 0x800>;
 959                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 960                         ti,hwmods = "dmm";
 961                 };
 962
 963                 i2c1: i2c@48070000 {
 964                         compatible = "ti,omap4-i2c";
 965                         reg = <0x48070000 0x100>;
 966                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 967                         #address-cells = <1>;
 968                         #size-cells = <0>;
 969                         ti,hwmods = "i2c1";
 970                         status = "disabled";
 971                 };
 972
 973                 i2c2: i2c@48072000 {
 974                         compatible = "ti,omap4-i2c";
 975                         reg = <0x48072000 0x100>;
 976                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 977                         #address-cells = <1>;
 978                         #size-cells = <0>;
 979                         ti,hwmods = "i2c2";
 980                         status = "disabled";
 981                 };
 982
 983                 i2c3: i2c@48060000 {
 984                         compatible = "ti,omap4-i2c";
 985                         reg = <0x48060000 0x100>;
 986                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 987                         #address-cells = <1>;
 988                         #size-cells = <0>;
 989                         ti,hwmods = "i2c3";
 990                         status = "disabled";
 991                 };
 992
 993                 i2c4: i2c@4807a000 {
 994                         compatible = "ti,omap4-i2c";
 995                         reg = <0x4807a000 0x100>;
 996                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 997                         #address-cells = <1>;
 998                         #size-cells = <0>;
 999                         ti,hwmods = "i2c4";
1000                         status = "disabled";
1001                 };
1002
1003                 i2c5: i2c@4807c000 {
1004                         compatible = "ti,omap4-i2c";
1005                         reg = <0x4807c000 0x100>;
1006                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1007                         #address-cells = <1>;
1008                         #size-cells = <0>;
1009                         ti,hwmods = "i2c5";
1010                         status = "disabled";
1011                 };
1012
1013                 mmc1: mmc@4809c000 {
1014                         compatible = "ti,omap4-hsmmc";
1015                         reg = <0x4809c000 0x400>;
1016                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1017                         ti,hwmods = "mmc1";
1018                         ti,dual-volt;
1019                         ti,needs-special-reset;
1020                         dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1021                         dma-names = "tx", "rx";
1022                         status = "disabled";
1023                         pbias-supply = <&pbias_mmc_reg>;
1024                 };
1025
1026                 mmc2: mmc@480b4000 {
1027                         compatible = "ti,omap4-hsmmc";
1028                         reg = <0x480b4000 0x400>;
1029                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1030                         ti,hwmods = "mmc2";
1031                         ti,needs-special-reset;
1032                         dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1033                         dma-names = "tx", "rx";
1034                         status = "disabled";
1035                 };
1036
1037                 mmc3: mmc@480ad000 {
1038                         compatible = "ti,omap4-hsmmc";
1039                         reg = <0x480ad000 0x400>;
1040                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1041                         ti,hwmods = "mmc3";
1042                         ti,needs-special-reset;
1043                         dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1044                         dma-names = "tx", "rx";
1045                         status = "disabled";
1046                 };
1047
1048                 mmc4: mmc@480d1000 {
1049                         compatible = "ti,omap4-hsmmc";
1050                         reg = <0x480d1000 0x400>;
1051                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1052                         ti,hwmods = "mmc4";
1053                         ti,needs-special-reset;
1054                         dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1055                         dma-names = "tx", "rx";
1056                         status = "disabled";
1057                 };
1058
1059                 mmu0_dsp1: mmu@40d01000 {
1060                         compatible = "ti,dra7-dsp-iommu";
1061                         reg = <0x40d01000 0x100>;
1062                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1063                         ti,hwmods = "mmu0_dsp1";
1064                         #iommu-cells = <0>;
1065                         ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1066                         status = "disabled";
1067                 };
1068
1069                 mmu1_dsp1: mmu@40d02000 {
1070                         compatible = "ti,dra7-dsp-iommu";
1071                         reg = <0x40d02000 0x100>;
1072                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1073                         ti,hwmods = "mmu1_dsp1";
1074                         #iommu-cells = <0>;
1075                         ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1076                         status = "disabled";
1077                 };
1078
1079                 mmu_ipu1: mmu@58882000 {
1080                         compatible = "ti,dra7-iommu";
1081                         reg = <0x58882000 0x100>;
1082                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1083                         ti,hwmods = "mmu_ipu1";
1084                         #iommu-cells = <0>;
1085                         ti,iommu-bus-err-back;
1086                         status = "disabled";
1087                 };
1088
1089                 mmu_ipu2: mmu@55082000 {
1090                         compatible = "ti,dra7-iommu";
1091                         reg = <0x55082000 0x100>;
1092                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1093                         ti,hwmods = "mmu_ipu2";
1094                         #iommu-cells = <0>;
1095                         ti,iommu-bus-err-back;
1096                         status = "disabled";
1097                 };
1098
1099                 abb_mpu: regulator-abb-mpu {
1100                         compatible = "ti,abb-v3";
1101                         regulator-name = "abb_mpu";
1102                         #address-cells = <0>;
1103                         #size-cells = <0>;
1104                         clocks = <&sys_clkin1>;
1105                         ti,settling-time = <50>;
1106                         ti,clock-cycles = <16>;
1107
1108                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1109                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1110                               <0x4ae0c158 0x4>;
1111                         reg-names = "setup-address", "control-address",
1112                                     "int-address", "efuse-address",
1113                                     "ldo-address";
1114                         ti,tranxdone-status-mask = <0x80>;
1115                         /* LDOVBBMPU_FBB_MUX_CTRL */
1116                         ti,ldovbb-override-mask = <0x400>;
1117                         /* LDOVBBMPU_FBB_VSET_OUT */
1118                         ti,ldovbb-vset-mask = <0x1F>;
1119
1120                         /*
1121                          * NOTE: only FBB mode used but actual vset will
1122                          * determine final biasing
1123                          */
1124                         ti,abb_info = <
1125                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1126                         1060000         0       0x0     0 0x02000000 0x01F00000
1127                         1160000         0       0x4     0 0x02000000 0x01F00000
1128                         1210000         0       0x8     0 0x02000000 0x01F00000
1129                         >;
1130                 };
1131
1132                 abb_ivahd: regulator-abb-ivahd {
1133                         compatible = "ti,abb-v3";
1134                         regulator-name = "abb_ivahd";
1135                         #address-cells = <0>;
1136                         #size-cells = <0>;
1137                         clocks = <&sys_clkin1>;
1138                         ti,settling-time = <50>;
1139                         ti,clock-cycles = <16>;
1140
1141                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1142                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1143                               <0x4a002470 0x4>;
1144                         reg-names = "setup-address", "control-address",
1145                                     "int-address", "efuse-address",
1146                                     "ldo-address";
1147                         ti,tranxdone-status-mask = <0x40000000>;
1148                         /* LDOVBBIVA_FBB_MUX_CTRL */
1149                         ti,ldovbb-override-mask = <0x400>;
1150                         /* LDOVBBIVA_FBB_VSET_OUT */
1151                         ti,ldovbb-vset-mask = <0x1F>;
1152
1153                         /*
1154                          * NOTE: only FBB mode used but actual vset will
1155                          * determine final biasing
1156                          */
1157                         ti,abb_info = <
1158                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1159                         1055000         0       0x0     0 0x02000000 0x01F00000
1160                         1150000         0       0x4     0 0x02000000 0x01F00000
1161                         1250000         0       0x8     0 0x02000000 0x01F00000
1162                         >;
1163                 };
1164
1165                 abb_dspeve: regulator-abb-dspeve {
1166                         compatible = "ti,abb-v3";
1167                         regulator-name = "abb_dspeve";
1168                         #address-cells = <0>;
1169                         #size-cells = <0>;
1170                         clocks = <&sys_clkin1>;
1171                         ti,settling-time = <50>;
1172                         ti,clock-cycles = <16>;
1173
1174                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1175                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1176                               <0x4a00246c 0x4>;
1177                         reg-names = "setup-address", "control-address",
1178                                     "int-address", "efuse-address",
1179                                     "ldo-address";
1180                         ti,tranxdone-status-mask = <0x20000000>;
1181                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1182                         ti,ldovbb-override-mask = <0x400>;
1183                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
1184                         ti,ldovbb-vset-mask = <0x1F>;
1185
1186                         /*
1187                          * NOTE: only FBB mode used but actual vset will
1188                          * determine final biasing
1189                          */
1190                         ti,abb_info = <
1191                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1192                         1055000         0       0x0     0 0x02000000 0x01F00000
1193                         1150000         0       0x4     0 0x02000000 0x01F00000
1194                         1250000         0       0x8     0 0x02000000 0x01F00000
1195                         >;
1196                 };
1197
1198                 abb_gpu: regulator-abb-gpu {
1199                         compatible = "ti,abb-v3";
1200                         regulator-name = "abb_gpu";
1201                         #address-cells = <0>;
1202                         #size-cells = <0>;
1203                         clocks = <&sys_clkin1>;
1204                         ti,settling-time = <50>;
1205                         ti,clock-cycles = <16>;
1206
1207                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1208                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1209                               <0x4ae0c154 0x4>;
1210                         reg-names = "setup-address", "control-address",
1211                                     "int-address", "efuse-address",
1212                                     "ldo-address";
1213                         ti,tranxdone-status-mask = <0x10000000>;
1214                         /* LDOVBBGPU_FBB_MUX_CTRL */
1215                         ti,ldovbb-override-mask = <0x400>;
1216                         /* LDOVBBGPU_FBB_VSET_OUT */
1217                         ti,ldovbb-vset-mask = <0x1F>;
1218
1219                         /*
1220                          * NOTE: only FBB mode used but actual vset will
1221                          * determine final biasing
1222                          */
1223                         ti,abb_info = <
1224                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1225                         1090000         0       0x0     0 0x02000000 0x01F00000
1226                         1210000         0       0x4     0 0x02000000 0x01F00000
1227                         1280000         0       0x8     0 0x02000000 0x01F00000
1228                         >;
1229                 };
1230
1231                 mcspi1: spi@48098000 {
1232                         compatible = "ti,omap4-mcspi";
1233                         reg = <0x48098000 0x200>;
1234                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1235                         #address-cells = <1>;
1236                         #size-cells = <0>;
1237                         ti,hwmods = "mcspi1";
1238                         ti,spi-num-cs = <4>;
1239                         dmas = <&sdma_xbar 35>,
1240                                <&sdma_xbar 36>,
1241                                <&sdma_xbar 37>,
1242                                <&sdma_xbar 38>,
1243                                <&sdma_xbar 39>,
1244                                <&sdma_xbar 40>,
1245                                <&sdma_xbar 41>,
1246                                <&sdma_xbar 42>;
1247                         dma-names = "tx0", "rx0", "tx1", "rx1",
1248                                     "tx2", "rx2", "tx3", "rx3";
1249                         status = "disabled";
1250                 };
1251
1252                 mcspi2: spi@4809a000 {
1253                         compatible = "ti,omap4-mcspi";
1254                         reg = <0x4809a000 0x200>;
1255                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1256                         #address-cells = <1>;
1257                         #size-cells = <0>;
1258                         ti,hwmods = "mcspi2";
1259                         ti,spi-num-cs = <2>;
1260                         dmas = <&sdma_xbar 43>,
1261                                <&sdma_xbar 44>,
1262                                <&sdma_xbar 45>,
1263                                <&sdma_xbar 46>;
1264                         dma-names = "tx0", "rx0", "tx1", "rx1";
1265                         status = "disabled";
1266                 };
1267
1268                 mcspi3: spi@480b8000 {
1269                         compatible = "ti,omap4-mcspi";
1270                         reg = <0x480b8000 0x200>;
1271                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1272                         #address-cells = <1>;
1273                         #size-cells = <0>;
1274                         ti,hwmods = "mcspi3";
1275                         ti,spi-num-cs = <2>;
1276                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1277                         dma-names = "tx0", "rx0";
1278                         status = "disabled";
1279                 };
1280
1281                 mcspi4: spi@480ba000 {
1282                         compatible = "ti,omap4-mcspi";
1283                         reg = <0x480ba000 0x200>;
1284                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1285                         #address-cells = <1>;
1286                         #size-cells = <0>;
1287                         ti,hwmods = "mcspi4";
1288                         ti,spi-num-cs = <1>;
1289                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1290                         dma-names = "tx0", "rx0";
1291                         status = "disabled";
1292                 };
1293
1294                 qspi: qspi@4b300000 {
1295                         compatible = "ti,dra7xxx-qspi";
1296                         reg = <0x4b300000 0x100>,
1297                               <0x5c000000 0x4000000>;
1298                         reg-names = "qspi_base", "qspi_mmap";
1299                         syscon-chipselects = <&scm_conf 0x558>;
1300                         #address-cells = <1>;
1301                         #size-cells = <0>;
1302                         ti,hwmods = "qspi";
1303                         clocks = <&qspi_gfclk_div>;
1304                         clock-names = "fck";
1305                         num-cs = <4>;
1306                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1307                         status = "disabled";
1308                 };
1309
1310                 /* OCP2SCP3 */
1311                 ocp2scp@4a090000 {
1312                         compatible = "ti,omap-ocp2scp";
1313                         #address-cells = <1>;
1314                         #size-cells = <1>;
1315                         ranges;
1316                         reg = <0x4a090000 0x20>;
1317                         ti,hwmods = "ocp2scp3";
1318                         sata_phy: phy@4A096000 {
1319                                 compatible = "ti,phy-pipe3-sata";
1320                                 reg = <0x4A096000 0x80>, /* phy_rx */
1321                                       <0x4A096400 0x64>, /* phy_tx */
1322                                       <0x4A096800 0x40>; /* pll_ctrl */
1323                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1324                                 syscon-phy-power = <&scm_conf 0x374>;
1325                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1326                                 clock-names = "sysclk", "refclk";
1327                                 syscon-pllreset = <&scm_conf 0x3fc>;
1328                                 #phy-cells = <0>;
1329                         };
1330
1331                         pcie1_phy: pciephy@4a094000 {
1332                                 compatible = "ti,phy-pipe3-pcie";
1333                                 reg = <0x4a094000 0x80>, /* phy_rx */
1334                                       <0x4a094400 0x64>; /* phy_tx */
1335                                 reg-names = "phy_rx", "phy_tx";
1336                                 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1337                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1338                                 clocks = <&dpll_pcie_ref_ck>,
1339                                          <&dpll_pcie_ref_m2ldo_ck>,
1340                                          <&optfclk_pciephy1_32khz>,
1341                                          <&optfclk_pciephy1_clk>,
1342                                          <&optfclk_pciephy1_div_clk>,
1343                                          <&optfclk_pciephy_div>,
1344                                          <&sys_clkin1>;
1345                                 clock-names = "dpll_ref", "dpll_ref_m2",
1346                                               "wkupclk", "refclk",
1347                                               "div-clk", "phy-div", "sysclk";
1348                                 #phy-cells = <0>;
1349                         };
1350
1351                         pcie2_phy: pciephy@4a095000 {
1352                                 compatible = "ti,phy-pipe3-pcie";
1353                                 reg = <0x4a095000 0x80>, /* phy_rx */
1354                                       <0x4a095400 0x64>; /* phy_tx */
1355                                 reg-names = "phy_rx", "phy_tx";
1356                                 syscon-phy-power = <&scm_conf_pcie 0x20>;
1357                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1358                                 clocks = <&dpll_pcie_ref_ck>,
1359                                          <&dpll_pcie_ref_m2ldo_ck>,
1360                                          <&optfclk_pciephy2_32khz>,
1361                                          <&optfclk_pciephy2_clk>,
1362                                          <&optfclk_pciephy2_div_clk>,
1363                                          <&optfclk_pciephy_div>,
1364                                          <&sys_clkin1>;
1365                                 clock-names = "dpll_ref", "dpll_ref_m2",
1366                                               "wkupclk", "refclk",
1367                                               "div-clk", "phy-div", "sysclk";
1368                                 #phy-cells = <0>;
1369                                 status = "disabled";
1370                         };
1371                 };
1372
1373                 sata: sata@4a141100 {
1374                         compatible = "snps,dwc-ahci";
1375                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1376                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1377                         phys = <&sata_phy>;
1378                         phy-names = "sata-phy";
1379                         clocks = <&sata_ref_clk>;
1380                         ti,hwmods = "sata";
1381                         ports-implemented = <0x1>;
1382                 };
1383
1384                 rtc: rtc@48838000 {
1385                         compatible = "ti,am3352-rtc";
1386                         reg = <0x48838000 0x100>;
1387                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1388                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1389                         ti,hwmods = "rtcss";
1390                         clocks = <&sys_32k_ck>;
1391                 };
1392
1393                 /* OCP2SCP1 */
1394                 ocp2scp@4a080000 {
1395                         compatible = "ti,omap-ocp2scp";
1396                         #address-cells = <1>;
1397                         #size-cells = <1>;
1398                         ranges;
1399                         reg = <0x4a080000 0x20>;
1400                         ti,hwmods = "ocp2scp1";
1401
1402                         usb2_phy1: phy@4a084000 {
1403                                 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1404                                 reg = <0x4a084000 0x400>;
1405                                 syscon-phy-power = <&scm_conf 0x300>;
1406                                 clocks = <&usb_phy1_always_on_clk32k>,
1407                                          <&usb_otg_ss1_refclk960m>;
1408                                 clock-names =   "wkupclk",
1409                                                 "refclk";
1410                                 #phy-cells = <0>;
1411                         };
1412
1413                         usb2_phy2: phy@4a085000 {
1414                                 compatible = "ti,dra7x-usb2-phy2",
1415                                              "ti,omap-usb2";
1416                                 reg = <0x4a085000 0x400>;
1417                                 syscon-phy-power = <&scm_conf 0xe74>;
1418                                 clocks = <&usb_phy2_always_on_clk32k>,
1419                                          <&usb_otg_ss2_refclk960m>;
1420                                 clock-names =   "wkupclk",
1421                                                 "refclk";
1422                                 #phy-cells = <0>;
1423                         };
1424
1425                         usb3_phy1: phy@4a084400 {
1426                                 compatible = "ti,omap-usb3";
1427                                 reg = <0x4a084400 0x80>,
1428                                       <0x4a084800 0x64>,
1429                                       <0x4a084c00 0x40>;
1430                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1431                                 syscon-phy-power = <&scm_conf 0x370>;
1432                                 clocks = <&usb_phy3_always_on_clk32k>,
1433                                          <&sys_clkin1>,
1434                                          <&usb_otg_ss1_refclk960m>;
1435                                 clock-names =   "wkupclk",
1436                                                 "sysclk",
1437                                                 "refclk";
1438                                 #phy-cells = <0>;
1439                         };
1440                 };
1441
1442                 omap_dwc3_1: omap_dwc3_1@48880000 {
1443                         compatible = "ti,dwc3";
1444                         ti,hwmods = "usb_otg_ss1";
1445                         reg = <0x48880000 0x10000>;
1446                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1447                         #address-cells = <1>;
1448                         #size-cells = <1>;
1449                         utmi-mode = <2>;
1450                         ranges;
1451                         usb1: usb@48890000 {
1452                                 compatible = "snps,dwc3";
1453                                 reg = <0x48890000 0x17000>;
1454                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1455                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1456                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1457                                 interrupt-names = "peripheral",
1458                                                   "host",
1459                                                   "otg";
1460                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1461                                 phy-names = "usb2-phy", "usb3-phy";
1462                                 maximum-speed = "super-speed";
1463                                 dr_mode = "otg";
1464                                 snps,dis_u3_susphy_quirk;
1465                                 snps,dis_u2_susphy_quirk;
1466                         };
1467                 };
1468
1469                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1470                         compatible = "ti,dwc3";
1471                         ti,hwmods = "usb_otg_ss2";
1472                         reg = <0x488c0000 0x10000>;
1473                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1474                         #address-cells = <1>;
1475                         #size-cells = <1>;
1476                         utmi-mode = <2>;
1477                         ranges;
1478                         usb2: usb@488d0000 {
1479                                 compatible = "snps,dwc3";
1480                                 reg = <0x488d0000 0x17000>;
1481                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1482                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1483                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1484                                 interrupt-names = "peripheral",
1485                                                   "host",
1486                                                   "otg";
1487                                 phys = <&usb2_phy2>;
1488                                 phy-names = "usb2-phy";
1489                                 maximum-speed = "high-speed";
1490                                 dr_mode = "otg";
1491                                 snps,dis_u3_susphy_quirk;
1492                                 snps,dis_u2_susphy_quirk;
1493                         };
1494                 };
1495
1496                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1497                 omap_dwc3_3: omap_dwc3_3@48900000 {
1498                         compatible = "ti,dwc3";
1499                         ti,hwmods = "usb_otg_ss3";
1500                         reg = <0x48900000 0x10000>;
1501                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1502                         #address-cells = <1>;
1503                         #size-cells = <1>;
1504                         utmi-mode = <2>;
1505                         ranges;
1506                         status = "disabled";
1507                         usb3: usb@48910000 {
1508                                 compatible = "snps,dwc3";
1509                                 reg = <0x48910000 0x17000>;
1510                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1511                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1512                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1513                                 interrupt-names = "peripheral",
1514                                                   "host",
1515                                                   "otg";
1516                                 maximum-speed = "high-speed";
1517                                 dr_mode = "otg";
1518                                 snps,dis_u3_susphy_quirk;
1519                                 snps,dis_u2_susphy_quirk;
1520                         };
1521                 };
1522
1523                 elm: elm@48078000 {
1524                         compatible = "ti,am3352-elm";
1525                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1526                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1527                         ti,hwmods = "elm";
1528                         status = "disabled";
1529                 };
1530
1531                 gpmc: gpmc@50000000 {
1532                         compatible = "ti,am3352-gpmc";
1533                         ti,hwmods = "gpmc";
1534                         reg = <0x50000000 0x37c>;      /* device IO registers */
1535                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1536                         dmas = <&edma_xbar 4 0>;
1537                         dma-names = "rxtx";
1538                         gpmc,num-cs = <8>;
1539                         gpmc,num-waitpins = <2>;
1540                         #address-cells = <2>;
1541                         #size-cells = <1>;
1542                         interrupt-controller;
1543                         #interrupt-cells = <2>;
1544                         gpio-controller;
1545                         #gpio-cells = <2>;
1546                         status = "disabled";
1547                 };
1548
1549                 atl: atl@4843c000 {
1550                         compatible = "ti,dra7-atl";
1551                         reg = <0x4843c000 0x3ff>;
1552                         ti,hwmods = "atl";
1553                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1554                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1555                         clocks = <&atl_gfclk_mux>;
1556                         clock-names = "fck";
1557                         status = "disabled";
1558                 };
1559
1560                 mcasp1: mcasp@48460000 {
1561                         compatible = "ti,dra7-mcasp-audio";
1562                         ti,hwmods = "mcasp1";
1563                         reg = <0x48460000 0x2000>,
1564                               <0x45800000 0x1000>;
1565                         reg-names = "mpu","dat";
1566                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1567                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1568                         interrupt-names = "tx", "rx";
1569                         dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1570                         dma-names = "tx", "rx";
1571                         clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1572                                  <&mcasp1_ahclkr_mux>;
1573                         clock-names = "fck", "ahclkx", "ahclkr";
1574                         status = "disabled";
1575                 };
1576
1577                 mcasp2: mcasp@48464000 {
1578                         compatible = "ti,dra7-mcasp-audio";
1579                         ti,hwmods = "mcasp2";
1580                         reg = <0x48464000 0x2000>,
1581                               <0x45c00000 0x1000>;
1582                         reg-names = "mpu","dat";
1583                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1584                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1585                         interrupt-names = "tx", "rx";
1586                         dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1587                         dma-names = "tx", "rx";
1588                         clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1589                                  <&mcasp2_ahclkr_mux>;
1590                         clock-names = "fck", "ahclkx", "ahclkr";
1591                         status = "disabled";
1592                 };
1593
1594                 mcasp3: mcasp@48468000 {
1595                         compatible = "ti,dra7-mcasp-audio";
1596                         ti,hwmods = "mcasp3";
1597                         reg = <0x48468000 0x2000>,
1598                               <0x46000000 0x1000>;
1599                         reg-names = "mpu","dat";
1600                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1601                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1602                         interrupt-names = "tx", "rx";
1603                         dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1604                         dma-names = "tx", "rx";
1605                         clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1606                         clock-names = "fck", "ahclkx";
1607                         status = "disabled";
1608                 };
1609
1610                 mcasp4: mcasp@4846c000 {
1611                         compatible = "ti,dra7-mcasp-audio";
1612                         ti,hwmods = "mcasp4";
1613                         reg = <0x4846c000 0x2000>,
1614                               <0x48436000 0x1000>;
1615                         reg-names = "mpu","dat";
1616                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1617                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1618                         interrupt-names = "tx", "rx";
1619                         dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1620                         dma-names = "tx", "rx";
1621                         clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1622                         clock-names = "fck", "ahclkx";
1623                         status = "disabled";
1624                 };
1625
1626                 mcasp5: mcasp@48470000 {
1627                         compatible = "ti,dra7-mcasp-audio";
1628                         ti,hwmods = "mcasp5";
1629                         reg = <0x48470000 0x2000>,
1630                               <0x4843a000 0x1000>;
1631                         reg-names = "mpu","dat";
1632                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1633                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1634                         interrupt-names = "tx", "rx";
1635                         dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1636                         dma-names = "tx", "rx";
1637                         clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1638                         clock-names = "fck", "ahclkx";
1639                         status = "disabled";
1640                 };
1641
1642                 mcasp6: mcasp@48474000 {
1643                         compatible = "ti,dra7-mcasp-audio";
1644                         ti,hwmods = "mcasp6";
1645                         reg = <0x48474000 0x2000>,
1646                               <0x4844c000 0x1000>;
1647                         reg-names = "mpu","dat";
1648                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1649                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1650                         interrupt-names = "tx", "rx";
1651                         dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1652                         dma-names = "tx", "rx";
1653                         clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1654                         clock-names = "fck", "ahclkx";
1655                         status = "disabled";
1656                 };
1657
1658                 mcasp7: mcasp@48478000 {
1659                         compatible = "ti,dra7-mcasp-audio";
1660                         ti,hwmods = "mcasp7";
1661                         reg = <0x48478000 0x2000>,
1662                               <0x48450000 0x1000>;
1663                         reg-names = "mpu","dat";
1664                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1665                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1666                         interrupt-names = "tx", "rx";
1667                         dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1668                         dma-names = "tx", "rx";
1669                         clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1670                         clock-names = "fck", "ahclkx";
1671                         status = "disabled";
1672                 };
1673
1674                 mcasp8: mcasp@4847c000 {
1675                         compatible = "ti,dra7-mcasp-audio";
1676                         ti,hwmods = "mcasp8";
1677                         reg = <0x4847c000 0x2000>,
1678                               <0x48454000 0x1000>;
1679                         reg-names = "mpu","dat";
1680                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1681                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1682                         interrupt-names = "tx", "rx";
1683                         dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1684                         dma-names = "tx", "rx";
1685                         clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1686                         clock-names = "fck", "ahclkx";
1687                         status = "disabled";
1688                 };
1689
1690                 crossbar_mpu: crossbar@4a002a48 {
1691                         compatible = "ti,irq-crossbar";
1692                         reg = <0x4a002a48 0x130>;
1693                         interrupt-controller;
1694                         interrupt-parent = <&wakeupgen>;
1695                         #interrupt-cells = <3>;
1696                         ti,max-irqs = <160>;
1697                         ti,max-crossbar-sources = <MAX_SOURCES>;
1698                         ti,reg-size = <2>;
1699                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1700                         ti,irqs-skip = <10 133 139 140>;
1701                         ti,irqs-safe-map = <0>;
1702                 };
1703
1704                 mac: ethernet@48484000 {
1705                         compatible = "ti,dra7-cpsw","ti,cpsw";
1706                         ti,hwmods = "gmac";
1707                         clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1708                         clock-names = "fck", "cpts";
1709                         cpdma_channels = <8>;
1710                         ale_entries = <1024>;
1711                         bd_ram_size = <0x2000>;
1712                         mac_control = <0x20>;
1713                         slaves = <2>;
1714                         active_slave = <0>;
1715                         cpts_clock_mult = <0x784CFE14>;
1716                         cpts_clock_shift = <29>;
1717                         reg = <0x48484000 0x1000
1718                                0x48485200 0x2E00>;
1719                         #address-cells = <1>;
1720                         #size-cells = <1>;
1721
1722                         /*
1723                          * Do not allow gating of cpsw clock as workaround
1724                          * for errata i877. Keeping internal clock disabled
1725                          * causes the device switching characteristics
1726                          * to degrade over time and eventually fail to meet
1727                          * the data manual delay time/skew specs.
1728                          */
1729                         ti,no-idle;
1730
1731                         /*
1732                          * rx_thresh_pend
1733                          * rx_pend
1734                          * tx_pend
1735                          * misc_pend
1736                          */
1737                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1738                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1739                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1740                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1741                         ranges;
1742                         syscon = <&scm_conf>;
1743                         status = "disabled";
1744
1745                         davinci_mdio: mdio@48485000 {
1746                                 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1747                                 #address-cells = <1>;
1748                                 #size-cells = <0>;
1749                                 ti,hwmods = "davinci_mdio";
1750                                 bus_freq = <1000000>;
1751                                 reg = <0x48485000 0x100>;
1752                         };
1753
1754                         cpsw_emac0: slave@48480200 {
1755                                 /* Filled in by U-Boot */
1756                                 mac-address = [ 00 00 00 00 00 00 ];
1757                         };
1758
1759                         cpsw_emac1: slave@48480300 {
1760                                 /* Filled in by U-Boot */
1761                                 mac-address = [ 00 00 00 00 00 00 ];
1762                         };
1763
1764                         phy_sel: cpsw-phy-sel@4a002554 {
1765                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1766                                 reg= <0x4a002554 0x4>;
1767                                 reg-names = "gmii-sel";
1768                         };
1769                 };
1770
1771                 dcan1: can@481cc000 {
1772                         compatible = "ti,dra7-d_can";
1773                         ti,hwmods = "dcan1";
1774                         reg = <0x4ae3c000 0x2000>;
1775                         syscon-raminit = <&scm_conf 0x558 0>;
1776                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1777                         clocks = <&dcan1_sys_clk_mux>;
1778                         status = "disabled";
1779                 };
1780
1781                 dcan2: can@481d0000 {
1782                         compatible = "ti,dra7-d_can";
1783                         ti,hwmods = "dcan2";
1784                         reg = <0x48480000 0x2000>;
1785                         syscon-raminit = <&scm_conf 0x558 1>;
1786                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1787                         clocks = <&sys_clkin1>;
1788                         status = "disabled";
1789                 };
1790
1791                 dss: dss@58000000 {
1792                         compatible = "ti,dra7-dss";
1793                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1794                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1795                         status = "disabled";
1796                         ti,hwmods = "dss_core";
1797                         /* CTRL_CORE_DSS_PLL_CONTROL */
1798                         syscon-pll-ctrl = <&scm_conf 0x538>;
1799                         #address-cells = <1>;
1800                         #size-cells = <1>;
1801                         ranges;
1802
1803                         dispc@58001000 {
1804                                 compatible = "ti,dra7-dispc";
1805                                 reg = <0x58001000 0x1000>;
1806                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1807                                 ti,hwmods = "dss_dispc";
1808                                 clocks = <&dss_dss_clk>;
1809                                 clock-names = "fck";
1810                                 /* CTRL_CORE_SMA_SW_1 */
1811                                 syscon-pol = <&scm_conf 0x534>;
1812                         };
1813
1814                         hdmi: encoder@58060000 {
1815                                 compatible = "ti,dra7-hdmi";
1816                                 reg = <0x58040000 0x200>,
1817                                       <0x58040200 0x80>,
1818                                       <0x58040300 0x80>,
1819                                       <0x58060000 0x19000>;
1820                                 reg-names = "wp", "pll", "phy", "core";
1821                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1822                                 status = "disabled";
1823                                 ti,hwmods = "dss_hdmi";
1824                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1825                                 clock-names = "fck", "sys_clk";
1826                         };
1827                 };
1828
1829                 epwmss0: epwmss@4843e000 {
1830                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1831                         reg = <0x4843e000 0x30>;
1832                         ti,hwmods = "epwmss0";
1833                         #address-cells = <1>;
1834                         #size-cells = <1>;
1835                         status = "disabled";
1836                         ranges;
1837
1838                         ehrpwm0: pwm@4843e200 {
1839                                 compatible = "ti,dra746-ehrpwm",
1840                                              "ti,am3352-ehrpwm";
1841                                 #pwm-cells = <3>;
1842                                 reg = <0x4843e200 0x80>;
1843                                 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1844                                 clock-names = "tbclk", "fck";
1845                                 status = "disabled";
1846                         };
1847
1848                         ecap0: ecap@4843e100 {
1849                                 compatible = "ti,dra746-ecap",
1850                                              "ti,am3352-ecap";
1851                                 #pwm-cells = <3>;
1852                                 reg = <0x4843e100 0x80>;
1853                                 clocks = <&l4_root_clk_div>;
1854                                 clock-names = "fck";
1855                                 status = "disabled";
1856                         };
1857                 };
1858
1859                 epwmss1: epwmss@48440000 {
1860                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1861                         reg = <0x48440000 0x30>;
1862                         ti,hwmods = "epwmss1";
1863                         #address-cells = <1>;
1864                         #size-cells = <1>;
1865                         status = "disabled";
1866                         ranges;
1867
1868                         ehrpwm1: pwm@48440200 {
1869                                 compatible = "ti,dra746-ehrpwm",
1870                                              "ti,am3352-ehrpwm";
1871                                 #pwm-cells = <3>;
1872                                 reg = <0x48440200 0x80>;
1873                                 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1874                                 clock-names = "tbclk", "fck";
1875                                 status = "disabled";
1876                         };
1877
1878                         ecap1: ecap@48440100 {
1879                                 compatible = "ti,dra746-ecap",
1880                                              "ti,am3352-ecap";
1881                                 #pwm-cells = <3>;
1882                                 reg = <0x48440100 0x80>;
1883                                 clocks = <&l4_root_clk_div>;
1884                                 clock-names = "fck";
1885                                 status = "disabled";
1886                         };
1887                 };
1888
1889                 epwmss2: epwmss@48442000 {
1890                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1891                         reg = <0x48442000 0x30>;
1892                         ti,hwmods = "epwmss2";
1893                         #address-cells = <1>;
1894                         #size-cells = <1>;
1895                         status = "disabled";
1896                         ranges;
1897
1898                         ehrpwm2: pwm@48442200 {
1899                                 compatible = "ti,dra746-ehrpwm",
1900                                              "ti,am3352-ehrpwm";
1901                                 #pwm-cells = <3>;
1902                                 reg = <0x48442200 0x80>;
1903                                 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1904                                 clock-names = "tbclk", "fck";
1905                                 status = "disabled";
1906                         };
1907
1908                         ecap2: ecap@48442100 {
1909                                 compatible = "ti,dra746-ecap",
1910                                              "ti,am3352-ecap";
1911                                 #pwm-cells = <3>;
1912                                 reg = <0x48442100 0x80>;
1913                                 clocks = <&l4_root_clk_div>;
1914                                 clock-names = "fck";
1915                                 status = "disabled";
1916                         };
1917                 };
1918
1919                 aes1: aes@4b500000 {
1920                         compatible = "ti,omap4-aes";
1921                         ti,hwmods = "aes1";
1922                         reg = <0x4b500000 0xa0>;
1923                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1924                         dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1925                         dma-names = "tx", "rx";
1926                         clocks = <&l3_iclk_div>;
1927                         clock-names = "fck";
1928                 };
1929
1930                 aes2: aes@4b700000 {
1931                         compatible = "ti,omap4-aes";
1932                         ti,hwmods = "aes2";
1933                         reg = <0x4b700000 0xa0>;
1934                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1935                         dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1936                         dma-names = "tx", "rx";
1937                         clocks = <&l3_iclk_div>;
1938                         clock-names = "fck";
1939                 };
1940
1941                 des: des@480a5000 {
1942                         compatible = "ti,omap4-des";
1943                         ti,hwmods = "des";
1944                         reg = <0x480a5000 0xa0>;
1945                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1946                         dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1947                         dma-names = "tx", "rx";
1948                         clocks = <&l3_iclk_div>;
1949                         clock-names = "fck";
1950                 };
1951
1952                 sham: sham@53100000 {
1953                         compatible = "ti,omap5-sham";
1954                         ti,hwmods = "sham";
1955                         reg = <0x4b101000 0x300>;
1956                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1957                         dmas = <&edma_xbar 119 0>;
1958                         dma-names = "rx";
1959                         clocks = <&l3_iclk_div>;
1960                         clock-names = "fck";
1961                 };
1962
1963                 rng: rng@48090000 {
1964                         compatible = "ti,omap4-rng";
1965                         ti,hwmods = "rng";
1966                         reg = <0x48090000 0x2000>;
1967                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1968                         clocks = <&l3_iclk_div>;
1969                         clock-names = "fck";
1970                 };
1971         };
1972
1973         thermal_zones: thermal-zones {
1974                 #include "omap4-cpu-thermal.dtsi"
1975                 #include "omap5-gpu-thermal.dtsi"
1976                 #include "omap5-core-thermal.dtsi"
1977                 #include "dra7-dspeve-thermal.dtsi"
1978                 #include "dra7-iva-thermal.dtsi"
1979         };
1980
1981 };
1982
1983 &cpu_thermal {
1984         polling-delay = <500>; /* milliseconds */
1985 };
1986
1987 /include/ "dra7xx-clocks.dtsi"