arch/arm/boot/dts/highbank.dts

   1 /*
   2  * Copyright 2011-2012 Calxeda, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 /dts-v1/;
  18
  19 /* First 4KB has pen for secondary cores. */
  20 /memreserve/ 0x00000000 0x0001000;
  21
  22 / {
  23         model = "Calxeda Highbank";
  24         compatible = "calxeda,highbank";
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27         clock-ranges;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@900 {
  34                         compatible = "arm,cortex-a9";
  35                         device_type = "cpu";
  36                         reg = <0x900>;
  37                         next-level-cache = <&L2>;
  38                         clocks = <&a9pll>;
  39                         clock-names = "cpu";
  40                 };
  41
  42                 cpu@901 {
  43                         compatible = "arm,cortex-a9";
  44                         device_type = "cpu";
  45                         reg = <0x901>;
  46                         next-level-cache = <&L2>;
  47                         clocks = <&a9pll>;
  48                         clock-names = "cpu";
  49                 };
  50
  51                 cpu@902 {
  52                         compatible = "arm,cortex-a9";
  53                         device_type = "cpu";
  54                         reg = <0x902>;
  55                         next-level-cache = <&L2>;
  56                         clocks = <&a9pll>;
  57                         clock-names = "cpu";
  58                 };
  59
  60                 cpu@903 {
  61                         compatible = "arm,cortex-a9";
  62                         device_type = "cpu";
  63                         reg = <0x903>;
  64                         next-level-cache = <&L2>;
  65                         clocks = <&a9pll>;
  66                         clock-names = "cpu";
  67                 };
  68         };
  69
  70         memory {
  71                 name = "memory";
  72                 device_type = "memory";
  73                 reg = <0x00000000 0xff900000>;
  74         };
  75
  76         soc {
  77                 ranges = <0x00000000 0x00000000 0xffffffff>;
  78
  79                 timer@fff10600 {
  80                         compatible = "arm,cortex-a9-twd-timer";
  81                         reg = <0xfff10600 0x20>;
  82                         interrupts = <1 13 0xf01>;
  83                         clocks = <&a9periphclk>;
  84                 };
  85
  86                 watchdog@fff10620 {
  87                         compatible = "arm,cortex-a9-twd-wdt";
  88                         reg = <0xfff10620 0x20>;
  89                         interrupts = <1 14 0xf01>;
  90                         clocks = <&a9periphclk>;
  91                 };
  92
  93                 intc: interrupt-controller@fff11000 {
  94                         compatible = "arm,cortex-a9-gic";
  95                         #interrupt-cells = <3>;
  96                         #size-cells = <0>;
  97                         #address-cells = <1>;
  98                         interrupt-controller;
  99                         reg = <0xfff11000 0x1000>,
 100                               <0xfff10100 0x100>;
 101                 };
 102
 103                 L2: l2-cache {
 104                         compatible = "arm,pl310-cache";
 105                         reg = <0xfff12000 0x1000>;
 106                         interrupts = <0 70 4>;
 107                         cache-unified;
 108                         cache-level = <2>;
 109                 };
 110
 111                 pmu {
 112                         compatible = "arm,cortex-a9-pmu";
 113                         interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
 114                 };
 115
 116
 117                 sregs@fff3c200 {
 118                         compatible = "calxeda,hb-sregs-l2-ecc";
 119                         reg = <0xfff3c200 0x100>;
 120                         interrupts = <0 71 4  0 72 4>;
 121                 };
 122
 123         };
 124 };
 125
 126 /include/ "ecx-common.dtsi"