arch/arm/boot/dts/imx51-babbage.dts

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /dts-v1/;
  14 #include "imx51.dtsi"
  15
  16 / {
  17         model = "Freescale i.MX51 Babbage Board";
  18         compatible = "fsl,imx51-babbage", "fsl,imx51";
  19
  20         memory {
  21                 reg = <0x90000000 0x20000000>;
  22         };
  23
  24         display0: display@di0 {
  25                 compatible = "fsl,imx-parallel-display";
  26                 interface-pix-fmt = "rgb24";
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pinctrl_ipu_disp1>;
  29                 display-timings {
  30                         native-mode = <&timing0>;
  31                         timing0: dvi {
  32                                 clock-frequency = <65000000>;
  33                                 hactive = <1024>;
  34                                 vactive = <768>;
  35                                 hback-porch = <220>;
  36                                 hfront-porch = <40>;
  37                                 vback-porch = <21>;
  38                                 vfront-porch = <7>;
  39                                 hsync-len = <60>;
  40                                 vsync-len = <10>;
  41                         };
  42                 };
  43
  44                 port {
  45                         display0_in: endpoint {
  46                                 remote-endpoint = <&ipu_di0_disp0>;
  47                         };
  48                 };
  49         };
  50
  51         display1: display@di1 {
  52                 compatible = "fsl,imx-parallel-display";
  53                 interface-pix-fmt = "rgb565";
  54                 pinctrl-names = "default";
  55                 pinctrl-0 = <&pinctrl_ipu_disp2>;
  56                 status = "disabled";
  57                 display-timings {
  58                         native-mode = <&timing1>;
  59                         timing1: claawvga {
  60                                 clock-frequency = <27000000>;
  61                                 hactive = <800>;
  62                                 vactive = <480>;
  63                                 hback-porch = <40>;
  64                                 hfront-porch = <60>;
  65                                 vback-porch = <10>;
  66                                 vfront-porch = <10>;
  67                                 hsync-len = <20>;
  68                                 vsync-len = <10>;
  69                                 hsync-active = <0>;
  70                                 vsync-active = <0>;
  71                                 de-active = <1>;
  72                                 pixelclk-active = <0>;
  73                         };
  74                 };
  75
  76                 port {
  77                         display1_in: endpoint {
  78                                 remote-endpoint = <&ipu_di1_disp1>;
  79                         };
  80                 };
  81         };
  82
  83         gpio-keys {
  84                 compatible = "gpio-keys";
  85
  86                 power {
  87                         label = "Power Button";
  88                         gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
  89                         linux,code = <116>; /* KEY_POWER */
  90                         gpio-key,wakeup;
  91                 };
  92         };
  93
  94         leds {
  95                 compatible = "gpio-leds";
  96                 pinctrl-names = "default";
  97                 pinctrl-0 = <&pinctrl_gpio_leds>;
  98
  99                 led-diagnostic {
 100                         label = "diagnostic";
 101                         gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 102                 };
 103         };
 104
 105         sound {
 106                 compatible = "fsl,imx51-babbage-sgtl5000",
 107                              "fsl,imx-audio-sgtl5000";
 108                 model = "imx51-babbage-sgtl5000";
 109                 ssi-controller = <&ssi2>;
 110                 audio-codec = <&sgtl5000>;
 111                 audio-routing =
 112                         "MIC_IN", "Mic Jack",
 113                         "Mic Jack", "Mic Bias",
 114                         "Headphone Jack", "HP_OUT";
 115                 mux-int-port = <2>;
 116                 mux-ext-port = <3>;
 117         };
 118
 119         clocks {
 120                 ckih1 {
 121                         clock-frequency = <22579200>;
 122                 };
 123
 124                 clk_26M: codec_clock {
 125                         compatible = "fixed-clock";
 126                         reg=<0>;
 127                         #clock-cells = <0>;
 128                         clock-frequency = <26000000>;
 129                         gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
 130                 };
 131         };
 132
 133         regulators {
 134                 compatible = "simple-bus";
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137
 138                 reg_usb_vbus: regulator@0 {
 139                         compatible = "regulator-fixed";
 140                         reg = <0>;
 141                         regulator-name = "usb_vbus";
 142                         regulator-min-microvolt = <5000000>;
 143                         regulator-max-microvolt = <5000000>;
 144                         gpio = <&gpio2 5 0>;
 145                         enable-active-high;
 146                 };
 147         };
 148
 149         usbphy {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 compatible = "simple-bus";
 153
 154                 usbh1phy: usbh1phy@0 {
 155                         compatible = "usb-nop-xceiv";
 156                         reg = <0>;
 157                         clocks = <&clks 0>;
 158                         clock-names = "main_clk";
 159                 };
 160         };
 161 };
 162
 163 &esdhc1 {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_esdhc1>;
 166         fsl,cd-controller;
 167         fsl,wp-controller;
 168         status = "okay";
 169 };
 170
 171 &esdhc2 {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_esdhc2>;
 174         cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 175         wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 176         status = "okay";
 177 };
 178
 179 &uart3 {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_uart3>;
 182         fsl,uart-has-rtscts;
 183         status = "okay";
 184 };
 185
 186 &ecspi1 {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_ecspi1>;
 189         fsl,spi-num-chipselects = <2>;
 190         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
 191                    <&gpio4 25 GPIO_ACTIVE_LOW>;
 192         status = "okay";
 193
 194         pmic: mc13892@0 {
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 compatible = "fsl,mc13892";
 198                 spi-max-frequency = <6000000>;
 199                 spi-cs-high;
 200                 reg = <0>;
 201                 interrupt-parent = <&gpio1>;
 202                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 203
 204                 regulators {
 205                         sw1_reg: sw1 {
 206                                 regulator-min-microvolt = <600000>;
 207                                 regulator-max-microvolt = <1375000>;
 208                                 regulator-boot-on;
 209                                 regulator-always-on;
 210                         };
 211
 212                         sw2_reg: sw2 {
 213                                 regulator-min-microvolt = <900000>;
 214                                 regulator-max-microvolt = <1850000>;
 215                                 regulator-boot-on;
 216                                 regulator-always-on;
 217                         };
 218
 219                         sw3_reg: sw3 {
 220                                 regulator-min-microvolt = <1100000>;
 221                                 regulator-max-microvolt = <1850000>;
 222                                 regulator-boot-on;
 223                                 regulator-always-on;
 224                         };
 225
 226                         sw4_reg: sw4 {
 227                                 regulator-min-microvolt = <1100000>;
 228                                 regulator-max-microvolt = <1850000>;
 229                                 regulator-boot-on;
 230                                 regulator-always-on;
 231                         };
 232
 233                         vpll_reg: vpll {
 234                                 regulator-min-microvolt = <1050000>;
 235                                 regulator-max-microvolt = <1800000>;
 236                                 regulator-boot-on;
 237                                 regulator-always-on;
 238                         };
 239
 240                         vdig_reg: vdig {
 241                                 regulator-min-microvolt = <1650000>;
 242                                 regulator-max-microvolt = <1650000>;
 243                                 regulator-boot-on;
 244                         };
 245
 246                         vsd_reg: vsd {
 247                                 regulator-min-microvolt = <1800000>;
 248                                 regulator-max-microvolt = <3150000>;
 249                         };
 250
 251                         vusb2_reg: vusb2 {
 252                                 regulator-min-microvolt = <2400000>;
 253                                 regulator-max-microvolt = <2775000>;
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257
 258                         vvideo_reg: vvideo {
 259                                 regulator-min-microvolt = <2775000>;
 260                                 regulator-max-microvolt = <2775000>;
 261                         };
 262
 263                         vaudio_reg: vaudio {
 264                                 regulator-min-microvolt = <2300000>;
 265                                 regulator-max-microvolt = <3000000>;
 266                         };
 267
 268                         vcam_reg: vcam {
 269                                 regulator-min-microvolt = <2500000>;
 270                                 regulator-max-microvolt = <3000000>;
 271                         };
 272
 273                         vgen1_reg: vgen1 {
 274                                 regulator-min-microvolt = <1200000>;
 275                                 regulator-max-microvolt = <1200000>;
 276                         };
 277
 278                         vgen2_reg: vgen2 {
 279                                 regulator-min-microvolt = <1200000>;
 280                                 regulator-max-microvolt = <3150000>;
 281                                 regulator-always-on;
 282                         };
 283
 284                         vgen3_reg: vgen3 {
 285                                 regulator-min-microvolt = <1800000>;
 286                                 regulator-max-microvolt = <2900000>;
 287                                 regulator-always-on;
 288                         };
 289                 };
 290         };
 291
 292         flash: at45db321d@1 {
 293                 #address-cells = <1>;
 294                 #size-cells = <1>;
 295                 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
 296                 spi-max-frequency = <25000000>;
 297                 reg = <1>;
 298
 299                 partition@0 {
 300                         label = "U-Boot";
 301                         reg = <0x0 0x40000>;
 302                         read-only;
 303                 };
 304
 305                 partition@40000 {
 306                         label = "Kernel";
 307                         reg = <0x40000 0x3c0000>;
 308                 };
 309         };
 310 };
 311
 312 &ipu_di0_disp0 {
 313         remote-endpoint = <&display0_in>;
 314 };
 315
 316 &ipu_di1_disp1 {
 317         remote-endpoint = <&display1_in>;
 318 };
 319
 320 &ssi2 {
 321         fsl,mode = "i2s-slave";
 322         status = "okay";
 323 };
 324
 325 &iomuxc {
 326         pinctrl-names = "default";
 327         pinctrl-0 = <&pinctrl_hog>;
 328
 329         imx51-babbage {
 330                 pinctrl_hog: hoggrp {
 331                         fsl,pins = <
 332                                 MX51_PAD_GPIO1_0__SD1_CD     0x20d5
 333                                 MX51_PAD_GPIO1_1__SD1_WP     0x20d5
 334                                 MX51_PAD_GPIO1_5__GPIO1_5    0x100
 335                                 MX51_PAD_GPIO1_6__GPIO1_6    0x100
 336                                 MX51_PAD_EIM_A27__GPIO2_21   0x5
 337                                 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
 338                                 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
 339                                 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
 340                         >;
 341                 };
 342
 343                 pinctrl_audmux: audmuxgrp {
 344                         fsl,pins = <
 345                                 MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
 346                                 MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x80000000
 347                                 MX51_PAD_AUD3_BB_CK__AUD3_TXC           0x80000000
 348                                 MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x80000000
 349                         >;
 350                 };
 351
 352                 pinctrl_ecspi1: ecspi1grp {
 353                         fsl,pins = <
 354                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
 355                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
 356                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
 357                         >;
 358                 };
 359
 360                 pinctrl_esdhc1: esdhc1grp {
 361                         fsl,pins = <
 362                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
 363                                 MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
 364                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
 365                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
 366                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
 367                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
 368                         >;
 369                 };
 370
 371                 pinctrl_esdhc2: esdhc2grp {
 372                         fsl,pins = <
 373                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
 374                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
 375                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
 376                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
 377                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
 378                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
 379                         >;
 380                 };
 381
 382                 pinctrl_fec: fecgrp {
 383                         fsl,pins = <
 384                                 MX51_PAD_EIM_EB2__FEC_MDIO              0x80000000
 385                                 MX51_PAD_EIM_EB3__FEC_RDATA1            0x80000000
 386                                 MX51_PAD_EIM_CS2__FEC_RDATA2            0x80000000
 387                                 MX51_PAD_EIM_CS3__FEC_RDATA3            0x80000000
 388                                 MX51_PAD_EIM_CS4__FEC_RX_ER             0x80000000
 389                                 MX51_PAD_EIM_CS5__FEC_CRS               0x80000000
 390                                 MX51_PAD_NANDF_RB2__FEC_COL             0x80000000
 391                                 MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x80000000
 392                                 MX51_PAD_NANDF_D9__FEC_RDATA0           0x80000000
 393                                 MX51_PAD_NANDF_D8__FEC_TDATA0           0x80000000
 394                                 MX51_PAD_NANDF_CS2__FEC_TX_ER           0x80000000
 395                                 MX51_PAD_NANDF_CS3__FEC_MDC             0x80000000
 396                                 MX51_PAD_NANDF_CS4__FEC_TDATA1          0x80000000
 397                                 MX51_PAD_NANDF_CS5__FEC_TDATA2          0x80000000
 398                                 MX51_PAD_NANDF_CS6__FEC_TDATA3          0x80000000
 399                                 MX51_PAD_NANDF_CS7__FEC_TX_EN           0x80000000
 400                                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x80000000
 401                                 MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
 402                         >;
 403                 };
 404
 405                 pinctrl_gpio_leds: gpioledsgrp {
 406                         fsl,pins = <
 407                                 MX51_PAD_EIM_D22__GPIO2_6               0x80000000
 408                         >;
 409                 };
 410
 411                 pinctrl_i2c2: i2c2grp {
 412                         fsl,pins = <
 413                                 MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
 414                                 MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
 415                         >;
 416                 };
 417
 418                 pinctrl_ipu_disp1: ipudisp1grp {
 419                         fsl,pins = <
 420                                 MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
 421                                 MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
 422                                 MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
 423                                 MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
 424                                 MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
 425                                 MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
 426                                 MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
 427                                 MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
 428                                 MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
 429                                 MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
 430                                 MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
 431                                 MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
 432                                 MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
 433                                 MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
 434                                 MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
 435                                 MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
 436                                 MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
 437                                 MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
 438                                 MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
 439                                 MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
 440                                 MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
 441                                 MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
 442                                 MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
 443                                 MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
 444                                 MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
 445                                 MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
 446                         >;
 447                 };
 448
 449                 pinctrl_ipu_disp2: ipudisp2grp {
 450                         fsl,pins = <
 451                                 MX51_PAD_DISP2_DAT0__DISP2_DAT0         0x5
 452                                 MX51_PAD_DISP2_DAT1__DISP2_DAT1         0x5
 453                                 MX51_PAD_DISP2_DAT2__DISP2_DAT2         0x5
 454                                 MX51_PAD_DISP2_DAT3__DISP2_DAT3         0x5
 455                                 MX51_PAD_DISP2_DAT4__DISP2_DAT4         0x5
 456                                 MX51_PAD_DISP2_DAT5__DISP2_DAT5         0x5
 457                                 MX51_PAD_DISP2_DAT6__DISP2_DAT6         0x5
 458                                 MX51_PAD_DISP2_DAT7__DISP2_DAT7         0x5
 459                                 MX51_PAD_DISP2_DAT8__DISP2_DAT8         0x5
 460                                 MX51_PAD_DISP2_DAT9__DISP2_DAT9         0x5
 461                                 MX51_PAD_DISP2_DAT10__DISP2_DAT10       0x5
 462                                 MX51_PAD_DISP2_DAT11__DISP2_DAT11       0x5
 463                                 MX51_PAD_DISP2_DAT12__DISP2_DAT12       0x5
 464                                 MX51_PAD_DISP2_DAT13__DISP2_DAT13       0x5
 465                                 MX51_PAD_DISP2_DAT14__DISP2_DAT14       0x5
 466                                 MX51_PAD_DISP2_DAT15__DISP2_DAT15       0x5
 467                                 MX51_PAD_DI2_PIN2__DI2_PIN2             0x5
 468                                 MX51_PAD_DI2_PIN3__DI2_PIN3             0x5
 469                                 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     0x5
 470                                 MX51_PAD_DI_GP4__DI2_PIN15              0x5
 471                         >;
 472                 };
 473
 474                 pinctrl_kpp: kppgrp {
 475                         fsl,pins = <
 476                                 MX51_PAD_KEY_ROW0__KEY_ROW0             0xe0
 477                                 MX51_PAD_KEY_ROW1__KEY_ROW1             0xe0
 478                                 MX51_PAD_KEY_ROW2__KEY_ROW2             0xe0
 479                                 MX51_PAD_KEY_ROW3__KEY_ROW3             0xe0
 480                                 MX51_PAD_KEY_COL0__KEY_COL0             0xe8
 481                                 MX51_PAD_KEY_COL1__KEY_COL1             0xe8
 482                                 MX51_PAD_KEY_COL2__KEY_COL2             0xe8
 483                                 MX51_PAD_KEY_COL3__KEY_COL3             0xe8
 484                         >;
 485                 };
 486
 487                 pinctrl_uart1: uart1grp {
 488                         fsl,pins = <
 489                                 MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
 490                                 MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
 491                                 MX51_PAD_UART1_RTS__UART1_RTS           0x1c5
 492                                 MX51_PAD_UART1_CTS__UART1_CTS           0x1c5
 493                         >;
 494                 };
 495
 496                 pinctrl_uart2: uart2grp {
 497                         fsl,pins = <
 498                                 MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
 499                                 MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
 500                         >;
 501                 };
 502
 503                 pinctrl_uart3: uart3grp {
 504                         fsl,pins = <
 505                                 MX51_PAD_EIM_D25__UART3_RXD             0x1c5
 506                                 MX51_PAD_EIM_D26__UART3_TXD             0x1c5
 507                                 MX51_PAD_EIM_D27__UART3_RTS             0x1c5
 508                                 MX51_PAD_EIM_D24__UART3_CTS             0x1c5
 509                         >;
 510                 };
 511
 512                 pinctrl_usbh1: usbh1grp {
 513                         fsl,pins = <
 514                                 MX51_PAD_USBH1_CLK__USBH1_CLK           0x80000000
 515                                 MX51_PAD_USBH1_DIR__USBH1_DIR           0x80000000
 516                                 MX51_PAD_USBH1_NXT__USBH1_NXT           0x80000000
 517                                 MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x80000000
 518                                 MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x80000000
 519                                 MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x80000000
 520                                 MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x80000000
 521                                 MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x80000000
 522                                 MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x80000000
 523                                 MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x80000000
 524                                 MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x80000000
 525                                 MX51_PAD_EIM_D21__GPIO2_5               0x80000000
 526                         >;
 527                 };
 528         };
 529 };
 530
 531 &uart1 {
 532         pinctrl-names = "default";
 533         pinctrl-0 = <&pinctrl_uart1>;
 534         fsl,uart-has-rtscts;
 535         status = "okay";
 536 };
 537
 538 &uart2 {
 539         pinctrl-names = "default";
 540         pinctrl-0 = <&pinctrl_uart2>;
 541         status = "okay";
 542 };
 543
 544 &i2c2 {
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&pinctrl_i2c2>;
 547         status = "okay";
 548
 549         sgtl5000: codec@0a {
 550                 compatible = "fsl,sgtl5000";
 551                 reg = <0x0a>;
 552                 clocks = <&clk_26M>;
 553                 VDDA-supply = <&vdig_reg>;
 554                 VDDIO-supply = <&vvideo_reg>;
 555         };
 556 };
 557
 558 &audmux {
 559         pinctrl-names = "default";
 560         pinctrl-0 = <&pinctrl_audmux>;
 561         status = "okay";
 562 };
 563
 564 &fec {
 565         pinctrl-names = "default";
 566         pinctrl-0 = <&pinctrl_fec>;
 567         phy-mode = "mii";
 568         phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
 569         phy-reset-duration = <1>;
 570         status = "okay";
 571 };
 572
 573 &kpp {
 574         pinctrl-names = "default";
 575         pinctrl-0 = <&pinctrl_kpp>;
 576         linux,keymap = <
 577                 MATRIX_KEY(0, 0, KEY_UP)
 578                 MATRIX_KEY(0, 1, KEY_DOWN)
 579                 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
 580                 MATRIX_KEY(0, 3, KEY_HOME)
 581                 MATRIX_KEY(1, 0, KEY_RIGHT)
 582                 MATRIX_KEY(1, 1, KEY_LEFT)
 583                 MATRIX_KEY(1, 2, KEY_ENTER)
 584                 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
 585                 MATRIX_KEY(2, 0, KEY_F6)
 586                 MATRIX_KEY(2, 1, KEY_F8)
 587                 MATRIX_KEY(2, 2, KEY_F9)
 588                 MATRIX_KEY(2, 3, KEY_F10)
 589                 MATRIX_KEY(3, 0, KEY_F1)
 590                 MATRIX_KEY(3, 1, KEY_F2)
 591                 MATRIX_KEY(3, 2, KEY_F3)
 592                 MATRIX_KEY(3, 3, KEY_POWER)
 593                 >;
 594         status = "okay";
 595 };
 596
 597 &usbh1 {
 598         pinctrl-names = "default";
 599         pinctrl-0 = <&pinctrl_usbh1>;
 600         vbus-supply = <&reg_usb_vbus>;
 601         fsl,usbphy = <&usbh1phy>;
 602         phy_type = "ulpi";
 603         status = "okay";
 604 };