arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         aliases {
  17                 mxcfb0 = &mxcfb1;
  18                 mxcfb1 = &mxcfb2;
  19                 mxcfb2 = &mxcfb3;
  20                 mxcfb3 = &mxcfb4;
  21         };
  22
  23         battery: max8903@0 {
  24                 compatible = "fsl,max8903-charger";
  25                 pinctrl-names = "default";
  26                 dok_input = <&gpio2 24 1>;
  27                 uok_input = <&gpio1 27 1>;
  28                 chg_input = <&gpio3 23 1>;
  29                 flt_input = <&gpio5 2 1>;
  30                 fsl,dcm_always_high;
  31                 fsl,dc_valid;
  32                 fsl,usb_valid;
  33                 status = "okay";
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38
  39                 charger-led {
  40                         gpios = <&gpio1 2 0>;
  41                         linux,default-trigger = "max8903-charger-charging";
  42                         retain-state-suspended;
  43                 };
  44         };
  45
  46         memory {
  47                 reg = <0x10000000 0x40000000>;
  48         };
  49
  50         regulators {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 reg_usb_otg_vbus: regulator@0 {
  56                         compatible = "regulator-fixed";
  57                         reg = <0>;
  58                         regulator-name = "usb_otg_vbus";
  59                         regulator-min-microvolt = <5000000>;
  60                         regulator-max-microvolt = <5000000>;
  61                         gpio = <&gpio3 22 0>;
  62                         enable-active-high;
  63                 };
  64
  65                 reg_usb_h1_vbus: regulator@1 {
  66                         compatible = "regulator-fixed";
  67                         reg = <1>;
  68                         regulator-name = "usb_h1_vbus";
  69                         regulator-min-microvolt = <5000000>;
  70                         regulator-max-microvolt = <5000000>;
  71                         gpio = <&gpio1 29 0>;
  72                         enable-active-high;
  73                 };
  74
  75                 reg_audio: regulator@2 {
  76                         compatible = "regulator-fixed";
  77                         reg = <2>;
  78                         regulator-name = "wm8962-supply";
  79                         gpio = <&gpio4 10 0>;
  80                         enable-active-high;
  81                 };
  82
  83                 reg_sensor: regulator@3 {
  84                         compatible = "regulator-fixed";
  85                         reg = <3>;
  86                         regulator-name = "sensor-supply";
  87                         regulator-min-microvolt = <3300000>;
  88                         regulator-max-microvolt = <3300000>;
  89                         gpio = <&gpio2 31 0>;
  90                         startup-delay-us = <500>;
  91                         enable-active-high;
  92                 };
  93         };
  94
  95         gpio-keys {
  96                 compatible = "gpio-keys";
  97                 pinctrl-names = "default";
  98                 pinctrl-0 = <&pinctrl_gpio_keys>;
  99
 100                 power {
 101                         label = "Power Button";
 102                         gpios = <&gpio3 29 0>;
 103                         gpio-key,wakeup;
 104                         linux,code = <KEY_POWER>;
 105                 };
 106
 107                 volume-up {
 108                         label = "Volume Up";
 109                         gpios = <&gpio1 4 0>;
 110                         gpio-key,wakeup;
 111                         linux,code = <KEY_VOLUMEUP>;
 112                 };
 113
 114                 volume-down {
 115                         label = "Volume Down";
 116                         gpios = <&gpio1 5 0>;
 117                         gpio-key,wakeup;
 118                         linux,code = <KEY_VOLUMEDOWN>;
 119                 };
 120         };
 121
 122         sound {
 123                 compatible = "fsl,imx6q-sabresd-wm8962",
 124                            "fsl,imx-audio-wm8962";
 125                 model = "wm8962-audio";
 126                 ssi-controller = <&ssi2>;
 127                 audio-codec = <&codec>;
 128                 audio-routing =
 129                         "Headphone Jack", "HPOUTL",
 130                         "Headphone Jack", "HPOUTR",
 131                         "Ext Spk", "SPKOUTL",
 132                         "Ext Spk", "SPKOUTR",
 133                         "MICBIAS", "AMIC",
 134                         "IN3R", "MICBIAS",
 135                         "DMIC", "MICBIAS",
 136                         "DMICDAT", "DMIC";
 137                 mux-int-port = <2>;
 138                 mux-ext-port = <3>;
 139         };
 140
 141         sound-hdmi {
 142                 compatible = "fsl,imx6q-audio-hdmi",
 143                              "fsl,imx-audio-hdmi";
 144                 model = "imx-audio-hdmi";
 145                 hdmi-controller = <&hdmi_audio>;
 146         };
 147
 148         mxcfb1: fb@0 {
 149                 compatible = "fsl,mxc_sdc_fb";
 150                 disp_dev = "ldb";
 151                 interface_pix_fmt = "RGB666";
 152                 default_bpp = <16>;
 153                 int_clk = <0>;
 154                 late_init = <0>;
 155                 status = "disabled";
 156         };
 157
 158         mxcfb2: fb@1 {
 159                 compatible = "fsl,mxc_sdc_fb";
 160                 disp_dev = "hdmi";
 161                 interface_pix_fmt = "RGB24";
 162                 mode_str ="1920x1080M@60";
 163                 default_bpp = <24>;
 164                 int_clk = <0>;
 165                 late_init = <0>;
 166                 status = "disabled";
 167         };
 168
 169         mxcfb3: fb@2 {
 170                 compatible = "fsl,mxc_sdc_fb";
 171                 disp_dev = "lcd";
 172                 interface_pix_fmt = "RGB565";
 173                 mode_str ="CLAA-WVGA";
 174                 default_bpp = <16>;
 175                 int_clk = <0>;
 176                 late_init = <0>;
 177                 status = "disabled";
 178         };
 179
 180         mxcfb4: fb@3 {
 181                 compatible = "fsl,mxc_sdc_fb";
 182                 disp_dev = "ldb";
 183                 interface_pix_fmt = "RGB666";
 184                 default_bpp = <16>;
 185                 int_clk = <0>;
 186                 late_init = <0>;
 187                 status = "disabled";
 188         };
 189
 190         lcd@0 {
 191                 compatible = "fsl,lcd";
 192                 ipu_id = <0>;
 193                 disp_id = <0>;
 194                 default_ifmt = "RGB565";
 195                 pinctrl-names = "default";
 196                 pinctrl-0 = <&pinctrl_ipu1>;
 197                 status = "okay";
 198         };
 199
 200         backlight {
 201                 compatible = "pwm-backlight";
 202                 pwms = <&pwm1 0 5000000>;
 203                 brightness-levels = <0 4 8 16 32 64 128 255>;
 204                 default-brightness-level = <7>;
 205                 status = "okay";
 206         };
 207
 208         v4l2_out {
 209                 compatible = "fsl,mxc_v4l2_output";
 210                 status = "okay";
 211         };
 212 };
 213
 214 &audmux {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_audmux>;
 217         status = "okay";
 218 };
 219
 220 &cpu0 {
 221         arm-supply = <&sw1a_reg>;
 222         soc-supply = <&sw1c_reg>;
 223 };
 224
 225 &ecspi1 {
 226         fsl,spi-num-chipselects = <1>;
 227         cs-gpios = <&gpio4 9 0>;
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_ecspi1>;
 230         status = "okay";
 231
 232         flash: m25p80@0 {
 233                 #address-cells = <1>;
 234                 #size-cells = <1>;
 235                 compatible = "st,m25p32";
 236                 spi-max-frequency = <20000000>;
 237                 reg = <0>;
 238         };
 239 };
 240
 241 &fec {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_enet>;
 244         phy-mode = "rgmii";
 245         phy-reset-gpios = <&gpio1 25 0>;
 246         status = "okay";
 247 };
 248
 249 &i2c1 {
 250         clock-frequency = <100000>;
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_i2c1>;
 253         status = "okay";
 254
 255         codec: wm8962@1a {
 256                 compatible = "wlf,wm8962";
 257                 reg = <0x1a>;
 258                 clocks = <&clks 201>;
 259                 DCVDD-supply = <&reg_audio>;
 260                 DBVDD-supply = <&reg_audio>;
 261                 AVDD-supply = <&reg_audio>;
 262                 CPVDD-supply = <&reg_audio>;
 263                 MICVDD-supply = <&reg_audio>;
 264                 PLLVDD-supply = <&reg_audio>;
 265                 SPKVDD1-supply = <&reg_audio>;
 266                 SPKVDD2-supply = <&reg_audio>;
 267                 gpio-cfg = <
 268                         0x0000 /* 0:Default */
 269                         0x0000 /* 1:Default */
 270                         0x0013 /* 2:FN_DMICCLK */
 271                         0x0000 /* 3:Default */
 272                         0x8014 /* 4:FN_DMICCDAT */
 273                         0x0000 /* 5:Default */
 274                 >;
 275        };
 276
 277         mma8451@1c {
 278                 compatible = "fsl,mma8451";
 279                 reg = <0x1c>;
 280                 position = <0>;
 281                 vdd-supply = <&reg_sensor>;
 282                 vddio-supply = <&reg_sensor>;
 283                 interrupt-parent = <&gpio1>;
 284                 interrupts = <18 8>;
 285                 interrupt-route = <1>;
 286         };
 287 };
 288
 289 &i2c2 {
 290         clock-frequency = <100000>;
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_i2c2>;
 293         status = "okay";
 294
 295         hdmi: edid@50 {
 296                 compatible = "fsl,imx6-hdmi-i2c";
 297                 reg = <0x50>;
 298         };
 299
 300         max11801@48 {
 301                 compatible = "maxim,max11801";
 302                 reg = <0x48>;
 303                 interrupt-parent = <&gpio3>;
 304                 interrupts = <26 2>;
 305                 work-mode = <1>;/*DCM mode*/
 306         };
 307
 308         pmic: pfuze100@08 {
 309                 compatible = "fsl,pfuze100";
 310                 reg = <0x08>;
 311
 312                 regulators {
 313                         sw1a_reg: sw1ab {
 314                                 regulator-min-microvolt = <300000>;
 315                                 regulator-max-microvolt = <1875000>;
 316                                 regulator-boot-on;
 317                                 regulator-always-on;
 318                                 regulator-ramp-delay = <6250>;
 319                         };
 320
 321                         sw1c_reg: sw1c {
 322                                 regulator-min-microvolt = <300000>;
 323                                 regulator-max-microvolt = <1875000>;
 324                                 regulator-boot-on;
 325                                 regulator-always-on;
 326                                 regulator-ramp-delay = <6250>;
 327                         };
 328
 329                         sw2_reg: sw2 {
 330                                 regulator-min-microvolt = <800000>;
 331                                 regulator-max-microvolt = <3300000>;
 332                                 regulator-boot-on;
 333                                 regulator-always-on;
 334                         };
 335
 336                         sw3a_reg: sw3a {
 337                                 regulator-min-microvolt = <400000>;
 338                                 regulator-max-microvolt = <1975000>;
 339                                 regulator-boot-on;
 340                                 regulator-always-on;
 341                         };
 342
 343                         sw3b_reg: sw3b {
 344                                 regulator-min-microvolt = <400000>;
 345                                 regulator-max-microvolt = <1975000>;
 346                                 regulator-boot-on;
 347                                 regulator-always-on;
 348                         };
 349
 350                         sw4_reg: sw4 {
 351                                 regulator-min-microvolt = <800000>;
 352                                 regulator-max-microvolt = <3300000>;
 353                         };
 354
 355                         swbst_reg: swbst {
 356                                 regulator-min-microvolt = <5000000>;
 357                                 regulator-max-microvolt = <5150000>;
 358                         };
 359
 360                         snvs_reg: vsnvs {
 361                                 regulator-min-microvolt = <1000000>;
 362                                 regulator-max-microvolt = <3000000>;
 363                                 regulator-boot-on;
 364                                 regulator-always-on;
 365                         };
 366
 367                         vref_reg: vrefddr {
 368                                 regulator-boot-on;
 369                                 regulator-always-on;
 370                         };
 371
 372                         vgen1_reg: vgen1 {
 373                                 regulator-min-microvolt = <800000>;
 374                                 regulator-max-microvolt = <1550000>;
 375                         };
 376
 377                         vgen2_reg: vgen2 {
 378                                 regulator-min-microvolt = <800000>;
 379                                 regulator-max-microvolt = <1550000>;
 380                         };
 381
 382                         vgen3_reg: vgen3 {
 383                                 regulator-min-microvolt = <1800000>;
 384                                 regulator-max-microvolt = <3300000>;
 385                         };
 386
 387                         vgen4_reg: vgen4 {
 388                                 regulator-min-microvolt = <1800000>;
 389                                 regulator-max-microvolt = <3300000>;
 390                                 regulator-always-on;
 391                         };
 392
 393                         vgen5_reg: vgen5 {
 394                                 regulator-min-microvolt = <1800000>;
 395                                 regulator-max-microvolt = <3300000>;
 396                                 regulator-always-on;
 397                         };
 398
 399                         vgen6_reg: vgen6 {
 400                                 regulator-min-microvolt = <1800000>;
 401                                 regulator-max-microvolt = <3300000>;
 402                                 regulator-always-on;
 403                         };
 404                 };
 405         };
 406 };
 407
 408 &i2c3 {
 409         clock-frequency = <100000>;
 410         pinctrl-names = "default";
 411         pinctrl-0 = <&pinctrl_i2c3>;
 412         status = "okay";
 413
 414         egalax_ts@04 {
 415                 compatible = "eeti,egalax_ts";
 416                 reg = <0x04>;
 417                 interrupt-parent = <&gpio6>;
 418                 interrupts = <7 2>;
 419                 wakeup-gpios = <&gpio6 7 0>;
 420         };
 421
 422         mag3110@0e {
 423                 compatible = "fsl,mag3110";
 424                 reg = <0x0e>;
 425                 position = <2>;
 426                 vdd-supply = <&reg_sensor>;
 427                 vddio-supply = <&reg_sensor>;
 428                 interrupt-parent = <&gpio3>;
 429                 interrupts = <16 1>;
 430         };
 431 };
 432
 433 &iomuxc {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_hog>;
 436
 437         imx6qdl-sabresd {
 438                 pinctrl_hog: hoggrp {
 439                         fsl,pins = <
 440                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
 441                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
 442                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
 443                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
 444                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 445                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
 446                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 447                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
 448                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
 449                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
 450                                 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
 451                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 452                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
 453                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
 454                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
 455                                 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
 456                                 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
 457                         >;
 458                 };
 459
 460                 pinctrl_audmux: audmuxgrp {
 461                         fsl,pins = <
 462                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 463                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 464                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 465                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 466                         >;
 467                 };
 468
 469                 pinctrl_ecspi1: ecspi1grp {
 470                         fsl,pins = <
 471                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 472                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 473                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 474                         >;
 475                 };
 476
 477                 pinctrl_enet: enetgrp {
 478                         fsl,pins = <
 479                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 480                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 481                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 482                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 483                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 484                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 485                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 486                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 487                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 488                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 489                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 490                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 491                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 492                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 493                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 494                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 495                         >;
 496                 };
 497
 498                 pinctrl_enet_irq: enetirqgrp {
 499                         fsl,pins = <
 500                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 501                         >;
 502                 };
 503
 504                 pinctrl_gpio_keys: gpio_keysgrp {
 505                         fsl,pins = <
 506                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
 507                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x80000000
 508                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x80000000
 509                         >;
 510                 };
 511
 512                 pinctrl_hdmi_cec: hdmicecgrp {
 513                         fsl,pins = <
 514                                 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 515                         >;
 516                 };
 517
 518                 pinctrl_hdmi_hdcp: hdmihdcpgrp {
 519                         fsl,pins = <
 520                                 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 521                                 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 522                         >;
 523                 };
 524
 525                 pinctrl_i2c1: i2c1grp {
 526                         fsl,pins = <
 527                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 528                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 529                         >;
 530                 };
 531
 532                 pinctrl_i2c2: i2c2grp {
 533                         fsl,pins = <
 534                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 535                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 536                          >;
 537                 };
 538
 539                 pinctrl_i2c3: i2c3grp {
 540                         fsl,pins = <
 541                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 542                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 543                         >;
 544                 };
 545
 546                 pinctrl_ipu1: ipu1grp {
 547                         fsl,pins = <
 548                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 549                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 550                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 551                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 552                                 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
 553                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 554                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 555                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 556                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 557                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 558                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 559                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 560                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 561                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 562                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 563                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 564                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 565                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 566                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 567                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 568                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 569                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 570                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 571                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 572                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 573                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 574                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 575                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 576                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 577                         >;
 578                 };
 579
 580                 pinctrl_pwm1: pwm1grp {
 581                         fsl,pins = <
 582                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 583                         >;
 584                 };
 585
 586                 pinctrl_uart1: uart1grp {
 587                         fsl,pins = <
 588                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 589                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 590                         >;
 591                 };
 592
 593                 pinctrl_uart5_1: uart5grp-1 {
 594                         fsl,pins = <
 595                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 596                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 597                                 MX6QDL_PAD_KEY_COL4__UART5_RTS_B        0x1b0b1
 598                                 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B        0x1b0b1
 599                         >;
 600                 };
 601
 602                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 603                         fsl,pins = <
 604                                 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA      0x1b0b1
 605                                 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA      0x1b0b1
 606                                 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B        0x1b0b1
 607                                 MX6QDL_PAD_KEY_COL4__UART5_CTS_B        0x1b0b1
 608                         >;
 609                 };
 610
 611                 pinctrl_usbotg: usbotggrp {
 612                         fsl,pins = <
 613                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 614                         >;
 615                 };
 616
 617                 pinctrl_usdhc2: usdhc2grp {
 618                         fsl,pins = <
 619                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 620                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 621                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 622                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 623                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 624                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 625                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 626                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 627                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 628                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 629                         >;
 630                 };
 631
 632                 pinctrl_usdhc3: usdhc3grp {
 633                         fsl,pins = <
 634                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 635                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 636                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 637                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 638                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 639                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 640                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 641                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 642                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 643                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 644                         >;
 645                 };
 646         };
 647 };
 648
 649 &dcic1 {
 650         dcic_id = <0>;
 651         dcic_mux = "dcic-hdmi";
 652         status = "okay";
 653 };
 654
 655 &dcic2 {
 656         dcic_id = <1>;
 657         dcic_mux = "dcic-lvds1";
 658         status = "okay";
 659 };
 660
 661 &gpc {
 662         /* use ldo-bypass, u-boot will check it and configure */
 663         fsl,ldo-bypass = <1>;
 664 };
 665
 666 &hdmi_audio {
 667         status = "okay";
 668 };
 669
 670 &hdmi_cec {
 671         pinctrl-names = "default";
 672         pinctrl-0 = <&pinctrl_hdmi_cec>;
 673         status = "okay";
 674 };
 675
 676 &hdmi_core {
 677         ipu_id = <0>;
 678         disp_id = <0>;
 679         status = "okay";
 680 };
 681
 682 &hdmi_video {
 683         fsl,phy_reg_vlev = <0x0294>;
 684         fsl,phy_reg_cksymtx = <0x800d>;
 685         status = "okay";
 686 };
 687
 688 &ldb {
 689         status = "okay";
 690
 691         lvds-channel@0 {
 692                 fsl,data-mapping = "spwg";
 693                 fsl,data-width = <18>;
 694                 status = "okay";
 695
 696                 display-timings {
 697                         native-mode = <&timing0>;
 698                         timing0: hsd100pxn1 {
 699                                 clock-frequency = <65000000>;
 700                                 hactive = <1024>;
 701                                 vactive = <768>;
 702                                 hback-porch = <220>;
 703                                 hfront-porch = <40>;
 704                                 vback-porch = <21>;
 705                                 vfront-porch = <7>;
 706                                 hsync-len = <60>;
 707                                 vsync-len = <10>;
 708                         };
 709                 };
 710         };
 711
 712         lvds-channel@1 {
 713                 fsl,data-mapping = "spwg";
 714                 fsl,data-width = <18>;
 715                 primary;
 716                 status = "okay";
 717
 718                 display-timings {
 719                         native-mode = <&timing1>;
 720                         timing1: hsd100pxn1 {
 721                                 clock-frequency = <65000000>;
 722                                 hactive = <1024>;
 723                                 vactive = <768>;
 724                                 hback-porch = <220>;
 725                                 hfront-porch = <40>;
 726                                 vback-porch = <21>;
 727                                 vfront-porch = <7>;
 728                                 hsync-len = <60>;
 729                                 vsync-len = <10>;
 730                         };
 731                 };
 732         };
 733 };
 734
 735 &pwm1 {
 736         pinctrl-names = "default";
 737         pinctrl-0 = <&pinctrl_pwm1>;
 738         status = "okay";
 739 };
 740
 741 &ssi2 {
 742         fsl,mode = "i2s-slave";
 743         status = "okay";
 744 };
 745
 746 &uart1 {
 747         pinctrl-names = "default";
 748         pinctrl-0 = <&pinctrl_uart1>;
 749         status = "okay";
 750 };
 751
 752 &usbh1 {
 753         vbus-supply = <&reg_usb_h1_vbus>;
 754         status = "okay";
 755 };
 756
 757 &usbotg {
 758         vbus-supply = <&reg_usb_otg_vbus>;
 759         pinctrl-names = "default";
 760         pinctrl-0 = <&pinctrl_usbotg>;
 761         disable-over-current;
 762         status = "okay";
 763 };
 764
 765 &usdhc2 {
 766         pinctrl-names = "default";
 767         pinctrl-0 = <&pinctrl_usdhc2>;
 768         bus-width = <8>;
 769         cd-gpios = <&gpio2 2 0>;
 770         wp-gpios = <&gpio2 3 0>;
 771         status = "okay";
 772 };
 773
 774 &usdhc3 {
 775         pinctrl-names = "default";
 776         pinctrl-0 = <&pinctrl_usdhc3>;
 777         bus-width = <8>;
 778         cd-gpios = <&gpio2 0 0>;
 779         wp-gpios = <&gpio2 1 0>;
 780         status = "okay";
 781 };