arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         aliases {
  17                 mxcfb0 = &mxcfb1;
  18                 mxcfb1 = &mxcfb2;
  19                 mxcfb2 = &mxcfb3;
  20                 mxcfb3 = &mxcfb4;
  21         };
  22
  23         memory {
  24                 reg = <0x10000000 0x40000000>;
  25         };
  26
  27         regulators {
  28                 compatible = "simple-bus";
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 reg_usb_otg_vbus: regulator@0 {
  33                         compatible = "regulator-fixed";
  34                         reg = <0>;
  35                         regulator-name = "usb_otg_vbus";
  36                         regulator-min-microvolt = <5000000>;
  37                         regulator-max-microvolt = <5000000>;
  38                         gpio = <&gpio3 22 0>;
  39                         enable-active-high;
  40                 };
  41
  42                 reg_usb_h1_vbus: regulator@1 {
  43                         compatible = "regulator-fixed";
  44                         reg = <1>;
  45                         regulator-name = "usb_h1_vbus";
  46                         regulator-min-microvolt = <5000000>;
  47                         regulator-max-microvolt = <5000000>;
  48                         gpio = <&gpio1 29 0>;
  49                         enable-active-high;
  50                 };
  51
  52                 reg_audio: regulator@2 {
  53                         compatible = "regulator-fixed";
  54                         reg = <2>;
  55                         regulator-name = "wm8962-supply";
  56                         gpio = <&gpio4 10 0>;
  57                         enable-active-high;
  58                 };
  59         };
  60
  61         gpio-keys {
  62                 compatible = "gpio-keys";
  63                 pinctrl-names = "default";
  64                 pinctrl-0 = <&pinctrl_gpio_keys>;
  65
  66                 power {
  67                         label = "Power Button";
  68                         gpios = <&gpio3 29 0>;
  69                         gpio-key,wakeup;
  70                         linux,code = <KEY_POWER>;
  71                 };
  72
  73                 volume-up {
  74                         label = "Volume Up";
  75                         gpios = <&gpio1 4 0>;
  76                         gpio-key,wakeup;
  77                         linux,code = <KEY_VOLUMEUP>;
  78                 };
  79
  80                 volume-down {
  81                         label = "Volume Down";
  82                         gpios = <&gpio1 5 0>;
  83                         gpio-key,wakeup;
  84                         linux,code = <KEY_VOLUMEDOWN>;
  85                 };
  86         };
  87
  88         sound {
  89                 compatible = "fsl,imx6q-sabresd-wm8962",
  90                            "fsl,imx-audio-wm8962";
  91                 model = "wm8962-audio";
  92                 ssi-controller = <&ssi2>;
  93                 audio-codec = <&codec>;
  94                 audio-routing =
  95                         "Headphone Jack", "HPOUTL",
  96                         "Headphone Jack", "HPOUTR",
  97                         "Ext Spk", "SPKOUTL",
  98                         "Ext Spk", "SPKOUTR",
  99                         "MICBIAS", "AMIC",
 100                         "IN3R", "MICBIAS",
 101                         "DMIC", "MICBIAS",
 102                         "DMICDAT", "DMIC";
 103                 mux-int-port = <2>;
 104                 mux-ext-port = <3>;
 105         };
 106
 107         sound-hdmi {
 108                 compatible = "fsl,imx6q-audio-hdmi",
 109                              "fsl,imx-audio-hdmi";
 110                 model = "imx-audio-hdmi";
 111                 hdmi-controller = <&hdmi_audio>;
 112         };
 113
 114         mxcfb1: fb@0 {
 115                 compatible = "fsl,mxc_sdc_fb";
 116                 disp_dev = "ldb";
 117                 interface_pix_fmt = "RGB666";
 118                 default_bpp = <16>;
 119                 int_clk = <0>;
 120                 late_init = <0>;
 121                 status = "disabled";
 122         };
 123
 124         mxcfb2: fb@1 {
 125                 compatible = "fsl,mxc_sdc_fb";
 126                 disp_dev = "hdmi";
 127                 interface_pix_fmt = "RGB24";
 128                 mode_str ="1920x1080M@60";
 129                 default_bpp = <24>;
 130                 int_clk = <0>;
 131                 late_init = <0>;
 132                 status = "disabled";
 133         };
 134
 135         mxcfb3: fb@2 {
 136                 compatible = "fsl,mxc_sdc_fb";
 137                 disp_dev = "lcd";
 138                 interface_pix_fmt = "RGB565";
 139                 mode_str ="CLAA-WVGA";
 140                 default_bpp = <16>;
 141                 int_clk = <0>;
 142                 late_init = <0>;
 143                 status = "disabled";
 144         };
 145
 146         mxcfb4: fb@3 {
 147                 compatible = "fsl,mxc_sdc_fb";
 148                 disp_dev = "ldb";
 149                 interface_pix_fmt = "RGB666";
 150                 default_bpp = <16>;
 151                 int_clk = <0>;
 152                 late_init = <0>;
 153                 status = "disabled";
 154         };
 155
 156         lcd@0 {
 157                 compatible = "fsl,lcd";
 158                 ipu_id = <0>;
 159                 disp_id = <0>;
 160                 default_ifmt = "RGB565";
 161                 pinctrl-names = "default";
 162                 pinctrl-0 = <&pinctrl_ipu1>;
 163                 status = "okay";
 164         };
 165
 166         backlight {
 167                 compatible = "pwm-backlight";
 168                 pwms = <&pwm1 0 5000000>;
 169                 brightness-levels = <0 4 8 16 32 64 128 255>;
 170                 default-brightness-level = <7>;
 171                 status = "okay";
 172         };
 173
 174         v4l2_out {
 175                 compatible = "fsl,mxc_v4l2_output";
 176                 status = "okay";
 177         };
 178 };
 179
 180 &audmux {
 181         pinctrl-names = "default";
 182         pinctrl-0 = <&pinctrl_audmux>;
 183         status = "okay";
 184 };
 185
 186 &ecspi1 {
 187         fsl,spi-num-chipselects = <1>;
 188         cs-gpios = <&gpio4 9 0>;
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_ecspi1>;
 191         status = "okay";
 192
 193         flash: m25p80@0 {
 194                 #address-cells = <1>;
 195                 #size-cells = <1>;
 196                 compatible = "st,m25p32";
 197                 spi-max-frequency = <20000000>;
 198                 reg = <0>;
 199         };
 200 };
 201
 202 &fec {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_enet>;
 205         phy-mode = "rgmii";
 206         phy-reset-gpios = <&gpio1 25 0>;
 207         status = "okay";
 208 };
 209
 210 &i2c1 {
 211         clock-frequency = <100000>;
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_i2c1>;
 214         status = "okay";
 215
 216         codec: wm8962@1a {
 217                 compatible = "wlf,wm8962";
 218                 reg = <0x1a>;
 219                 clocks = <&clks 201>;
 220                 DCVDD-supply = <&reg_audio>;
 221                 DBVDD-supply = <&reg_audio>;
 222                 AVDD-supply = <&reg_audio>;
 223                 CPVDD-supply = <&reg_audio>;
 224                 MICVDD-supply = <&reg_audio>;
 225                 PLLVDD-supply = <&reg_audio>;
 226                 SPKVDD1-supply = <&reg_audio>;
 227                 SPKVDD2-supply = <&reg_audio>;
 228                 gpio-cfg = <
 229                         0x0000 /* 0:Default */
 230                         0x0000 /* 1:Default */
 231                         0x0013 /* 2:FN_DMICCLK */
 232                         0x0000 /* 3:Default */
 233                         0x8014 /* 4:FN_DMICCDAT */
 234                         0x0000 /* 5:Default */
 235                 >;
 236        };
 237 };
 238
 239 &i2c2 {
 240         clock-frequency = <100000>;
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_i2c2>;
 243         status = "okay";
 244
 245         hdmi: edid@50 {
 246                 compatible = "fsl,imx6-hdmi-i2c";
 247                 reg = <0x50>;
 248         };
 249 };
 250
 251 &i2c3 {
 252         clock-frequency = <100000>;
 253         pinctrl-names = "default";
 254         pinctrl-0 = <&pinctrl_i2c3>;
 255         status = "okay";
 256
 257         egalax_ts@04 {
 258                 compatible = "eeti,egalax_ts";
 259                 reg = <0x04>;
 260                 interrupt-parent = <&gpio6>;
 261                 interrupts = <7 2>;
 262                 wakeup-gpios = <&gpio6 7 0>;
 263         };
 264 };
 265
 266 &iomuxc {
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_hog>;
 269
 270         imx6qdl-sabresd {
 271                 pinctrl_hog: hoggrp {
 272                         fsl,pins = <
 273                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
 274                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
 275                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
 276                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
 277                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 278                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
 279                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 280                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
 281                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
 282                         >;
 283                 };
 284
 285                 pinctrl_audmux: audmuxgrp {
 286                         fsl,pins = <
 287                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 288                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 289                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 290                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 291                         >;
 292                 };
 293
 294                 pinctrl_ecspi1: ecspi1grp {
 295                         fsl,pins = <
 296                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 297                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 298                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 299                         >;
 300                 };
 301
 302                 pinctrl_enet: enetgrp {
 303                         fsl,pins = <
 304                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 305                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 306                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 307                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 308                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 309                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 310                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 311                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 312                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 313                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 314                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 315                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 316                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 317                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 318                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 319                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 320                         >;
 321                 };
 322
 323                 pinctrl_gpio_keys: gpio_keysgrp {
 324                         fsl,pins = <
 325                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
 326                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x80000000
 327                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x80000000
 328                         >;
 329                 };
 330
 331                 pinctrl_hdmi_cec: hdmicecgrp {
 332                         fsl,pins = <
 333                                 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 334                         >;
 335                 };
 336
 337                 pinctrl_hdmi_hdcp: hdmihdcpgrp {
 338                         fsl,pins = <
 339                                 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 340                                 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 341                         >;
 342                 };
 343
 344                 pinctrl_i2c1: i2c1grp {
 345                         fsl,pins = <
 346                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 347                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 348                         >;
 349                 };
 350
 351                 pinctrl_i2c2: i2c2grp {
 352                         fsl,pins = <
 353                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 354                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 355                          >;
 356                 };
 357
 358                 pinctrl_i2c3: i2c3grp {
 359                         fsl,pins = <
 360                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 361                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 362                         >;
 363                 };
 364
 365                 pinctrl_ipu1: ipu1grp {
 366                         fsl,pins = <
 367                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 368                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 369                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 370                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 371                                 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
 372                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 373                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 374                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 375                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 376                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 377                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 378                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 379                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 380                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 381                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 382                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 383                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 384                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 385                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 386                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 387                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 388                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 389                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 390                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 391                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 392                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 393                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 394                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 395                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 396                         >;
 397                 };
 398
 399                 pinctrl_pwm1: pwm1grp {
 400                         fsl,pins = <
 401                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 402                         >;
 403                 };
 404
 405                 pinctrl_uart1: uart1grp {
 406                         fsl,pins = <
 407                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 408                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 409                         >;
 410                 };
 411
 412                 pinctrl_uart5_1: uart5grp-1 {
 413                         fsl,pins = <
 414                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 415                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 416                                 MX6QDL_PAD_KEY_COL4__UART5_RTS_B        0x1b0b1
 417                                 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B        0x1b0b1
 418                         >;
 419                 };
 420
 421                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 422                         fsl,pins = <
 423                                 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA      0x1b0b1
 424                                 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA      0x1b0b1
 425                                 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B        0x1b0b1
 426                                 MX6QDL_PAD_KEY_COL4__UART5_CTS_B        0x1b0b1
 427                         >;
 428                 };
 429
 430                 pinctrl_usbotg: usbotggrp {
 431                         fsl,pins = <
 432                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 433                         >;
 434                 };
 435
 436                 pinctrl_usdhc2: usdhc2grp {
 437                         fsl,pins = <
 438                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 439                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 440                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 441                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 442                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 443                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 444                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 445                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 446                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 447                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 448                         >;
 449                 };
 450
 451                 pinctrl_usdhc3: usdhc3grp {
 452                         fsl,pins = <
 453                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 454                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 455                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 456                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 457                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 458                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 459                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 460                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 461                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 462                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 463                         >;
 464                 };
 465         };
 466 };
 467
 468 &dcic1 {
 469         dcic_id = <0>;
 470         dcic_mux = "dcic-hdmi";
 471         status = "okay";
 472 };
 473
 474 &dcic2 {
 475         dcic_id = <1>;
 476         dcic_mux = "dcic-lvds1";
 477         status = "okay";
 478 };
 479
 480 &hdmi_audio {
 481         status = "okay";
 482 };
 483
 484 &hdmi_cec {
 485         pinctrl-names = "default";
 486         pinctrl-0 = <&pinctrl_hdmi_cec>;
 487         status = "okay";
 488 };
 489
 490 &hdmi_core {
 491         ipu_id = <0>;
 492         disp_id = <0>;
 493         status = "okay";
 494 };
 495
 496 &hdmi_video {
 497         fsl,phy_reg_vlev = <0x0294>;
 498         fsl,phy_reg_cksymtx = <0x800d>;
 499         status = "okay";
 500 };
 501
 502 &ldb {
 503         status = "okay";
 504
 505         lvds-channel@0 {
 506                 fsl,data-mapping = "spwg";
 507                 fsl,data-width = <18>;
 508                 status = "okay";
 509
 510                 display-timings {
 511                         native-mode = <&timing0>;
 512                         timing0: hsd100pxn1 {
 513                                 clock-frequency = <65000000>;
 514                                 hactive = <1024>;
 515                                 vactive = <768>;
 516                                 hback-porch = <220>;
 517                                 hfront-porch = <40>;
 518                                 vback-porch = <21>;
 519                                 vfront-porch = <7>;
 520                                 hsync-len = <60>;
 521                                 vsync-len = <10>;
 522                         };
 523                 };
 524         };
 525
 526         lvds-channel@1 {
 527                 fsl,data-mapping = "spwg";
 528                 fsl,data-width = <18>;
 529                 primary;
 530                 status = "okay";
 531
 532                 display-timings {
 533                         native-mode = <&timing1>;
 534                         timing1: hsd100pxn1 {
 535                                 clock-frequency = <65000000>;
 536                                 hactive = <1024>;
 537                                 vactive = <768>;
 538                                 hback-porch = <220>;
 539                                 hfront-porch = <40>;
 540                                 vback-porch = <21>;
 541                                 vfront-porch = <7>;
 542                                 hsync-len = <60>;
 543                                 vsync-len = <10>;
 544                         };
 545                 };
 546         };
 547 };
 548
 549 &pwm1 {
 550         pinctrl-names = "default";
 551         pinctrl-0 = <&pinctrl_pwm1>;
 552         status = "okay";
 553 };
 554
 555 &ssi2 {
 556         fsl,mode = "i2s-slave";
 557         status = "okay";
 558 };
 559
 560 &uart1 {
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&pinctrl_uart1>;
 563         status = "okay";
 564 };
 565
 566 &usbh1 {
 567         vbus-supply = <&reg_usb_h1_vbus>;
 568         status = "okay";
 569 };
 570
 571 &usbotg {
 572         vbus-supply = <&reg_usb_otg_vbus>;
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&pinctrl_usbotg>;
 575         disable-over-current;
 576         status = "okay";
 577 };
 578
 579 &usdhc2 {
 580         pinctrl-names = "default";
 581         pinctrl-0 = <&pinctrl_usdhc2>;
 582         bus-width = <8>;
 583         cd-gpios = <&gpio2 2 0>;
 584         wp-gpios = <&gpio2 3 0>;
 585         status = "okay";
 586 };
 587
 588 &usdhc3 {
 589         pinctrl-names = "default";
 590         pinctrl-0 = <&pinctrl_usdhc3>;
 591         bus-width = <8>;
 592         cd-gpios = <&gpio2 0 0>;
 593         wp-gpios = <&gpio2 1 0>;
 594         status = "okay";
 595 };