arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         aliases {
  17                 mxcfb0 = &mxcfb1;
  18                 mxcfb1 = &mxcfb2;
  19                 mxcfb2 = &mxcfb3;
  20                 mxcfb3 = &mxcfb4;
  21         };
  22
  23         battery: max8903@0 {
  24                 compatible = "fsl,max8903-charger";
  25                 pinctrl-names = "default";
  26                 dok_input = <&gpio2 24 1>;
  27                 uok_input = <&gpio1 27 1>;
  28                 chg_input = <&gpio3 23 1>;
  29                 flt_input = <&gpio5 2 1>;
  30                 fsl,dcm_always_high;
  31                 fsl,dc_valid;
  32                 fsl,usb_valid;
  33                 status = "okay";
  34         };
  35
  36         memory {
  37                 reg = <0x10000000 0x40000000>;
  38         };
  39
  40         regulators {
  41                 compatible = "simple-bus";
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 reg_usb_otg_vbus: regulator@0 {
  46                         compatible = "regulator-fixed";
  47                         reg = <0>;
  48                         regulator-name = "usb_otg_vbus";
  49                         regulator-min-microvolt = <5000000>;
  50                         regulator-max-microvolt = <5000000>;
  51                         gpio = <&gpio3 22 0>;
  52                         enable-active-high;
  53                 };
  54
  55                 reg_usb_h1_vbus: regulator@1 {
  56                         compatible = "regulator-fixed";
  57                         reg = <1>;
  58                         regulator-name = "usb_h1_vbus";
  59                         regulator-min-microvolt = <5000000>;
  60                         regulator-max-microvolt = <5000000>;
  61                         gpio = <&gpio1 29 0>;
  62                         enable-active-high;
  63                 };
  64
  65                 reg_audio: regulator@2 {
  66                         compatible = "regulator-fixed";
  67                         reg = <2>;
  68                         regulator-name = "wm8962-supply";
  69                         gpio = <&gpio4 10 0>;
  70                         enable-active-high;
  71                 };
  72         };
  73
  74         gpio-keys {
  75                 compatible = "gpio-keys";
  76                 pinctrl-names = "default";
  77                 pinctrl-0 = <&pinctrl_gpio_keys>;
  78
  79                 power {
  80                         label = "Power Button";
  81                         gpios = <&gpio3 29 0>;
  82                         gpio-key,wakeup;
  83                         linux,code = <KEY_POWER>;
  84                 };
  85
  86                 volume-up {
  87                         label = "Volume Up";
  88                         gpios = <&gpio1 4 0>;
  89                         gpio-key,wakeup;
  90                         linux,code = <KEY_VOLUMEUP>;
  91                 };
  92
  93                 volume-down {
  94                         label = "Volume Down";
  95                         gpios = <&gpio1 5 0>;
  96                         gpio-key,wakeup;
  97                         linux,code = <KEY_VOLUMEDOWN>;
  98                 };
  99         };
 100
 101         sound {
 102                 compatible = "fsl,imx6q-sabresd-wm8962",
 103                            "fsl,imx-audio-wm8962";
 104                 model = "wm8962-audio";
 105                 ssi-controller = <&ssi2>;
 106                 audio-codec = <&codec>;
 107                 audio-routing =
 108                         "Headphone Jack", "HPOUTL",
 109                         "Headphone Jack", "HPOUTR",
 110                         "Ext Spk", "SPKOUTL",
 111                         "Ext Spk", "SPKOUTR",
 112                         "MICBIAS", "AMIC",
 113                         "IN3R", "MICBIAS",
 114                         "DMIC", "MICBIAS",
 115                         "DMICDAT", "DMIC";
 116                 mux-int-port = <2>;
 117                 mux-ext-port = <3>;
 118         };
 119
 120         sound-hdmi {
 121                 compatible = "fsl,imx6q-audio-hdmi",
 122                              "fsl,imx-audio-hdmi";
 123                 model = "imx-audio-hdmi";
 124                 hdmi-controller = <&hdmi_audio>;
 125         };
 126
 127         mxcfb1: fb@0 {
 128                 compatible = "fsl,mxc_sdc_fb";
 129                 disp_dev = "ldb";
 130                 interface_pix_fmt = "RGB666";
 131                 default_bpp = <16>;
 132                 int_clk = <0>;
 133                 late_init = <0>;
 134                 status = "disabled";
 135         };
 136
 137         mxcfb2: fb@1 {
 138                 compatible = "fsl,mxc_sdc_fb";
 139                 disp_dev = "hdmi";
 140                 interface_pix_fmt = "RGB24";
 141                 mode_str ="1920x1080M@60";
 142                 default_bpp = <24>;
 143                 int_clk = <0>;
 144                 late_init = <0>;
 145                 status = "disabled";
 146         };
 147
 148         mxcfb3: fb@2 {
 149                 compatible = "fsl,mxc_sdc_fb";
 150                 disp_dev = "lcd";
 151                 interface_pix_fmt = "RGB565";
 152                 mode_str ="CLAA-WVGA";
 153                 default_bpp = <16>;
 154                 int_clk = <0>;
 155                 late_init = <0>;
 156                 status = "disabled";
 157         };
 158
 159         mxcfb4: fb@3 {
 160                 compatible = "fsl,mxc_sdc_fb";
 161                 disp_dev = "ldb";
 162                 interface_pix_fmt = "RGB666";
 163                 default_bpp = <16>;
 164                 int_clk = <0>;
 165                 late_init = <0>;
 166                 status = "disabled";
 167         };
 168
 169         lcd@0 {
 170                 compatible = "fsl,lcd";
 171                 ipu_id = <0>;
 172                 disp_id = <0>;
 173                 default_ifmt = "RGB565";
 174                 pinctrl-names = "default";
 175                 pinctrl-0 = <&pinctrl_ipu1>;
 176                 status = "okay";
 177         };
 178
 179         backlight {
 180                 compatible = "pwm-backlight";
 181                 pwms = <&pwm1 0 5000000>;
 182                 brightness-levels = <0 4 8 16 32 64 128 255>;
 183                 default-brightness-level = <7>;
 184                 status = "okay";
 185         };
 186
 187         v4l2_out {
 188                 compatible = "fsl,mxc_v4l2_output";
 189                 status = "okay";
 190         };
 191 };
 192
 193 &audmux {
 194         pinctrl-names = "default";
 195         pinctrl-0 = <&pinctrl_audmux>;
 196         status = "okay";
 197 };
 198
 199 &ecspi1 {
 200         fsl,spi-num-chipselects = <1>;
 201         cs-gpios = <&gpio4 9 0>;
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_ecspi1>;
 204         status = "okay";
 205
 206         flash: m25p80@0 {
 207                 #address-cells = <1>;
 208                 #size-cells = <1>;
 209                 compatible = "st,m25p32";
 210                 spi-max-frequency = <20000000>;
 211                 reg = <0>;
 212         };
 213 };
 214
 215 &fec {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_enet>;
 218         phy-mode = "rgmii";
 219         phy-reset-gpios = <&gpio1 25 0>;
 220         status = "okay";
 221 };
 222
 223 &i2c1 {
 224         clock-frequency = <100000>;
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_i2c1>;
 227         status = "okay";
 228
 229         codec: wm8962@1a {
 230                 compatible = "wlf,wm8962";
 231                 reg = <0x1a>;
 232                 clocks = <&clks 201>;
 233                 DCVDD-supply = <&reg_audio>;
 234                 DBVDD-supply = <&reg_audio>;
 235                 AVDD-supply = <&reg_audio>;
 236                 CPVDD-supply = <&reg_audio>;
 237                 MICVDD-supply = <&reg_audio>;
 238                 PLLVDD-supply = <&reg_audio>;
 239                 SPKVDD1-supply = <&reg_audio>;
 240                 SPKVDD2-supply = <&reg_audio>;
 241                 gpio-cfg = <
 242                         0x0000 /* 0:Default */
 243                         0x0000 /* 1:Default */
 244                         0x0013 /* 2:FN_DMICCLK */
 245                         0x0000 /* 3:Default */
 246                         0x8014 /* 4:FN_DMICCDAT */
 247                         0x0000 /* 5:Default */
 248                 >;
 249        };
 250 };
 251
 252 &i2c2 {
 253         clock-frequency = <100000>;
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_i2c2>;
 256         status = "okay";
 257
 258         hdmi: edid@50 {
 259                 compatible = "fsl,imx6-hdmi-i2c";
 260                 reg = <0x50>;
 261         };
 262
 263         max11801@48 {
 264                 compatible = "maxim,max11801";
 265                 reg = <0x48>;
 266                 interrupt-parent = <&gpio3>;
 267                 interrupts = <26 2>;
 268                 work-mode = <1>;/*DCM mode*/
 269         };
 270 };
 271
 272 &i2c3 {
 273         clock-frequency = <100000>;
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_i2c3>;
 276         status = "okay";
 277
 278         egalax_ts@04 {
 279                 compatible = "eeti,egalax_ts";
 280                 reg = <0x04>;
 281                 interrupt-parent = <&gpio6>;
 282                 interrupts = <7 2>;
 283                 wakeup-gpios = <&gpio6 7 0>;
 284         };
 285 };
 286
 287 &iomuxc {
 288         pinctrl-names = "default";
 289         pinctrl-0 = <&pinctrl_hog>;
 290
 291         imx6qdl-sabresd {
 292                 pinctrl_hog: hoggrp {
 293                         fsl,pins = <
 294                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
 295                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
 296                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
 297                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
 298                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 299                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
 300                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 301                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
 302                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
 303                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
 304                                 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
 305                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 306                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
 307                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
 308                         >;
 309                 };
 310
 311                 pinctrl_audmux: audmuxgrp {
 312                         fsl,pins = <
 313                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 314                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 315                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 316                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 317                         >;
 318                 };
 319
 320                 pinctrl_ecspi1: ecspi1grp {
 321                         fsl,pins = <
 322                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 323                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 324                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 325                         >;
 326                 };
 327
 328                 pinctrl_enet: enetgrp {
 329                         fsl,pins = <
 330                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 331                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 332                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 333                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 334                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 335                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 336                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 337                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 338                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 339                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 340                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 341                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 342                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 343                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 344                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 345                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 346                         >;
 347                 };
 348
 349                 pinctrl_gpio_keys: gpio_keysgrp {
 350                         fsl,pins = <
 351                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
 352                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x80000000
 353                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x80000000
 354                         >;
 355                 };
 356
 357                 pinctrl_hdmi_cec: hdmicecgrp {
 358                         fsl,pins = <
 359                                 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 360                         >;
 361                 };
 362
 363                 pinctrl_hdmi_hdcp: hdmihdcpgrp {
 364                         fsl,pins = <
 365                                 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 366                                 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 367                         >;
 368                 };
 369
 370                 pinctrl_i2c1: i2c1grp {
 371                         fsl,pins = <
 372                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 373                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 374                         >;
 375                 };
 376
 377                 pinctrl_i2c2: i2c2grp {
 378                         fsl,pins = <
 379                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 380                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 381                          >;
 382                 };
 383
 384                 pinctrl_i2c3: i2c3grp {
 385                         fsl,pins = <
 386                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 387                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 388                         >;
 389                 };
 390
 391                 pinctrl_ipu1: ipu1grp {
 392                         fsl,pins = <
 393                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 394                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 395                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 396                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 397                                 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
 398                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 399                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 400                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 401                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 402                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 403                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 404                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 405                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 406                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 407                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 408                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 409                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 410                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 411                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 412                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 413                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 414                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 415                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 416                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 417                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 418                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 419                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 420                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 421                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 422                         >;
 423                 };
 424
 425                 pinctrl_pwm1: pwm1grp {
 426                         fsl,pins = <
 427                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 428                         >;
 429                 };
 430
 431                 pinctrl_uart1: uart1grp {
 432                         fsl,pins = <
 433                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 434                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 435                         >;
 436                 };
 437
 438                 pinctrl_uart5_1: uart5grp-1 {
 439                         fsl,pins = <
 440                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 441                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 442                                 MX6QDL_PAD_KEY_COL4__UART5_RTS_B        0x1b0b1
 443                                 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B        0x1b0b1
 444                         >;
 445                 };
 446
 447                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 448                         fsl,pins = <
 449                                 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA      0x1b0b1
 450                                 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA      0x1b0b1
 451                                 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B        0x1b0b1
 452                                 MX6QDL_PAD_KEY_COL4__UART5_CTS_B        0x1b0b1
 453                         >;
 454                 };
 455
 456                 pinctrl_usbotg: usbotggrp {
 457                         fsl,pins = <
 458                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 459                         >;
 460                 };
 461
 462                 pinctrl_usdhc2: usdhc2grp {
 463                         fsl,pins = <
 464                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 465                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 466                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 467                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 468                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 469                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 470                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 471                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 472                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 473                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 474                         >;
 475                 };
 476
 477                 pinctrl_usdhc3: usdhc3grp {
 478                         fsl,pins = <
 479                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 480                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 481                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 482                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 483                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 484                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 485                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 486                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 487                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 488                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 489                         >;
 490                 };
 491         };
 492 };
 493
 494 &dcic1 {
 495         dcic_id = <0>;
 496         dcic_mux = "dcic-hdmi";
 497         status = "okay";
 498 };
 499
 500 &dcic2 {
 501         dcic_id = <1>;
 502         dcic_mux = "dcic-lvds1";
 503         status = "okay";
 504 };
 505
 506 &hdmi_audio {
 507         status = "okay";
 508 };
 509
 510 &hdmi_cec {
 511         pinctrl-names = "default";
 512         pinctrl-0 = <&pinctrl_hdmi_cec>;
 513         status = "okay";
 514 };
 515
 516 &hdmi_core {
 517         ipu_id = <0>;
 518         disp_id = <0>;
 519         status = "okay";
 520 };
 521
 522 &hdmi_video {
 523         fsl,phy_reg_vlev = <0x0294>;
 524         fsl,phy_reg_cksymtx = <0x800d>;
 525         status = "okay";
 526 };
 527
 528 &ldb {
 529         status = "okay";
 530
 531         lvds-channel@0 {
 532                 fsl,data-mapping = "spwg";
 533                 fsl,data-width = <18>;
 534                 status = "okay";
 535
 536                 display-timings {
 537                         native-mode = <&timing0>;
 538                         timing0: hsd100pxn1 {
 539                                 clock-frequency = <65000000>;
 540                                 hactive = <1024>;
 541                                 vactive = <768>;
 542                                 hback-porch = <220>;
 543                                 hfront-porch = <40>;
 544                                 vback-porch = <21>;
 545                                 vfront-porch = <7>;
 546                                 hsync-len = <60>;
 547                                 vsync-len = <10>;
 548                         };
 549                 };
 550         };
 551
 552         lvds-channel@1 {
 553                 fsl,data-mapping = "spwg";
 554                 fsl,data-width = <18>;
 555                 primary;
 556                 status = "okay";
 557
 558                 display-timings {
 559                         native-mode = <&timing1>;
 560                         timing1: hsd100pxn1 {
 561                                 clock-frequency = <65000000>;
 562                                 hactive = <1024>;
 563                                 vactive = <768>;
 564                                 hback-porch = <220>;
 565                                 hfront-porch = <40>;
 566                                 vback-porch = <21>;
 567                                 vfront-porch = <7>;
 568                                 hsync-len = <60>;
 569                                 vsync-len = <10>;
 570                         };
 571                 };
 572         };
 573 };
 574
 575 &pwm1 {
 576         pinctrl-names = "default";
 577         pinctrl-0 = <&pinctrl_pwm1>;
 578         status = "okay";
 579 };
 580
 581 &ssi2 {
 582         fsl,mode = "i2s-slave";
 583         status = "okay";
 584 };
 585
 586 &uart1 {
 587         pinctrl-names = "default";
 588         pinctrl-0 = <&pinctrl_uart1>;
 589         status = "okay";
 590 };
 591
 592 &usbh1 {
 593         vbus-supply = <&reg_usb_h1_vbus>;
 594         status = "okay";
 595 };
 596
 597 &usbotg {
 598         vbus-supply = <&reg_usb_otg_vbus>;
 599         pinctrl-names = "default";
 600         pinctrl-0 = <&pinctrl_usbotg>;
 601         disable-over-current;
 602         status = "okay";
 603 };
 604
 605 &usdhc2 {
 606         pinctrl-names = "default";
 607         pinctrl-0 = <&pinctrl_usdhc2>;
 608         bus-width = <8>;
 609         cd-gpios = <&gpio2 2 0>;
 610         wp-gpios = <&gpio2 3 0>;
 611         status = "okay";
 612 };
 613
 614 &usdhc3 {
 615         pinctrl-names = "default";
 616         pinctrl-0 = <&pinctrl_usdhc3>;
 617         bus-width = <8>;
 618         cd-gpios = <&gpio2 0 0>;
 619         wp-gpios = <&gpio2 1 0>;
 620         status = "okay";
 621 };