arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         aliases {
  17                 mxcfb0 = &mxcfb1;
  18                 mxcfb1 = &mxcfb2;
  19                 mxcfb2 = &mxcfb3;
  20                 mxcfb3 = &mxcfb4;
  21         };
  22
  23         battery: max8903@0 {
  24                 compatible = "fsl,max8903-charger";
  25                 pinctrl-names = "default";
  26                 dok_input = <&gpio2 24 1>;
  27                 uok_input = <&gpio1 27 1>;
  28                 chg_input = <&gpio3 23 1>;
  29                 flt_input = <&gpio5 2 1>;
  30                 fsl,dcm_always_high;
  31                 fsl,dc_valid;
  32                 fsl,usb_valid;
  33                 status = "okay";
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38
  39                 charger-led {
  40                         gpios = <&gpio1 2 0>;
  41                         linux,default-trigger = "max8903-charger-charging";
  42                         retain-state-suspended;
  43                 };
  44         };
  45
  46         memory {
  47                 reg = <0x10000000 0x40000000>;
  48         };
  49
  50         regulators {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 reg_usb_otg_vbus: regulator@0 {
  56                         compatible = "regulator-fixed";
  57                         reg = <0>;
  58                         regulator-name = "usb_otg_vbus";
  59                         regulator-min-microvolt = <5000000>;
  60                         regulator-max-microvolt = <5000000>;
  61                         gpio = <&gpio3 22 0>;
  62                         enable-active-high;
  63                 };
  64
  65                 reg_usb_h1_vbus: regulator@1 {
  66                         compatible = "regulator-fixed";
  67                         reg = <1>;
  68                         regulator-name = "usb_h1_vbus";
  69                         regulator-min-microvolt = <5000000>;
  70                         regulator-max-microvolt = <5000000>;
  71                         gpio = <&gpio1 29 0>;
  72                         enable-active-high;
  73                 };
  74
  75                 reg_audio: regulator@2 {
  76                         compatible = "regulator-fixed";
  77                         reg = <2>;
  78                         regulator-name = "wm8962-supply";
  79                         gpio = <&gpio4 10 0>;
  80                         enable-active-high;
  81                 };
  82
  83                 reg_sensor: regulator@3 {
  84                         compatible = "regulator-fixed";
  85                         reg = <3>;
  86                         regulator-name = "sensor-supply";
  87                         regulator-min-microvolt = <3300000>;
  88                         regulator-max-microvolt = <3300000>;
  89                         gpio = <&gpio2 31 0>;
  90                         startup-delay-us = <500>;
  91                         enable-active-high;
  92                 };
  93         };
  94
  95         gpio-keys {
  96                 compatible = "gpio-keys";
  97                 pinctrl-names = "default";
  98                 pinctrl-0 = <&pinctrl_gpio_keys>;
  99
 100                 power {
 101                         label = "Power Button";
 102                         gpios = <&gpio3 29 0>;
 103                         gpio-key,wakeup;
 104                         linux,code = <KEY_POWER>;
 105                 };
 106
 107                 volume-up {
 108                         label = "Volume Up";
 109                         gpios = <&gpio1 4 0>;
 110                         gpio-key,wakeup;
 111                         linux,code = <KEY_VOLUMEUP>;
 112                 };
 113
 114                 volume-down {
 115                         label = "Volume Down";
 116                         gpios = <&gpio1 5 0>;
 117                         gpio-key,wakeup;
 118                         linux,code = <KEY_VOLUMEDOWN>;
 119                 };
 120         };
 121
 122         sound {
 123                 compatible = "fsl,imx6q-sabresd-wm8962",
 124                            "fsl,imx-audio-wm8962";
 125                 model = "wm8962-audio";
 126                 ssi-controller = <&ssi2>;
 127                 audio-codec = <&codec>;
 128                 audio-routing =
 129                         "Headphone Jack", "HPOUTL",
 130                         "Headphone Jack", "HPOUTR",
 131                         "Ext Spk", "SPKOUTL",
 132                         "Ext Spk", "SPKOUTR",
 133                         "MICBIAS", "AMIC",
 134                         "IN3R", "MICBIAS",
 135                         "DMIC", "MICBIAS",
 136                         "DMICDAT", "DMIC";
 137                 mux-int-port = <2>;
 138                 mux-ext-port = <3>;
 139         };
 140
 141         sound-hdmi {
 142                 compatible = "fsl,imx6q-audio-hdmi",
 143                              "fsl,imx-audio-hdmi";
 144                 model = "imx-audio-hdmi";
 145                 hdmi-controller = <&hdmi_audio>;
 146         };
 147
 148         mxcfb1: fb@0 {
 149                 compatible = "fsl,mxc_sdc_fb";
 150                 disp_dev = "ldb";
 151                 interface_pix_fmt = "RGB666";
 152                 default_bpp = <16>;
 153                 int_clk = <0>;
 154                 late_init = <0>;
 155                 status = "disabled";
 156         };
 157
 158         mxcfb2: fb@1 {
 159                 compatible = "fsl,mxc_sdc_fb";
 160                 disp_dev = "hdmi";
 161                 interface_pix_fmt = "RGB24";
 162                 mode_str ="1920x1080M@60";
 163                 default_bpp = <24>;
 164                 int_clk = <0>;
 165                 late_init = <0>;
 166                 status = "disabled";
 167         };
 168
 169         mxcfb3: fb@2 {
 170                 compatible = "fsl,mxc_sdc_fb";
 171                 disp_dev = "lcd";
 172                 interface_pix_fmt = "RGB565";
 173                 mode_str ="CLAA-WVGA";
 174                 default_bpp = <16>;
 175                 int_clk = <0>;
 176                 late_init = <0>;
 177                 status = "disabled";
 178         };
 179
 180         mxcfb4: fb@3 {
 181                 compatible = "fsl,mxc_sdc_fb";
 182                 disp_dev = "ldb";
 183                 interface_pix_fmt = "RGB666";
 184                 default_bpp = <16>;
 185                 int_clk = <0>;
 186                 late_init = <0>;
 187                 status = "disabled";
 188         };
 189
 190         lcd@0 {
 191                 compatible = "fsl,lcd";
 192                 ipu_id = <0>;
 193                 disp_id = <0>;
 194                 default_ifmt = "RGB565";
 195                 pinctrl-names = "default";
 196                 pinctrl-0 = <&pinctrl_ipu1>;
 197                 status = "okay";
 198         };
 199
 200         backlight {
 201                 compatible = "pwm-backlight";
 202                 pwms = <&pwm1 0 5000000>;
 203                 brightness-levels = <0 4 8 16 32 64 128 255>;
 204                 default-brightness-level = <7>;
 205                 status = "okay";
 206         };
 207
 208         v4l2_out {
 209                 compatible = "fsl,mxc_v4l2_output";
 210                 status = "okay";
 211         };
 212 };
 213
 214 &audmux {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_audmux>;
 217         status = "okay";
 218 };
 219
 220 &ecspi1 {
 221         fsl,spi-num-chipselects = <1>;
 222         cs-gpios = <&gpio4 9 0>;
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_ecspi1>;
 225         status = "okay";
 226
 227         flash: m25p80@0 {
 228                 #address-cells = <1>;
 229                 #size-cells = <1>;
 230                 compatible = "st,m25p32";
 231                 spi-max-frequency = <20000000>;
 232                 reg = <0>;
 233         };
 234 };
 235
 236 &fec {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&pinctrl_enet>;
 239         phy-mode = "rgmii";
 240         phy-reset-gpios = <&gpio1 25 0>;
 241         status = "okay";
 242 };
 243
 244 &i2c1 {
 245         clock-frequency = <100000>;
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_i2c1>;
 248         status = "okay";
 249
 250         codec: wm8962@1a {
 251                 compatible = "wlf,wm8962";
 252                 reg = <0x1a>;
 253                 clocks = <&clks 201>;
 254                 DCVDD-supply = <&reg_audio>;
 255                 DBVDD-supply = <&reg_audio>;
 256                 AVDD-supply = <&reg_audio>;
 257                 CPVDD-supply = <&reg_audio>;
 258                 MICVDD-supply = <&reg_audio>;
 259                 PLLVDD-supply = <&reg_audio>;
 260                 SPKVDD1-supply = <&reg_audio>;
 261                 SPKVDD2-supply = <&reg_audio>;
 262                 gpio-cfg = <
 263                         0x0000 /* 0:Default */
 264                         0x0000 /* 1:Default */
 265                         0x0013 /* 2:FN_DMICCLK */
 266                         0x0000 /* 3:Default */
 267                         0x8014 /* 4:FN_DMICCDAT */
 268                         0x0000 /* 5:Default */
 269                 >;
 270        };
 271
 272         mma8451@1c {
 273                 compatible = "fsl,mma8451";
 274                 reg = <0x1c>;
 275                 position = <0>;
 276                 vdd-supply = <&reg_sensor>;
 277                 vddio-supply = <&reg_sensor>;
 278                 interrupt-parent = <&gpio1>;
 279                 interrupts = <18 8>;
 280                 interrupt-route = <1>;
 281         };
 282 };
 283
 284 &i2c2 {
 285         clock-frequency = <100000>;
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_i2c2>;
 288         status = "okay";
 289
 290         hdmi: edid@50 {
 291                 compatible = "fsl,imx6-hdmi-i2c";
 292                 reg = <0x50>;
 293         };
 294
 295         max11801@48 {
 296                 compatible = "maxim,max11801";
 297                 reg = <0x48>;
 298                 interrupt-parent = <&gpio3>;
 299                 interrupts = <26 2>;
 300                 work-mode = <1>;/*DCM mode*/
 301         };
 302 };
 303
 304 &i2c3 {
 305         clock-frequency = <100000>;
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_i2c3>;
 308         status = "okay";
 309
 310         egalax_ts@04 {
 311                 compatible = "eeti,egalax_ts";
 312                 reg = <0x04>;
 313                 interrupt-parent = <&gpio6>;
 314                 interrupts = <7 2>;
 315                 wakeup-gpios = <&gpio6 7 0>;
 316         };
 317
 318         mag3110@0e {
 319                 compatible = "fsl,mag3110";
 320                 reg = <0x0e>;
 321                 position = <2>;
 322                 vdd-supply = <&reg_sensor>;
 323                 vddio-supply = <&reg_sensor>;
 324                 interrupt-parent = <&gpio3>;
 325                 interrupts = <16 1>;
 326         };
 327 };
 328
 329 &iomuxc {
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&pinctrl_hog>;
 332
 333         imx6qdl-sabresd {
 334                 pinctrl_hog: hoggrp {
 335                         fsl,pins = <
 336                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
 337                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
 338                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
 339                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
 340                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 341                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
 342                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 343                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
 344                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
 345                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
 346                                 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
 347                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 348                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
 349                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
 350                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
 351                                 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
 352                                 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
 353                         >;
 354                 };
 355
 356                 pinctrl_audmux: audmuxgrp {
 357                         fsl,pins = <
 358                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 359                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 360                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 361                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 362                         >;
 363                 };
 364
 365                 pinctrl_ecspi1: ecspi1grp {
 366                         fsl,pins = <
 367                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 368                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 369                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 370                         >;
 371                 };
 372
 373                 pinctrl_enet: enetgrp {
 374                         fsl,pins = <
 375                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 376                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 377                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 378                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 379                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 380                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 381                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 382                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 383                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 384                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 385                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 386                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 387                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 388                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 389                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 390                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 391                         >;
 392                 };
 393
 394                 pinctrl_enet_irq: enetirqgrp {
 395                         fsl,pins = <
 396                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 397                         >;
 398                 };
 399
 400                 pinctrl_gpio_keys: gpio_keysgrp {
 401                         fsl,pins = <
 402                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
 403                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x80000000
 404                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x80000000
 405                         >;
 406                 };
 407
 408                 pinctrl_hdmi_cec: hdmicecgrp {
 409                         fsl,pins = <
 410                                 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 411                         >;
 412                 };
 413
 414                 pinctrl_hdmi_hdcp: hdmihdcpgrp {
 415                         fsl,pins = <
 416                                 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 417                                 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 418                         >;
 419                 };
 420
 421                 pinctrl_i2c1: i2c1grp {
 422                         fsl,pins = <
 423                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 424                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 425                         >;
 426                 };
 427
 428                 pinctrl_i2c2: i2c2grp {
 429                         fsl,pins = <
 430                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 431                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 432                          >;
 433                 };
 434
 435                 pinctrl_i2c3: i2c3grp {
 436                         fsl,pins = <
 437                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 438                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 439                         >;
 440                 };
 441
 442                 pinctrl_ipu1: ipu1grp {
 443                         fsl,pins = <
 444                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 445                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 446                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 447                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 448                                 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
 449                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 450                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 451                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 452                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 453                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 454                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 455                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 456                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 457                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 458                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 459                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 460                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 461                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 462                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 463                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 464                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 465                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 466                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 467                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 468                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 469                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 470                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 471                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 472                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 473                         >;
 474                 };
 475
 476                 pinctrl_pwm1: pwm1grp {
 477                         fsl,pins = <
 478                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 479                         >;
 480                 };
 481
 482                 pinctrl_uart1: uart1grp {
 483                         fsl,pins = <
 484                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 485                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 486                         >;
 487                 };
 488
 489                 pinctrl_uart5_1: uart5grp-1 {
 490                         fsl,pins = <
 491                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 492                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 493                                 MX6QDL_PAD_KEY_COL4__UART5_RTS_B        0x1b0b1
 494                                 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B        0x1b0b1
 495                         >;
 496                 };
 497
 498                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 499                         fsl,pins = <
 500                                 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA      0x1b0b1
 501                                 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA      0x1b0b1
 502                                 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B        0x1b0b1
 503                                 MX6QDL_PAD_KEY_COL4__UART5_CTS_B        0x1b0b1
 504                         >;
 505                 };
 506
 507                 pinctrl_usbotg: usbotggrp {
 508                         fsl,pins = <
 509                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 510                         >;
 511                 };
 512
 513                 pinctrl_usdhc2: usdhc2grp {
 514                         fsl,pins = <
 515                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 516                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 517                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 518                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 519                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 520                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 521                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 522                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 523                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 524                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 525                         >;
 526                 };
 527
 528                 pinctrl_usdhc3: usdhc3grp {
 529                         fsl,pins = <
 530                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 531                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 532                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 533                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 534                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 535                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 536                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 537                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 538                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 539                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 540                         >;
 541                 };
 542         };
 543 };
 544
 545 &dcic1 {
 546         dcic_id = <0>;
 547         dcic_mux = "dcic-hdmi";
 548         status = "okay";
 549 };
 550
 551 &dcic2 {
 552         dcic_id = <1>;
 553         dcic_mux = "dcic-lvds1";
 554         status = "okay";
 555 };
 556
 557 &gpc {
 558         /* use ldo-bypass, u-boot will check it and configure */
 559         fsl,ldo-bypass = <1>;
 560 };
 561
 562 &hdmi_audio {
 563         status = "okay";
 564 };
 565
 566 &hdmi_cec {
 567         pinctrl-names = "default";
 568         pinctrl-0 = <&pinctrl_hdmi_cec>;
 569         status = "okay";
 570 };
 571
 572 &hdmi_core {
 573         ipu_id = <0>;
 574         disp_id = <0>;
 575         status = "okay";
 576 };
 577
 578 &hdmi_video {
 579         fsl,phy_reg_vlev = <0x0294>;
 580         fsl,phy_reg_cksymtx = <0x800d>;
 581         status = "okay";
 582 };
 583
 584 &ldb {
 585         status = "okay";
 586
 587         lvds-channel@0 {
 588                 fsl,data-mapping = "spwg";
 589                 fsl,data-width = <18>;
 590                 status = "okay";
 591
 592                 display-timings {
 593                         native-mode = <&timing0>;
 594                         timing0: hsd100pxn1 {
 595                                 clock-frequency = <65000000>;
 596                                 hactive = <1024>;
 597                                 vactive = <768>;
 598                                 hback-porch = <220>;
 599                                 hfront-porch = <40>;
 600                                 vback-porch = <21>;
 601                                 vfront-porch = <7>;
 602                                 hsync-len = <60>;
 603                                 vsync-len = <10>;
 604                         };
 605                 };
 606         };
 607
 608         lvds-channel@1 {
 609                 fsl,data-mapping = "spwg";
 610                 fsl,data-width = <18>;
 611                 primary;
 612                 status = "okay";
 613
 614                 display-timings {
 615                         native-mode = <&timing1>;
 616                         timing1: hsd100pxn1 {
 617                                 clock-frequency = <65000000>;
 618                                 hactive = <1024>;
 619                                 vactive = <768>;
 620                                 hback-porch = <220>;
 621                                 hfront-porch = <40>;
 622                                 vback-porch = <21>;
 623                                 vfront-porch = <7>;
 624                                 hsync-len = <60>;
 625                                 vsync-len = <10>;
 626                         };
 627                 };
 628         };
 629 };
 630
 631 &pwm1 {
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&pinctrl_pwm1>;
 634         status = "okay";
 635 };
 636
 637 &ssi2 {
 638         fsl,mode = "i2s-slave";
 639         status = "okay";
 640 };
 641
 642 &uart1 {
 643         pinctrl-names = "default";
 644         pinctrl-0 = <&pinctrl_uart1>;
 645         status = "okay";
 646 };
 647
 648 &usbh1 {
 649         vbus-supply = <&reg_usb_h1_vbus>;
 650         status = "okay";
 651 };
 652
 653 &usbotg {
 654         vbus-supply = <&reg_usb_otg_vbus>;
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&pinctrl_usbotg>;
 657         disable-over-current;
 658         status = "okay";
 659 };
 660
 661 &usdhc2 {
 662         pinctrl-names = "default";
 663         pinctrl-0 = <&pinctrl_usdhc2>;
 664         bus-width = <8>;
 665         cd-gpios = <&gpio2 2 0>;
 666         wp-gpios = <&gpio2 3 0>;
 667         status = "okay";
 668 };
 669
 670 &usdhc3 {
 671         pinctrl-names = "default";
 672         pinctrl-0 = <&pinctrl_usdhc3>;
 673         bus-width = <8>;
 674         cd-gpios = <&gpio2 0 0>;
 675         wp-gpios = <&gpio2 1 0>;
 676         status = "okay";
 677 };