arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         aliases {
  17                 mxcfb0 = &mxcfb1;
  18                 mxcfb1 = &mxcfb2;
  19                 mxcfb2 = &mxcfb3;
  20                 mxcfb3 = &mxcfb4;
  21         };
  22
  23         memory {
  24                 reg = <0x10000000 0x40000000>;
  25         };
  26
  27         regulators {
  28                 compatible = "simple-bus";
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 reg_usb_otg_vbus: regulator@0 {
  33                         compatible = "regulator-fixed";
  34                         reg = <0>;
  35                         regulator-name = "usb_otg_vbus";
  36                         regulator-min-microvolt = <5000000>;
  37                         regulator-max-microvolt = <5000000>;
  38                         gpio = <&gpio3 22 0>;
  39                         enable-active-high;
  40                 };
  41
  42                 reg_usb_h1_vbus: regulator@1 {
  43                         compatible = "regulator-fixed";
  44                         reg = <1>;
  45                         regulator-name = "usb_h1_vbus";
  46                         regulator-min-microvolt = <5000000>;
  47                         regulator-max-microvolt = <5000000>;
  48                         gpio = <&gpio1 29 0>;
  49                         enable-active-high;
  50                 };
  51
  52                 reg_audio: regulator@2 {
  53                         compatible = "regulator-fixed";
  54                         reg = <2>;
  55                         regulator-name = "wm8962-supply";
  56                         gpio = <&gpio4 10 0>;
  57                         enable-active-high;
  58                 };
  59         };
  60
  61         gpio-keys {
  62                 compatible = "gpio-keys";
  63                 pinctrl-names = "default";
  64                 pinctrl-0 = <&pinctrl_gpio_keys>;
  65
  66                 power {
  67                         label = "Power Button";
  68                         gpios = <&gpio3 29 0>;
  69                         gpio-key,wakeup;
  70                         linux,code = <KEY_POWER>;
  71                 };
  72
  73                 volume-up {
  74                         label = "Volume Up";
  75                         gpios = <&gpio1 4 0>;
  76                         gpio-key,wakeup;
  77                         linux,code = <KEY_VOLUMEUP>;
  78                 };
  79
  80                 volume-down {
  81                         label = "Volume Down";
  82                         gpios = <&gpio1 5 0>;
  83                         gpio-key,wakeup;
  84                         linux,code = <KEY_VOLUMEDOWN>;
  85                 };
  86         };
  87
  88         sound {
  89                 compatible = "fsl,imx6q-sabresd-wm8962",
  90                            "fsl,imx-audio-wm8962";
  91                 model = "wm8962-audio";
  92                 ssi-controller = <&ssi2>;
  93                 audio-codec = <&codec>;
  94                 audio-routing =
  95                         "Headphone Jack", "HPOUTL",
  96                         "Headphone Jack", "HPOUTR",
  97                         "Ext Spk", "SPKOUTL",
  98                         "Ext Spk", "SPKOUTR",
  99                         "MICBIAS", "AMIC",
 100                         "IN3R", "MICBIAS",
 101                         "DMIC", "MICBIAS",
 102                         "DMICDAT", "DMIC";
 103                 mux-int-port = <2>;
 104                 mux-ext-port = <3>;
 105         };
 106
 107         mxcfb1: fb@0 {
 108                 compatible = "fsl,mxc_sdc_fb";
 109                 disp_dev = "ldb";
 110                 interface_pix_fmt = "RGB666";
 111                 default_bpp = <16>;
 112                 int_clk = <0>;
 113                 late_init = <0>;
 114                 status = "disabled";
 115         };
 116
 117         mxcfb2: fb@1 {
 118                 compatible = "fsl,mxc_sdc_fb";
 119                 disp_dev = "hdmi";
 120                 interface_pix_fmt = "RGB24";
 121                 mode_str ="1920x1080M@60";
 122                 default_bpp = <24>;
 123                 int_clk = <0>;
 124                 late_init = <0>;
 125                 status = "disabled";
 126         };
 127
 128         mxcfb3: fb@2 {
 129                 compatible = "fsl,mxc_sdc_fb";
 130                 disp_dev = "lcd";
 131                 interface_pix_fmt = "RGB565";
 132                 mode_str ="CLAA-WVGA";
 133                 default_bpp = <16>;
 134                 int_clk = <0>;
 135                 late_init = <0>;
 136                 status = "disabled";
 137         };
 138
 139         mxcfb4: fb@3 {
 140                 compatible = "fsl,mxc_sdc_fb";
 141                 disp_dev = "ldb";
 142                 interface_pix_fmt = "RGB666";
 143                 default_bpp = <16>;
 144                 int_clk = <0>;
 145                 late_init = <0>;
 146                 status = "disabled";
 147         };
 148
 149         lcd@0 {
 150                 compatible = "fsl,lcd";
 151                 ipu_id = <0>;
 152                 disp_id = <0>;
 153                 default_ifmt = "RGB565";
 154                 pinctrl-names = "default";
 155                 pinctrl-0 = <&pinctrl_ipu1>;
 156                 status = "okay";
 157         };
 158
 159         backlight {
 160                 compatible = "pwm-backlight";
 161                 pwms = <&pwm1 0 5000000>;
 162                 brightness-levels = <0 4 8 16 32 64 128 255>;
 163                 default-brightness-level = <7>;
 164                 status = "okay";
 165         };
 166
 167         v4l2_out {
 168                 compatible = "fsl,mxc_v4l2_output";
 169                 status = "okay";
 170         };
 171 };
 172
 173 &audmux {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_audmux>;
 176         status = "okay";
 177 };
 178
 179 &ecspi1 {
 180         fsl,spi-num-chipselects = <1>;
 181         cs-gpios = <&gpio4 9 0>;
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_ecspi1>;
 184         status = "okay";
 185
 186         flash: m25p80@0 {
 187                 #address-cells = <1>;
 188                 #size-cells = <1>;
 189                 compatible = "st,m25p32";
 190                 spi-max-frequency = <20000000>;
 191                 reg = <0>;
 192         };
 193 };
 194
 195 &fec {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_enet>;
 198         phy-mode = "rgmii";
 199         phy-reset-gpios = <&gpio1 25 0>;
 200         status = "okay";
 201 };
 202
 203 &i2c1 {
 204         clock-frequency = <100000>;
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_i2c1>;
 207         status = "okay";
 208
 209         codec: wm8962@1a {
 210                 compatible = "wlf,wm8962";
 211                 reg = <0x1a>;
 212                 clocks = <&clks 201>;
 213                 DCVDD-supply = <&reg_audio>;
 214                 DBVDD-supply = <&reg_audio>;
 215                 AVDD-supply = <&reg_audio>;
 216                 CPVDD-supply = <&reg_audio>;
 217                 MICVDD-supply = <&reg_audio>;
 218                 PLLVDD-supply = <&reg_audio>;
 219                 SPKVDD1-supply = <&reg_audio>;
 220                 SPKVDD2-supply = <&reg_audio>;
 221                 gpio-cfg = <
 222                         0x0000 /* 0:Default */
 223                         0x0000 /* 1:Default */
 224                         0x0013 /* 2:FN_DMICCLK */
 225                         0x0000 /* 3:Default */
 226                         0x8014 /* 4:FN_DMICCDAT */
 227                         0x0000 /* 5:Default */
 228                 >;
 229        };
 230 };
 231
 232 &i2c3 {
 233         clock-frequency = <100000>;
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&pinctrl_i2c3>;
 236         status = "okay";
 237
 238         egalax_ts@04 {
 239                 compatible = "eeti,egalax_ts";
 240                 reg = <0x04>;
 241                 interrupt-parent = <&gpio6>;
 242                 interrupts = <7 2>;
 243                 wakeup-gpios = <&gpio6 7 0>;
 244         };
 245 };
 246
 247 &iomuxc {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_hog>;
 250
 251         imx6qdl-sabresd {
 252                 pinctrl_hog: hoggrp {
 253                         fsl,pins = <
 254                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
 255                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
 256                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
 257                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
 258                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 259                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
 260                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 261                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
 262                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
 263                         >;
 264                 };
 265
 266                 pinctrl_audmux: audmuxgrp {
 267                         fsl,pins = <
 268                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 269                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 270                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 271                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 272                         >;
 273                 };
 274
 275                 pinctrl_ecspi1: ecspi1grp {
 276                         fsl,pins = <
 277                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 278                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 279                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 280                         >;
 281                 };
 282
 283                 pinctrl_enet: enetgrp {
 284                         fsl,pins = <
 285                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 286                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 287                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 288                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 289                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 290                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 291                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 292                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 293                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 294                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 295                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 296                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 297                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 298                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 299                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 300                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 301                         >;
 302                 };
 303
 304                 pinctrl_gpio_keys: gpio_keysgrp {
 305                         fsl,pins = <
 306                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
 307                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x80000000
 308                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x80000000
 309                         >;
 310                 };
 311
 312                 pinctrl_i2c1: i2c1grp {
 313                         fsl,pins = <
 314                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 315                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 316                         >;
 317                 };
 318
 319                 pinctrl_i2c3: i2c3grp {
 320                         fsl,pins = <
 321                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 322                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 323                         >;
 324                 };
 325
 326                 pinctrl_ipu1: ipu1grp {
 327                         fsl,pins = <
 328                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 329                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 330                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 331                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 332                                 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
 333                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 334                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 335                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 336                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 337                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 338                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 339                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 340                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 341                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 342                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 343                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 344                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 345                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 346                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 347                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 348                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 349                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 350                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 351                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 352                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 353                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 354                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 355                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 356                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 357                         >;
 358                 };
 359
 360                 pinctrl_pwm1: pwm1grp {
 361                         fsl,pins = <
 362                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 363                         >;
 364                 };
 365
 366                 pinctrl_uart1: uart1grp {
 367                         fsl,pins = <
 368                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 369                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 370                         >;
 371                 };
 372
 373                 pinctrl_usbotg: usbotggrp {
 374                         fsl,pins = <
 375                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 376                         >;
 377                 };
 378
 379                 pinctrl_usdhc2: usdhc2grp {
 380                         fsl,pins = <
 381                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 382                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 383                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 384                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 385                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 386                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 387                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 388                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 389                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 390                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 391                         >;
 392                 };
 393
 394                 pinctrl_usdhc3: usdhc3grp {
 395                         fsl,pins = <
 396                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 397                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 398                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 399                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 400                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 401                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 402                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 403                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 404                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 405                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 406                         >;
 407                 };
 408         };
 409 };
 410
 411 &ldb {
 412         status = "okay";
 413
 414         lvds-channel@0 {
 415                 fsl,data-mapping = "spwg";
 416                 fsl,data-width = <18>;
 417                 status = "okay";
 418
 419                 display-timings {
 420                         native-mode = <&timing0>;
 421                         timing0: hsd100pxn1 {
 422                                 clock-frequency = <65000000>;
 423                                 hactive = <1024>;
 424                                 vactive = <768>;
 425                                 hback-porch = <220>;
 426                                 hfront-porch = <40>;
 427                                 vback-porch = <21>;
 428                                 vfront-porch = <7>;
 429                                 hsync-len = <60>;
 430                                 vsync-len = <10>;
 431                         };
 432                 };
 433         };
 434
 435         lvds-channel@1 {
 436                 fsl,data-mapping = "spwg";
 437                 fsl,data-width = <18>;
 438                 primary;
 439                 status = "okay";
 440
 441                 display-timings {
 442                         native-mode = <&timing1>;
 443                         timing1: hsd100pxn1 {
 444                                 clock-frequency = <65000000>;
 445                                 hactive = <1024>;
 446                                 vactive = <768>;
 447                                 hback-porch = <220>;
 448                                 hfront-porch = <40>;
 449                                 vback-porch = <21>;
 450                                 vfront-porch = <7>;
 451                                 hsync-len = <60>;
 452                                 vsync-len = <10>;
 453                         };
 454                 };
 455         };
 456 };
 457
 458 &pwm1 {
 459         pinctrl-names = "default";
 460         pinctrl-0 = <&pinctrl_pwm1>;
 461         status = "okay";
 462 };
 463
 464 &ssi2 {
 465         fsl,mode = "i2s-slave";
 466         status = "okay";
 467 };
 468
 469 &uart1 {
 470         pinctrl-names = "default";
 471         pinctrl-0 = <&pinctrl_uart1>;
 472         status = "okay";
 473 };
 474
 475 &usbh1 {
 476         vbus-supply = <&reg_usb_h1_vbus>;
 477         status = "okay";
 478 };
 479
 480 &usbotg {
 481         vbus-supply = <&reg_usb_otg_vbus>;
 482         pinctrl-names = "default";
 483         pinctrl-0 = <&pinctrl_usbotg>;
 484         disable-over-current;
 485         status = "okay";
 486 };
 487
 488 &usdhc2 {
 489         pinctrl-names = "default";
 490         pinctrl-0 = <&pinctrl_usdhc2>;
 491         bus-width = <8>;
 492         cd-gpios = <&gpio2 2 0>;
 493         wp-gpios = <&gpio2 3 0>;
 494         status = "okay";
 495 };
 496
 497 &usdhc3 {
 498         pinctrl-names = "default";
 499         pinctrl-0 = <&pinctrl_usdhc3>;
 500         bus-width = <8>;
 501         cd-gpios = <&gpio2 0 0>;
 502         wp-gpios = <&gpio2 1 0>;
 503         status = "okay";
 504 };