arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         aliases {
  17                 mxcfb0 = &mxcfb1;
  18                 mxcfb1 = &mxcfb2;
  19                 mxcfb2 = &mxcfb3;
  20                 mxcfb3 = &mxcfb4;
  21         };
  22
  23         battery: max8903@0 {
  24                 compatible = "fsl,max8903-charger";
  25                 pinctrl-names = "default";
  26                 dok_input = <&gpio2 24 1>;
  27                 uok_input = <&gpio1 27 1>;
  28                 chg_input = <&gpio3 23 1>;
  29                 flt_input = <&gpio5 2 1>;
  30                 fsl,dcm_always_high;
  31                 fsl,dc_valid;
  32                 fsl,usb_valid;
  33                 status = "okay";
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38
  39                 charger-led {
  40                         gpios = <&gpio1 2 0>;
  41                         linux,default-trigger = "max8903-charger-charging";
  42                         retain-state-suspended;
  43                 };
  44         };
  45
  46         memory {
  47                 reg = <0x10000000 0x40000000>;
  48         };
  49
  50         regulators {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 reg_usb_otg_vbus: regulator@0 {
  56                         compatible = "regulator-fixed";
  57                         reg = <0>;
  58                         regulator-name = "usb_otg_vbus";
  59                         regulator-min-microvolt = <5000000>;
  60                         regulator-max-microvolt = <5000000>;
  61                         gpio = <&gpio3 22 0>;
  62                         enable-active-high;
  63                 };
  64
  65                 reg_usb_h1_vbus: regulator@1 {
  66                         compatible = "regulator-fixed";
  67                         reg = <1>;
  68                         regulator-name = "usb_h1_vbus";
  69                         regulator-min-microvolt = <5000000>;
  70                         regulator-max-microvolt = <5000000>;
  71                         gpio = <&gpio1 29 0>;
  72                         enable-active-high;
  73                 };
  74
  75                 reg_audio: regulator@2 {
  76                         compatible = "regulator-fixed";
  77                         reg = <2>;
  78                         regulator-name = "wm8962-supply";
  79                         gpio = <&gpio4 10 0>;
  80                         enable-active-high;
  81                 };
  82
  83                 reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
  84                         compatible = "regulator-fixed";
  85                         regulator-name = "mipi_dsi_pwr_on";
  86                         gpio = <&gpio6 14 0>;
  87                         enable-active-high;
  88                 };
  89
  90                 reg_sensor: regulator@3 {
  91                         compatible = "regulator-fixed";
  92                         reg = <3>;
  93                         regulator-name = "sensor-supply";
  94                         regulator-min-microvolt = <3300000>;
  95                         regulator-max-microvolt = <3300000>;
  96                         gpio = <&gpio2 31 0>;
  97                         startup-delay-us = <500>;
  98                         enable-active-high;
  99                 };
 100         };
 101
 102         gpio-keys {
 103                 compatible = "gpio-keys";
 104                 pinctrl-names = "default";
 105                 pinctrl-0 = <&pinctrl_gpio_keys>;
 106
 107                 power {
 108                         label = "Power Button";
 109                         gpios = <&gpio3 29 1>;
 110                         gpio-key,wakeup;
 111                         linux,code = <KEY_POWER>;
 112                 };
 113
 114                 volume-up {
 115                         label = "Volume Up";
 116                         gpios = <&gpio1 4 1>;
 117                         gpio-key,wakeup;
 118                         linux,code = <KEY_VOLUMEUP>;
 119                 };
 120
 121                 volume-down {
 122                         label = "Volume Down";
 123                         gpios = <&gpio1 5 1>;
 124                         gpio-key,wakeup;
 125                         linux,code = <KEY_VOLUMEDOWN>;
 126                 };
 127         };
 128
 129         sound {
 130                 compatible = "fsl,imx6q-sabresd-wm8962",
 131                            "fsl,imx-audio-wm8962";
 132                 model = "wm8962-audio";
 133                 cpu-dai = <&ssi2>;
 134                 audio-codec = <&codec>;
 135                 audio-routing =
 136                         "Headphone Jack", "HPOUTL",
 137                         "Headphone Jack", "HPOUTR",
 138                         "Ext Spk", "SPKOUTL",
 139                         "Ext Spk", "SPKOUTR",
 140                         "MICBIAS", "AMIC",
 141                         "IN3R", "MICBIAS",
 142                         "DMIC", "MICBIAS",
 143                         "DMICDAT", "DMIC";
 144                 mux-int-port = <2>;
 145                 mux-ext-port = <3>;
 146                 hp-det-gpios = <&gpio7 8 1>;
 147                 mic-det-gpios = <&gpio1 9 1>;
 148         };
 149
 150         sound-hdmi {
 151                 compatible = "fsl,imx6q-audio-hdmi",
 152                              "fsl,imx-audio-hdmi";
 153                 model = "imx-audio-hdmi";
 154                 hdmi-controller = <&hdmi_audio>;
 155         };
 156
 157         mxcfb1: fb@0 {
 158                 compatible = "fsl,mxc_sdc_fb";
 159                 disp_dev = "ldb";
 160                 interface_pix_fmt = "RGB666";
 161                 default_bpp = <16>;
 162                 int_clk = <0>;
 163                 late_init = <0>;
 164                 status = "disabled";
 165         };
 166
 167         mxcfb2: fb@1 {
 168                 compatible = "fsl,mxc_sdc_fb";
 169                 disp_dev = "hdmi";
 170                 interface_pix_fmt = "RGB24";
 171                 mode_str ="1920x1080M@60";
 172                 default_bpp = <24>;
 173                 int_clk = <0>;
 174                 late_init = <0>;
 175                 status = "disabled";
 176         };
 177
 178         mxcfb3: fb@2 {
 179                 compatible = "fsl,mxc_sdc_fb";
 180                 disp_dev = "lcd";
 181                 interface_pix_fmt = "RGB565";
 182                 mode_str ="CLAA-WVGA";
 183                 default_bpp = <16>;
 184                 int_clk = <0>;
 185                 late_init = <0>;
 186                 status = "disabled";
 187         };
 188
 189         mxcfb4: fb@3 {
 190                 compatible = "fsl,mxc_sdc_fb";
 191                 disp_dev = "ldb";
 192                 interface_pix_fmt = "RGB666";
 193                 default_bpp = <16>;
 194                 int_clk = <0>;
 195                 late_init = <0>;
 196                 status = "disabled";
 197         };
 198
 199         lcd@0 {
 200                 compatible = "fsl,lcd";
 201                 ipu_id = <0>;
 202                 disp_id = <0>;
 203                 default_ifmt = "RGB565";
 204                 pinctrl-names = "default";
 205                 pinctrl-0 = <&pinctrl_ipu1>;
 206                 status = "okay";
 207         };
 208
 209         backlight {
 210                 compatible = "pwm-backlight";
 211                 pwms = <&pwm1 0 5000000>;
 212                 brightness-levels = <0 4 8 16 32 64 128 255>;
 213                 default-brightness-level = <7>;
 214                 status = "okay";
 215         };
 216
 217         v4l2_cap_0 {
 218                 compatible = "fsl,imx6q-v4l2-capture";
 219                 ipu_id = <0>;
 220                 csi_id = <0>;
 221                 mclk_source = <0>;
 222                 status = "okay";
 223         };
 224
 225         v4l2_cap_1 {
 226                 compatible = "fsl,imx6q-v4l2-capture";
 227                 ipu_id = <0>;
 228                 csi_id = <1>;
 229                 mclk_source = <0>;
 230                 status = "okay";
 231         };
 232
 233         v4l2_out {
 234                 compatible = "fsl,mxc_v4l2_output";
 235                 status = "okay";
 236         };
 237
 238         mipi_dsi_reset: mipi-dsi-reset {
 239                 compatible = "gpio-reset";
 240                 reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 241                 reset-delay-us = <50>;
 242                 #reset-cells = <0>;
 243         };
 244 };
 245
 246 &audmux {
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_audmux>;
 249         status = "okay";
 250 };
 251
 252 &cpu0 {
 253         arm-supply = <&sw1a_reg>;
 254         soc-supply = <&sw1c_reg>;
 255 };
 256
 257 &ecspi1 {
 258         fsl,spi-num-chipselects = <1>;
 259         cs-gpios = <&gpio4 9 0>;
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&pinctrl_ecspi1>;
 262         status = "okay";
 263
 264         flash: m25p80@0 {
 265                 #address-cells = <1>;
 266                 #size-cells = <1>;
 267                 compatible = "st,m25p32";
 268                 spi-max-frequency = <20000000>;
 269                 reg = <0>;
 270         };
 271 };
 272
 273 &fec {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_enet>;
 276         phy-mode = "rgmii";
 277         phy-reset-gpios = <&gpio1 25 0>;
 278         status = "okay";
 279 };
 280
 281 &i2c1 {
 282         clock-frequency = <100000>;
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_i2c1>;
 285         status = "okay";
 286
 287         codec: wm8962@1a {
 288                 compatible = "wlf,wm8962";
 289                 reg = <0x1a>;
 290                 clocks = <&clks 201>;
 291                 DCVDD-supply = <&reg_audio>;
 292                 DBVDD-supply = <&reg_audio>;
 293                 AVDD-supply = <&reg_audio>;
 294                 CPVDD-supply = <&reg_audio>;
 295                 MICVDD-supply = <&reg_audio>;
 296                 PLLVDD-supply = <&reg_audio>;
 297                 SPKVDD1-supply = <&reg_audio>;
 298                 SPKVDD2-supply = <&reg_audio>;
 299                 amic-mono;
 300                 gpio-cfg = <
 301                         0x0000 /* 0:Default */
 302                         0x0000 /* 1:Default */
 303                         0x0013 /* 2:FN_DMICCLK */
 304                         0x0000 /* 3:Default */
 305                         0x8014 /* 4:FN_DMICCDAT */
 306                         0x0000 /* 5:Default */
 307                 >;
 308        };
 309
 310         mma8451@1c {
 311                 compatible = "fsl,mma8451";
 312                 reg = <0x1c>;
 313                 position = <0>;
 314                 vdd-supply = <&reg_sensor>;
 315                 vddio-supply = <&reg_sensor>;
 316                 interrupt-parent = <&gpio1>;
 317                 interrupts = <18 8>;
 318                 interrupt-route = <1>;
 319         };
 320
 321         ov564x: ov564x@3c {
 322                 compatible = "ovti,ov564x";
 323                 reg = <0x3c>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&pinctrl_ipu1_2>;
 326                 clocks = <&clks IMX6QDL_CLK_CKO>;
 327                 clock-names = "csi_mclk";
 328                 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
 329                 AVDD-supply = <&vgen3_reg>;  /* 2.8v, on rev C board is VGEN3,
 330                                                 on rev B board is VGEN5 */
 331                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 332                 pwn-gpios = <&gpio1 16 1>;   /* active low: SD1_DAT0 */
 333                 rst-gpios = <&gpio1 17 0>;   /* active high: SD1_DAT1 */
 334                 csi_id = <0>;
 335                 mclk = <24000000>;
 336                 mclk_source = <0>;
 337         };
 338 };
 339
 340 &i2c2 {
 341         clock-frequency = <100000>;
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pinctrl_i2c2>;
 344         status = "okay";
 345
 346         hdmi: edid@50 {
 347                 compatible = "fsl,imx6-hdmi-i2c";
 348                 reg = <0x50>;
 349         };
 350
 351         max11801@48 {
 352                 compatible = "maxim,max11801";
 353                 reg = <0x48>;
 354                 interrupt-parent = <&gpio3>;
 355                 interrupts = <26 2>;
 356                 work-mode = <1>;/*DCM mode*/
 357         };
 358
 359         pmic: pfuze100@08 {
 360                 compatible = "fsl,pfuze100";
 361                 reg = <0x08>;
 362
 363                 regulators {
 364                         sw1a_reg: sw1ab {
 365                                 regulator-min-microvolt = <300000>;
 366                                 regulator-max-microvolt = <1875000>;
 367                                 regulator-boot-on;
 368                                 regulator-always-on;
 369                                 regulator-ramp-delay = <6250>;
 370                         };
 371
 372                         sw1c_reg: sw1c {
 373                                 regulator-min-microvolt = <300000>;
 374                                 regulator-max-microvolt = <1875000>;
 375                                 regulator-boot-on;
 376                                 regulator-always-on;
 377                                 regulator-ramp-delay = <6250>;
 378                         };
 379
 380                         sw2_reg: sw2 {
 381                                 regulator-min-microvolt = <800000>;
 382                                 regulator-max-microvolt = <3300000>;
 383                                 regulator-boot-on;
 384                                 regulator-always-on;
 385                         };
 386
 387                         sw3a_reg: sw3a {
 388                                 regulator-min-microvolt = <400000>;
 389                                 regulator-max-microvolt = <1975000>;
 390                                 regulator-boot-on;
 391                                 regulator-always-on;
 392                         };
 393
 394                         sw3b_reg: sw3b {
 395                                 regulator-min-microvolt = <400000>;
 396                                 regulator-max-microvolt = <1975000>;
 397                                 regulator-boot-on;
 398                                 regulator-always-on;
 399                         };
 400
 401                         sw4_reg: sw4 {
 402                                 regulator-min-microvolt = <800000>;
 403                                 regulator-max-microvolt = <3300000>;
 404                         };
 405
 406                         swbst_reg: swbst {
 407                                 regulator-min-microvolt = <5000000>;
 408                                 regulator-max-microvolt = <5150000>;
 409                         };
 410
 411                         snvs_reg: vsnvs {
 412                                 regulator-min-microvolt = <1000000>;
 413                                 regulator-max-microvolt = <3000000>;
 414                                 regulator-boot-on;
 415                                 regulator-always-on;
 416                         };
 417
 418                         vref_reg: vrefddr {
 419                                 regulator-boot-on;
 420                                 regulator-always-on;
 421                         };
 422
 423                         vgen1_reg: vgen1 {
 424                                 regulator-min-microvolt = <800000>;
 425                                 regulator-max-microvolt = <1550000>;
 426                         };
 427
 428                         vgen2_reg: vgen2 {
 429                                 regulator-min-microvolt = <800000>;
 430                                 regulator-max-microvolt = <1550000>;
 431                         };
 432
 433                         vgen3_reg: vgen3 {
 434                                 regulator-min-microvolt = <1800000>;
 435                                 regulator-max-microvolt = <3300000>;
 436                         };
 437
 438                         vgen4_reg: vgen4 {
 439                                 regulator-min-microvolt = <1800000>;
 440                                 regulator-max-microvolt = <3300000>;
 441                                 regulator-always-on;
 442                         };
 443
 444                         vgen5_reg: vgen5 {
 445                                 regulator-min-microvolt = <1800000>;
 446                                 regulator-max-microvolt = <3300000>;
 447                                 regulator-always-on;
 448                         };
 449
 450                         vgen6_reg: vgen6 {
 451                                 regulator-min-microvolt = <1800000>;
 452                                 regulator-max-microvolt = <3300000>;
 453                                 regulator-always-on;
 454                         };
 455                 };
 456         };
 457
 458         ov5640_mipi: ov5640_mipi@3c { /* i2c2 driver */
 459                 compatible = "ovti,ov5640_mipi";
 460                 reg = <0x3c>;
 461                 clocks = <&clks 201>;
 462                 clock-names = "csi_mclk";
 463                 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
 464                 AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
 465                                                 rev B board is VGEN5 */
 466                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 467                 pwn-gpios = <&gpio1 19 1>;   /* active low: SD1_CLK */
 468                 rst-gpios = <&gpio1 20 0>;   /* active high: SD1_DAT2 */
 469                 csi_id = <1>;
 470                 mclk = <24000000>;
 471                 mclk_source = <0>;
 472         };
 473 };
 474
 475 &i2c3 {
 476         clock-frequency = <100000>;
 477         pinctrl-names = "default";
 478         pinctrl-0 = <&pinctrl_i2c3>;
 479         status = "okay";
 480
 481         egalax_ts@04 {
 482                 compatible = "eeti,egalax_ts";
 483                 reg = <0x04>;
 484                 interrupt-parent = <&gpio6>;
 485                 interrupts = <7 2>;
 486                 wakeup-gpios = <&gpio6 7 0>;
 487         };
 488
 489         mag3110@0e {
 490                 compatible = "fsl,mag3110";
 491                 reg = <0x0e>;
 492                 position = <2>;
 493                 vdd-supply = <&reg_sensor>;
 494                 vddio-supply = <&reg_sensor>;
 495                 interrupt-parent = <&gpio3>;
 496                 interrupts = <16 1>;
 497         };
 498
 499         isl29023@44 {
 500                 compatible = "fsl,isl29023";
 501                 reg = <0x44>;
 502                 rext = <499>;
 503                 vdd-supply = <&reg_sensor>;
 504                 interrupt-parent = <&gpio3>;
 505                 interrupts = <9 2>;
 506         };
 507 };
 508
 509 &iomuxc {
 510         pinctrl-names = "default";
 511         pinctrl-0 = <&pinctrl_hog>;
 512
 513         imx6qdl-sabresd {
 514                 pinctrl_hog: hoggrp {
 515                         fsl,pins = <
 516                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
 517                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
 518                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
 519                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
 520                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 521                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
 522                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 523                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
 524                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
 525                                 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
 526                                 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
 527                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 528                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
 529                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
 530                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
 531                                 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
 532                                 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
 533                                 MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x80000000
 534                                 MX6QDL_PAD_GPIO_9__GPIO1_IO09   0x80000000
 535                                 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
 536                                 MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
 537                                 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
 538                                 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
 539                         >;
 540                 };
 541
 542                 pinctrl_audmux: audmuxgrp {
 543                         fsl,pins = <
 544                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 545                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 546                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 547                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 548                         >;
 549                 };
 550
 551                 pinctrl_ecspi1: ecspi1grp {
 552                         fsl,pins = <
 553                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 554                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 555                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 556                         >;
 557                 };
 558
 559                 pinctrl_enet: enetgrp {
 560                         fsl,pins = <
 561                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 562                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 563                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 564                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 565                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 566                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 567                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 568                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 569                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 570                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 571                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 572                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 573                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 574                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 575                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 576                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 577                         >;
 578                 };
 579
 580                 pinctrl_enet_irq: enetirqgrp {
 581                         fsl,pins = <
 582                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 583                         >;
 584                 };
 585
 586                 pinctrl_gpio_keys: gpio_keysgrp {
 587                         fsl,pins = <
 588                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
 589                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x80000000
 590                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x80000000
 591                         >;
 592                 };
 593
 594                 pinctrl_hdmi_cec: hdmicecgrp {
 595                         fsl,pins = <
 596                                 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 597                         >;
 598                 };
 599
 600                 pinctrl_hdmi_hdcp: hdmihdcpgrp {
 601                         fsl,pins = <
 602                                 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 603                                 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 604                         >;
 605                 };
 606
 607                 pinctrl_i2c1: i2c1grp {
 608                         fsl,pins = <
 609                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 610                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 611                         >;
 612                 };
 613
 614                 pinctrl_i2c2: i2c2grp {
 615                         fsl,pins = <
 616                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 617                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 618                          >;
 619                 };
 620
 621                 pinctrl_i2c3: i2c3grp {
 622                         fsl,pins = <
 623                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 624                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 625                         >;
 626                 };
 627
 628                 pinctrl_ipu1: ipu1grp {
 629                         fsl,pins = <
 630                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
 631                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
 632                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
 633                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
 634                                 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
 635                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
 636                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
 637                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
 638                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 639                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 640                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 641                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 642                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 643                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 644                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 645                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 646                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 647                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 648                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 649                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 650                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 651                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 652                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 653                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
 654                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
 655                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
 656                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
 657                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
 658                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
 659                         >;
 660                 };
 661
 662                 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
 663                         fsl,pins = <
 664                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
 665                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
 666                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
 667                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
 668                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
 669                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
 670                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
 671                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
 672                                 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
 673                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
 674                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
 675                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
 676                         >;
 677                 };
 678
 679                 pinctrl_pwm1: pwm1grp {
 680                         fsl,pins = <
 681                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 682                         >;
 683                 };
 684
 685                 pinctrl_uart1: uart1grp {
 686                         fsl,pins = <
 687                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 688                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 689                         >;
 690                 };
 691
 692                 pinctrl_uart5_1: uart5grp-1 {
 693                         fsl,pins = <
 694                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 695                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 696                                 MX6QDL_PAD_KEY_COL4__UART5_RTS_B        0x1b0b1
 697                                 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B        0x1b0b1
 698                         >;
 699                 };
 700
 701                 pinctrl_uart5dte_1: uart5dtegrp-1 {
 702                         fsl,pins = <
 703                                 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA      0x1b0b1
 704                                 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA      0x1b0b1
 705                                 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B        0x1b0b1
 706                                 MX6QDL_PAD_KEY_COL4__UART5_CTS_B        0x1b0b1
 707                         >;
 708                 };
 709
 710                 pinctrl_usbotg: usbotggrp {
 711                         fsl,pins = <
 712                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 713                         >;
 714                 };
 715
 716                 pinctrl_usdhc2: usdhc2grp {
 717                         fsl,pins = <
 718                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 719                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 720                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 721                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 722                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 723                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 724                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 725                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 726                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 727                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 728                         >;
 729                 };
 730
 731                 pinctrl_usdhc3: usdhc3grp {
 732                         fsl,pins = <
 733                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 734                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 735                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 736                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 737                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 738                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 739                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 740                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 741                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 742                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 743                         >;
 744                 };
 745
 746                 pinctrl_usdhc4: usdhc4grp {
 747                         fsl,pins = <
 748                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 749                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 750                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 751                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 752                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 753                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 754                                 MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 755                                 MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 756                                 MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 757                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 758                         >;
 759                 };
 760
 761         };
 762 };
 763
 764 &dcic1 {
 765         dcic_id = <0>;
 766         dcic_mux = "dcic-hdmi";
 767         status = "okay";
 768 };
 769
 770 &dcic2 {
 771         dcic_id = <1>;
 772         dcic_mux = "dcic-lvds1";
 773         status = "okay";
 774 };
 775
 776 &gpc {
 777         /* use ldo-bypass, u-boot will check it and configure */
 778         fsl,ldo-bypass = <1>;
 779         fsl,wdog-reset = <2>;
 780 };
 781
 782 &hdmi_audio {
 783         status = "okay";
 784 };
 785
 786 &hdmi_cec {
 787         pinctrl-names = "default";
 788         pinctrl-0 = <&pinctrl_hdmi_cec>;
 789         status = "okay";
 790 };
 791
 792 &hdmi_core {
 793         ipu_id = <0>;
 794         disp_id = <0>;
 795         status = "okay";
 796 };
 797
 798 &hdmi_video {
 799         fsl,phy_reg_vlev = <0x0294>;
 800         fsl,phy_reg_cksymtx = <0x800d>;
 801         status = "okay";
 802 };
 803
 804 &ldb {
 805         status = "okay";
 806
 807         lvds-channel@0 {
 808                 fsl,data-mapping = "spwg";
 809                 fsl,data-width = <18>;
 810                 status = "okay";
 811
 812                 display-timings {
 813                         native-mode = <&timing0>;
 814                         timing0: hsd100pxn1 {
 815                                 clock-frequency = <65000000>;
 816                                 hactive = <1024>;
 817                                 vactive = <768>;
 818                                 hback-porch = <220>;
 819                                 hfront-porch = <40>;
 820                                 vback-porch = <21>;
 821                                 vfront-porch = <7>;
 822                                 hsync-len = <60>;
 823                                 vsync-len = <10>;
 824                         };
 825                 };
 826         };
 827
 828         lvds-channel@1 {
 829                 fsl,data-mapping = "spwg";
 830                 fsl,data-width = <18>;
 831                 primary;
 832                 status = "okay";
 833
 834                 display-timings {
 835                         native-mode = <&timing1>;
 836                         timing1: hsd100pxn1 {
 837                                 clock-frequency = <65000000>;
 838                                 hactive = <1024>;
 839                                 vactive = <768>;
 840                                 hback-porch = <220>;
 841                                 hfront-porch = <40>;
 842                                 vback-porch = <21>;
 843                                 vfront-porch = <7>;
 844                                 hsync-len = <60>;
 845                                 vsync-len = <10>;
 846                         };
 847                 };
 848         };
 849 };
 850
 851 &mipi_csi {
 852         status = "okay";
 853         ipu_id = <0>;
 854         csi_id = <1>;
 855         v_channel = <0>;
 856         lanes = <2>;
 857 };
 858
 859 &mipi_dsi {
 860         dev_id = <0>;
 861         disp_id = <1>;
 862         lcd_panel = "TRULY-WVGA";
 863         disp-power-on-supply = <&reg_mipi_dsi_pwr_on>;
 864         resets = <&mipi_dsi_reset>;
 865         status = "okay";
 866 };
 867
 868 &pwm1 {
 869         pinctrl-names = "default";
 870         pinctrl-0 = <&pinctrl_pwm1>;
 871         status = "okay";
 872 };
 873
 874 &ssi2 {
 875         fsl,mode = "i2s-slave";
 876         status = "okay";
 877 };
 878
 879 &uart1 {
 880         pinctrl-names = "default";
 881         pinctrl-0 = <&pinctrl_uart1>;
 882         status = "okay";
 883 };
 884
 885 &usbh1 {
 886         vbus-supply = <&reg_usb_h1_vbus>;
 887         status = "okay";
 888 };
 889
 890 &usbotg {
 891         vbus-supply = <&reg_usb_otg_vbus>;
 892         pinctrl-names = "default";
 893         pinctrl-0 = <&pinctrl_usbotg>;
 894         disable-over-current;
 895         status = "okay";
 896 };
 897
 898 &usdhc2 {
 899         pinctrl-names = "default";
 900         pinctrl-0 = <&pinctrl_usdhc2>;
 901         bus-width = <8>;
 902         cd-gpios = <&gpio2 2 0>;
 903         wp-gpios = <&gpio2 3 0>;
 904         no-1-8-v;
 905         keep-power-in-suspend;
 906         enable-sdio-wakeup;
 907         status = "okay";
 908 };
 909
 910 &usdhc3 {
 911         pinctrl-names = "default";
 912         pinctrl-0 = <&pinctrl_usdhc3>;
 913         bus-width = <8>;
 914         cd-gpios = <&gpio2 0 0>;
 915         wp-gpios = <&gpio2 1 0>;
 916         no-1-8-v;
 917         keep-power-in-suspend;
 918         enable-sdio-wakeup;
 919         status = "okay";
 920 };
 921
 922 &usdhc4 {
 923         pinctrl-names = "default";
 924         pinctrl-0 = <&pinctrl_usdhc4>;
 925         bus-width = <8>;
 926         non-removable;
 927         no-1-8-v;
 928         keep-power-in-suspend;
 929         status = "okay";
 930 };
 931
 932 &wdog1 {
 933         status = "disabled";
 934 };
 935
 936 &wdog2 {
 937         status = "okay";
 938 };