arch/arm/boot/dts/imx6qdl.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29         };
  30
  31         intc: interrupt-controller@00a01000 {
  32                 compatible = "arm,cortex-a9-gic";
  33                 #interrupt-cells = <3>;
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 interrupt-controller;
  37                 reg = <0x00a01000 0x1000>,
  38                       <0x00a00100 0x100>;
  39         };
  40
  41         clocks {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 ckil {
  46                         compatible = "fsl,imx-ckil", "fixed-clock";
  47                         clock-frequency = <32768>;
  48                 };
  49
  50                 ckih1 {
  51                         compatible = "fsl,imx-ckih1", "fixed-clock";
  52                         clock-frequency = <0>;
  53                 };
  54
  55                 osc {
  56                         compatible = "fsl,imx-osc", "fixed-clock";
  57                         clock-frequency = <24000000>;
  58                 };
  59         };
  60
  61         soc {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 compatible = "simple-bus";
  65                 interrupt-parent = <&intc>;
  66                 ranges;
  67
  68                 dma-apbh@00110000 {
  69                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
  70                         reg = <0x00110000 0x2000>;
  71                         clocks = <&clks 106>;
  72                 };
  73
  74                 gpmi: gpmi-nand@00112000 {
  75                         compatible = "fsl,imx6q-gpmi-nand";
  76                         #address-cells = <1>;
  77                         #size-cells = <1>;
  78                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
  79                         reg-names = "gpmi-nand", "bch";
  80                         interrupts = <0 13 0x04>, <0 15 0x04>;
  81                         interrupt-names = "gpmi-dma", "bch";
  82                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
  83                                  <&clks 150>, <&clks 149>;
  84                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
  85                                       "gpmi_bch_apb", "per1_bch";
  86                         fsl,gpmi-dma-channel = <0>;
  87                         status = "disabled";
  88                 };
  89
  90                 timer@00a00600 {
  91                         compatible = "arm,cortex-a9-twd-timer";
  92                         reg = <0x00a00600 0x20>;
  93                         interrupts = <1 13 0xf01>;
  94                         clocks = <&clks 15>;
  95                 };
  96
  97                 L2: l2-cache@00a02000 {
  98                         compatible = "arm,pl310-cache";
  99                         reg = <0x00a02000 0x1000>;
 100                         interrupts = <0 92 0x04>;
 101                         cache-unified;
 102                         cache-level = <2>;
 103                 };
 104
 105                 aips-bus@02000000 { /* AIPS1 */
 106                         compatible = "fsl,aips-bus", "simple-bus";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109                         reg = <0x02000000 0x100000>;
 110                         ranges;
 111
 112                         spba-bus@02000000 {
 113                                 compatible = "fsl,spba-bus", "simple-bus";
 114                                 #address-cells = <1>;
 115                                 #size-cells = <1>;
 116                                 reg = <0x02000000 0x40000>;
 117                                 ranges;
 118
 119                                 spdif: spdif@02004000 {
 120                                         reg = <0x02004000 0x4000>;
 121                                         interrupts = <0 52 0x04>;
 122                                 };
 123
 124                                 ecspi1: ecspi@02008000 {
 125                                         #address-cells = <1>;
 126                                         #size-cells = <0>;
 127                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 128                                         reg = <0x02008000 0x4000>;
 129                                         interrupts = <0 31 0x04>;
 130                                         clocks = <&clks 112>, <&clks 112>;
 131                                         clock-names = "ipg", "per";
 132                                         status = "disabled";
 133                                 };
 134
 135                                 ecspi2: ecspi@0200c000 {
 136                                         #address-cells = <1>;
 137                                         #size-cells = <0>;
 138                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 139                                         reg = <0x0200c000 0x4000>;
 140                                         interrupts = <0 32 0x04>;
 141                                         clocks = <&clks 113>, <&clks 113>;
 142                                         clock-names = "ipg", "per";
 143                                         status = "disabled";
 144                                 };
 145
 146                                 ecspi3: ecspi@02010000 {
 147                                         #address-cells = <1>;
 148                                         #size-cells = <0>;
 149                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 150                                         reg = <0x02010000 0x4000>;
 151                                         interrupts = <0 33 0x04>;
 152                                         clocks = <&clks 114>, <&clks 114>;
 153                                         clock-names = "ipg", "per";
 154                                         status = "disabled";
 155                                 };
 156
 157                                 ecspi4: ecspi@02014000 {
 158                                         #address-cells = <1>;
 159                                         #size-cells = <0>;
 160                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 161                                         reg = <0x02014000 0x4000>;
 162                                         interrupts = <0 34 0x04>;
 163                                         clocks = <&clks 115>, <&clks 115>;
 164                                         clock-names = "ipg", "per";
 165                                         status = "disabled";
 166                                 };
 167
 168                                 uart1: serial@02020000 {
 169                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 170                                         reg = <0x02020000 0x4000>;
 171                                         interrupts = <0 26 0x04>;
 172                                         clocks = <&clks 160>, <&clks 161>;
 173                                         clock-names = "ipg", "per";
 174                                         status = "disabled";
 175                                 };
 176
 177                                 esai: esai@02024000 {
 178                                         reg = <0x02024000 0x4000>;
 179                                         interrupts = <0 51 0x04>;
 180                                 };
 181
 182                                 ssi1: ssi@02028000 {
 183                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 184                                         reg = <0x02028000 0x4000>;
 185                                         interrupts = <0 46 0x04>;
 186                                         clocks = <&clks 178>;
 187                                         fsl,fifo-depth = <15>;
 188                                         fsl,ssi-dma-events = <38 37>;
 189                                         status = "disabled";
 190                                 };
 191
 192                                 ssi2: ssi@0202c000 {
 193                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 194                                         reg = <0x0202c000 0x4000>;
 195                                         interrupts = <0 47 0x04>;
 196                                         clocks = <&clks 179>;
 197                                         fsl,fifo-depth = <15>;
 198                                         fsl,ssi-dma-events = <42 41>;
 199                                         status = "disabled";
 200                                 };
 201
 202                                 ssi3: ssi@02030000 {
 203                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
 204                                         reg = <0x02030000 0x4000>;
 205                                         interrupts = <0 48 0x04>;
 206                                         clocks = <&clks 180>;
 207                                         fsl,fifo-depth = <15>;
 208                                         fsl,ssi-dma-events = <46 45>;
 209                                         status = "disabled";
 210                                 };
 211
 212                                 asrc: asrc@02034000 {
 213                                         reg = <0x02034000 0x4000>;
 214                                         interrupts = <0 50 0x04>;
 215                                 };
 216
 217                                 spba@0203c000 {
 218                                         reg = <0x0203c000 0x4000>;
 219                                 };
 220                         };
 221
 222                         vpu: vpu@02040000 {
 223                                 reg = <0x02040000 0x3c000>;
 224                                 interrupts = <0 3 0x04 0 12 0x04>;
 225                         };
 226
 227                         aipstz@0207c000 { /* AIPSTZ1 */
 228                                 reg = <0x0207c000 0x4000>;
 229                         };
 230
 231                         pwm1: pwm@02080000 {
 232                                 #pwm-cells = <2>;
 233                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 234                                 reg = <0x02080000 0x4000>;
 235                                 interrupts = <0 83 0x04>;
 236                                 clocks = <&clks 62>, <&clks 145>;
 237                                 clock-names = "ipg", "per";
 238                         };
 239
 240                         pwm2: pwm@02084000 {
 241                                 #pwm-cells = <2>;
 242                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 243                                 reg = <0x02084000 0x4000>;
 244                                 interrupts = <0 84 0x04>;
 245                                 clocks = <&clks 62>, <&clks 146>;
 246                                 clock-names = "ipg", "per";
 247                         };
 248
 249                         pwm3: pwm@02088000 {
 250                                 #pwm-cells = <2>;
 251                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 252                                 reg = <0x02088000 0x4000>;
 253                                 interrupts = <0 85 0x04>;
 254                                 clocks = <&clks 62>, <&clks 147>;
 255                                 clock-names = "ipg", "per";
 256                         };
 257
 258                         pwm4: pwm@0208c000 {
 259                                 #pwm-cells = <2>;
 260                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 261                                 reg = <0x0208c000 0x4000>;
 262                                 interrupts = <0 86 0x04>;
 263                                 clocks = <&clks 62>, <&clks 148>;
 264                                 clock-names = "ipg", "per";
 265                         };
 266
 267                         can1: flexcan@02090000 {
 268                                 reg = <0x02090000 0x4000>;
 269                                 interrupts = <0 110 0x04>;
 270                         };
 271
 272                         can2: flexcan@02094000 {
 273                                 reg = <0x02094000 0x4000>;
 274                                 interrupts = <0 111 0x04>;
 275                         };
 276
 277                         gpt: gpt@02098000 {
 278                                 compatible = "fsl,imx6q-gpt";
 279                                 reg = <0x02098000 0x4000>;
 280                                 interrupts = <0 55 0x04>;
 281                         };
 282
 283                         gpio1: gpio@0209c000 {
 284                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 285                                 reg = <0x0209c000 0x4000>;
 286                                 interrupts = <0 66 0x04 0 67 0x04>;
 287                                 gpio-controller;
 288                                 #gpio-cells = <2>;
 289                                 interrupt-controller;
 290                                 #interrupt-cells = <2>;
 291                         };
 292
 293                         gpio2: gpio@020a0000 {
 294                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 295                                 reg = <0x020a0000 0x4000>;
 296                                 interrupts = <0 68 0x04 0 69 0x04>;
 297                                 gpio-controller;
 298                                 #gpio-cells = <2>;
 299                                 interrupt-controller;
 300                                 #interrupt-cells = <2>;
 301                         };
 302
 303                         gpio3: gpio@020a4000 {
 304                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 305                                 reg = <0x020a4000 0x4000>;
 306                                 interrupts = <0 70 0x04 0 71 0x04>;
 307                                 gpio-controller;
 308                                 #gpio-cells = <2>;
 309                                 interrupt-controller;
 310                                 #interrupt-cells = <2>;
 311                         };
 312
 313                         gpio4: gpio@020a8000 {
 314                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 315                                 reg = <0x020a8000 0x4000>;
 316                                 interrupts = <0 72 0x04 0 73 0x04>;
 317                                 gpio-controller;
 318                                 #gpio-cells = <2>;
 319                                 interrupt-controller;
 320                                 #interrupt-cells = <2>;
 321                         };
 322
 323                         gpio5: gpio@020ac000 {
 324                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 325                                 reg = <0x020ac000 0x4000>;
 326                                 interrupts = <0 74 0x04 0 75 0x04>;
 327                                 gpio-controller;
 328                                 #gpio-cells = <2>;
 329                                 interrupt-controller;
 330                                 #interrupt-cells = <2>;
 331                         };
 332
 333                         gpio6: gpio@020b0000 {
 334                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 335                                 reg = <0x020b0000 0x4000>;
 336                                 interrupts = <0 76 0x04 0 77 0x04>;
 337                                 gpio-controller;
 338                                 #gpio-cells = <2>;
 339                                 interrupt-controller;
 340                                 #interrupt-cells = <2>;
 341                         };
 342
 343                         gpio7: gpio@020b4000 {
 344                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 345                                 reg = <0x020b4000 0x4000>;
 346                                 interrupts = <0 78 0x04 0 79 0x04>;
 347                                 gpio-controller;
 348                                 #gpio-cells = <2>;
 349                                 interrupt-controller;
 350                                 #interrupt-cells = <2>;
 351                         };
 352
 353                         kpp: kpp@020b8000 {
 354                                 reg = <0x020b8000 0x4000>;
 355                                 interrupts = <0 82 0x04>;
 356                         };
 357
 358                         wdog1: wdog@020bc000 {
 359                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 360                                 reg = <0x020bc000 0x4000>;
 361                                 interrupts = <0 80 0x04>;
 362                                 clocks = <&clks 0>;
 363                         };
 364
 365                         wdog2: wdog@020c0000 {
 366                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 367                                 reg = <0x020c0000 0x4000>;
 368                                 interrupts = <0 81 0x04>;
 369                                 clocks = <&clks 0>;
 370                                 status = "disabled";
 371                         };
 372
 373                         clks: ccm@020c4000 {
 374                                 compatible = "fsl,imx6q-ccm";
 375                                 reg = <0x020c4000 0x4000>;
 376                                 interrupts = <0 87 0x04 0 88 0x04>;
 377                                 #clock-cells = <1>;
 378                         };
 379
 380                         anatop: anatop@020c8000 {
 381                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 382                                 reg = <0x020c8000 0x1000>;
 383                                 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 384
 385                                 regulator-1p1@110 {
 386                                         compatible = "fsl,anatop-regulator";
 387                                         regulator-name = "vdd1p1";
 388                                         regulator-min-microvolt = <800000>;
 389                                         regulator-max-microvolt = <1375000>;
 390                                         regulator-always-on;
 391                                         anatop-reg-offset = <0x110>;
 392                                         anatop-vol-bit-shift = <8>;
 393                                         anatop-vol-bit-width = <5>;
 394                                         anatop-min-bit-val = <4>;
 395                                         anatop-min-voltage = <800000>;
 396                                         anatop-max-voltage = <1375000>;
 397                                 };
 398
 399                                 regulator-3p0@120 {
 400                                         compatible = "fsl,anatop-regulator";
 401                                         regulator-name = "vdd3p0";
 402                                         regulator-min-microvolt = <2800000>;
 403                                         regulator-max-microvolt = <3150000>;
 404                                         regulator-always-on;
 405                                         anatop-reg-offset = <0x120>;
 406                                         anatop-vol-bit-shift = <8>;
 407                                         anatop-vol-bit-width = <5>;
 408                                         anatop-min-bit-val = <0>;
 409                                         anatop-min-voltage = <2625000>;
 410                                         anatop-max-voltage = <3400000>;
 411                                 };
 412
 413                                 regulator-2p5@130 {
 414                                         compatible = "fsl,anatop-regulator";
 415                                         regulator-name = "vdd2p5";
 416                                         regulator-min-microvolt = <2000000>;
 417                                         regulator-max-microvolt = <2750000>;
 418                                         regulator-always-on;
 419                                         anatop-reg-offset = <0x130>;
 420                                         anatop-vol-bit-shift = <8>;
 421                                         anatop-vol-bit-width = <5>;
 422                                         anatop-min-bit-val = <0>;
 423                                         anatop-min-voltage = <2000000>;
 424                                         anatop-max-voltage = <2750000>;
 425                                 };
 426
 427                                 reg_arm: regulator-vddcore@140 {
 428                                         compatible = "fsl,anatop-regulator";
 429                                         regulator-name = "cpu";
 430                                         regulator-min-microvolt = <725000>;
 431                                         regulator-max-microvolt = <1450000>;
 432                                         regulator-always-on;
 433                                         anatop-reg-offset = <0x140>;
 434                                         anatop-vol-bit-shift = <0>;
 435                                         anatop-vol-bit-width = <5>;
 436                                         anatop-delay-reg-offset = <0x170>;
 437                                         anatop-delay-bit-shift = <24>;
 438                                         anatop-delay-bit-width = <2>;
 439                                         anatop-min-bit-val = <1>;
 440                                         anatop-min-voltage = <725000>;
 441                                         anatop-max-voltage = <1450000>;
 442                                 };
 443
 444                                 reg_pu: regulator-vddpu@140 {
 445                                         compatible = "fsl,anatop-regulator";
 446                                         regulator-name = "vddpu";
 447                                         regulator-min-microvolt = <725000>;
 448                                         regulator-max-microvolt = <1450000>;
 449                                         regulator-always-on;
 450                                         anatop-reg-offset = <0x140>;
 451                                         anatop-vol-bit-shift = <9>;
 452                                         anatop-vol-bit-width = <5>;
 453                                         anatop-delay-reg-offset = <0x170>;
 454                                         anatop-delay-bit-shift = <26>;
 455                                         anatop-delay-bit-width = <2>;
 456                                         anatop-min-bit-val = <1>;
 457                                         anatop-min-voltage = <725000>;
 458                                         anatop-max-voltage = <1450000>;
 459                                 };
 460
 461                                 reg_soc: regulator-vddsoc@140 {
 462                                         compatible = "fsl,anatop-regulator";
 463                                         regulator-name = "vddsoc";
 464                                         regulator-min-microvolt = <725000>;
 465                                         regulator-max-microvolt = <1450000>;
 466                                         regulator-always-on;
 467                                         anatop-reg-offset = <0x140>;
 468                                         anatop-vol-bit-shift = <18>;
 469                                         anatop-vol-bit-width = <5>;
 470                                         anatop-delay-reg-offset = <0x170>;
 471                                         anatop-delay-bit-shift = <28>;
 472                                         anatop-delay-bit-width = <2>;
 473                                         anatop-min-bit-val = <1>;
 474                                         anatop-min-voltage = <725000>;
 475                                         anatop-max-voltage = <1450000>;
 476                                 };
 477                         };
 478
 479                         usbphy1: usbphy@020c9000 {
 480                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 481                                 reg = <0x020c9000 0x1000>;
 482                                 interrupts = <0 44 0x04>;
 483                                 clocks = <&clks 182>;
 484                         };
 485
 486                         usbphy2: usbphy@020ca000 {
 487                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 488                                 reg = <0x020ca000 0x1000>;
 489                                 interrupts = <0 45 0x04>;
 490                                 clocks = <&clks 183>;
 491                         };
 492
 493                         snvs@020cc000 {
 494                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 495                                 #address-cells = <1>;
 496                                 #size-cells = <1>;
 497                                 ranges = <0 0x020cc000 0x4000>;
 498
 499                                 snvs-rtc-lp@34 {
 500                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 501                                         reg = <0x34 0x58>;
 502                                         interrupts = <0 19 0x04 0 20 0x04>;
 503                                 };
 504                         };
 505
 506                         epit1: epit@020d0000 { /* EPIT1 */
 507                                 reg = <0x020d0000 0x4000>;
 508                                 interrupts = <0 56 0x04>;
 509                         };
 510
 511                         epit2: epit@020d4000 { /* EPIT2 */
 512                                 reg = <0x020d4000 0x4000>;
 513                                 interrupts = <0 57 0x04>;
 514                         };
 515
 516                         src: src@020d8000 {
 517                                 compatible = "fsl,imx6q-src";
 518                                 reg = <0x020d8000 0x4000>;
 519                                 interrupts = <0 91 0x04 0 96 0x04>;
 520                         };
 521
 522                         gpc: gpc@020dc000 {
 523                                 compatible = "fsl,imx6q-gpc";
 524                                 reg = <0x020dc000 0x4000>;
 525                                 interrupts = <0 89 0x04 0 90 0x04>;
 526                         };
 527
 528                         gpr: iomuxc-gpr@020e0000 {
 529                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
 530                                 reg = <0x020e0000 0x38>;
 531                         };
 532
 533                         dcic1: dcic@020e4000 {
 534                                 reg = <0x020e4000 0x4000>;
 535                                 interrupts = <0 124 0x04>;
 536                         };
 537
 538                         dcic2: dcic@020e8000 {
 539                                 reg = <0x020e8000 0x4000>;
 540                                 interrupts = <0 125 0x04>;
 541                         };
 542
 543                         sdma: sdma@020ec000 {
 544                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 545                                 reg = <0x020ec000 0x4000>;
 546                                 interrupts = <0 2 0x04>;
 547                                 clocks = <&clks 155>, <&clks 155>;
 548                                 clock-names = "ipg", "ahb";
 549                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 550                         };
 551                 };
 552
 553                 aips-bus@02100000 { /* AIPS2 */
 554                         compatible = "fsl,aips-bus", "simple-bus";
 555                         #address-cells = <1>;
 556                         #size-cells = <1>;
 557                         reg = <0x02100000 0x100000>;
 558                         ranges;
 559
 560                         caam@02100000 {
 561                                 reg = <0x02100000 0x40000>;
 562                                 interrupts = <0 105 0x04 0 106 0x04>;
 563                         };
 564
 565                         aipstz@0217c000 { /* AIPSTZ2 */
 566                                 reg = <0x0217c000 0x4000>;
 567                         };
 568
 569                         usbotg: usb@02184000 {
 570                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 571                                 reg = <0x02184000 0x200>;
 572                                 interrupts = <0 43 0x04>;
 573                                 clocks = <&clks 162>;
 574                                 fsl,usbphy = <&usbphy1>;
 575                                 fsl,usbmisc = <&usbmisc 0>;
 576                                 status = "disabled";
 577                         };
 578
 579                         usbh1: usb@02184200 {
 580                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 581                                 reg = <0x02184200 0x200>;
 582                                 interrupts = <0 40 0x04>;
 583                                 clocks = <&clks 162>;
 584                                 fsl,usbphy = <&usbphy2>;
 585                                 fsl,usbmisc = <&usbmisc 1>;
 586                                 status = "disabled";
 587                         };
 588
 589                         usbh2: usb@02184400 {
 590                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 591                                 reg = <0x02184400 0x200>;
 592                                 interrupts = <0 41 0x04>;
 593                                 clocks = <&clks 162>;
 594                                 fsl,usbmisc = <&usbmisc 2>;
 595                                 status = "disabled";
 596                         };
 597
 598                         usbh3: usb@02184600 {
 599                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 600                                 reg = <0x02184600 0x200>;
 601                                 interrupts = <0 42 0x04>;
 602                                 clocks = <&clks 162>;
 603                                 fsl,usbmisc = <&usbmisc 3>;
 604                                 status = "disabled";
 605                         };
 606
 607                         usbmisc: usbmisc: usbmisc@02184800 {
 608                                 #index-cells = <1>;
 609                                 compatible = "fsl,imx6q-usbmisc";
 610                                 reg = <0x02184800 0x200>;
 611                                 clocks = <&clks 162>;
 612                         };
 613
 614                         fec: ethernet@02188000 {
 615                                 compatible = "fsl,imx6q-fec";
 616                                 reg = <0x02188000 0x4000>;
 617                                 interrupts = <0 118 0x04 0 119 0x04>;
 618                                 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
 619                                 clock-names = "ipg", "ahb", "ptp";
 620                                 status = "disabled";
 621                         };
 622
 623                         mlb@0218c000 {
 624                                 reg = <0x0218c000 0x4000>;
 625                                 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
 626                         };
 627
 628                         usdhc1: usdhc@02190000 {
 629                                 compatible = "fsl,imx6q-usdhc";
 630                                 reg = <0x02190000 0x4000>;
 631                                 interrupts = <0 22 0x04>;
 632                                 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
 633                                 clock-names = "ipg", "ahb", "per";
 634                                 bus-width = <4>;
 635                                 status = "disabled";
 636                         };
 637
 638                         usdhc2: usdhc@02194000 {
 639                                 compatible = "fsl,imx6q-usdhc";
 640                                 reg = <0x02194000 0x4000>;
 641                                 interrupts = <0 23 0x04>;
 642                                 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
 643                                 clock-names = "ipg", "ahb", "per";
 644                                 bus-width = <4>;
 645                                 status = "disabled";
 646                         };
 647
 648                         usdhc3: usdhc@02198000 {
 649                                 compatible = "fsl,imx6q-usdhc";
 650                                 reg = <0x02198000 0x4000>;
 651                                 interrupts = <0 24 0x04>;
 652                                 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
 653                                 clock-names = "ipg", "ahb", "per";
 654                                 bus-width = <4>;
 655                                 status = "disabled";
 656                         };
 657
 658                         usdhc4: usdhc@0219c000 {
 659                                 compatible = "fsl,imx6q-usdhc";
 660                                 reg = <0x0219c000 0x4000>;
 661                                 interrupts = <0 25 0x04>;
 662                                 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
 663                                 clock-names = "ipg", "ahb", "per";
 664                                 bus-width = <4>;
 665                                 status = "disabled";
 666                         };
 667
 668                         i2c1: i2c@021a0000 {
 669                                 #address-cells = <1>;
 670                                 #size-cells = <0>;
 671                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 672                                 reg = <0x021a0000 0x4000>;
 673                                 interrupts = <0 36 0x04>;
 674                                 clocks = <&clks 125>;
 675                                 status = "disabled";
 676                         };
 677
 678                         i2c2: i2c@021a4000 {
 679                                 #address-cells = <1>;
 680                                 #size-cells = <0>;
 681                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 682                                 reg = <0x021a4000 0x4000>;
 683                                 interrupts = <0 37 0x04>;
 684                                 clocks = <&clks 126>;
 685                                 status = "disabled";
 686                         };
 687
 688                         i2c3: i2c@021a8000 {
 689                                 #address-cells = <1>;
 690                                 #size-cells = <0>;
 691                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 692                                 reg = <0x021a8000 0x4000>;
 693                                 interrupts = <0 38 0x04>;
 694                                 clocks = <&clks 127>;
 695                                 status = "disabled";
 696                         };
 697
 698                         romcp@021ac000 {
 699                                 reg = <0x021ac000 0x4000>;
 700                         };
 701
 702                         mmdc0: mmdc@021b0000 { /* MMDC0 */
 703                                 compatible = "fsl,imx6q-mmdc";
 704                                 reg = <0x021b0000 0x4000>;
 705                         };
 706
 707                         mmdc1: mmdc@021b4000 { /* MMDC1 */
 708                                 reg = <0x021b4000 0x4000>;
 709                         };
 710
 711                         weim@021b8000 {
 712                                 reg = <0x021b8000 0x4000>;
 713                                 interrupts = <0 14 0x04>;
 714                         };
 715
 716                         ocotp@021bc000 {
 717                                 compatible = "fsl,imx6q-ocotp";
 718                                 reg = <0x021bc000 0x4000>;
 719                         };
 720
 721                         ocotp@021c0000 {
 722                                 reg = <0x021c0000 0x4000>;
 723                                 interrupts = <0 21 0x04>;
 724                         };
 725
 726                         tzasc@021d0000 { /* TZASC1 */
 727                                 reg = <0x021d0000 0x4000>;
 728                                 interrupts = <0 108 0x04>;
 729                         };
 730
 731                         tzasc@021d4000 { /* TZASC2 */
 732                                 reg = <0x021d4000 0x4000>;
 733                                 interrupts = <0 109 0x04>;
 734                         };
 735
 736                         audmux: audmux@021d8000 {
 737                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
 738                                 reg = <0x021d8000 0x4000>;
 739                                 status = "disabled";
 740                         };
 741
 742                         mipi@021dc000 { /* MIPI-CSI */
 743                                 reg = <0x021dc000 0x4000>;
 744                         };
 745
 746                         mipi@021e0000 { /* MIPI-DSI */
 747                                 reg = <0x021e0000 0x4000>;
 748                         };
 749
 750                         vdoa@021e4000 {
 751                                 reg = <0x021e4000 0x4000>;
 752                                 interrupts = <0 18 0x04>;
 753                         };
 754
 755                         uart2: serial@021e8000 {
 756                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 757                                 reg = <0x021e8000 0x4000>;
 758                                 interrupts = <0 27 0x04>;
 759                                 clocks = <&clks 160>, <&clks 161>;
 760                                 clock-names = "ipg", "per";
 761                                 status = "disabled";
 762                         };
 763
 764                         uart3: serial@021ec000 {
 765                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 766                                 reg = <0x021ec000 0x4000>;
 767                                 interrupts = <0 28 0x04>;
 768                                 clocks = <&clks 160>, <&clks 161>;
 769                                 clock-names = "ipg", "per";
 770                                 status = "disabled";
 771                         };
 772
 773                         uart4: serial@021f0000 {
 774                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 775                                 reg = <0x021f0000 0x4000>;
 776                                 interrupts = <0 29 0x04>;
 777                                 clocks = <&clks 160>, <&clks 161>;
 778                                 clock-names = "ipg", "per";
 779                                 status = "disabled";
 780                         };
 781
 782                         uart5: serial@021f4000 {
 783                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 784                                 reg = <0x021f4000 0x4000>;
 785                                 interrupts = <0 30 0x04>;
 786                                 clocks = <&clks 160>, <&clks 161>;
 787                                 clock-names = "ipg", "per";
 788                                 status = "disabled";
 789                         };
 790                 };
 791
 792                 ipu1: ipu@02400000 {
 793                         #crtc-cells = <1>;
 794                         compatible = "fsl,imx6q-ipu";
 795                         reg = <0x02400000 0x400000>;
 796                         interrupts = <0 6 0x4 0 5 0x4>;
 797                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
 798                         clock-names = "bus", "di0", "di1";
 799                 };
 800         };
 801 };