arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include "skeleton.dtsi"
  13 #include "imx6sl-pinfunc.h"
  14 #include <dt-bindings/clock/imx6sl-clock.h>
  15
  16 / {
  17         aliases {
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 gpio3 = &gpio4;
  22                 gpio4 = &gpio5;
  23                 mmc0 = &usdhc1;
  24                 mmc1 = &usdhc2;
  25                 mmc2 = &usdhc3;
  26                 mmc3 = &usdhc4;
  27                 serial0 = &uart1;
  28                 serial1 = &uart2;
  29                 serial2 = &uart3;
  30                 serial3 = &uart4;
  31                 serial4 = &uart5;
  32                 spi0 = &ecspi1;
  33                 spi1 = &ecspi2;
  34                 spi2 = &ecspi3;
  35                 spi3 = &ecspi4;
  36                 usbphy0 = &usbphy1;
  37                 usbphy1 = &usbphy2;
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 cpu0: cpu@0 {
  45                         compatible = "arm,cortex-a9";
  46                         device_type = "cpu";
  47                         reg = <0x0>;
  48                         next-level-cache = <&L2>;
  49                         operating-points = <
  50                                 /* kHz    uV */
  51                                 996000  1275000
  52                                 792000  1175000
  53                                 396000  975000
  54                         >;
  55                         fsl,soc-operating-points = <
  56                                 /* ARM kHz      SOC-PU uV */
  57                                 996000          1225000
  58                                 792000          1175000
  59                                 396000          1175000
  60                         >;
  61                         clock-latency = <61036>; /* two CLK32 periods */
  62                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  63                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  64                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  65                         clock-names = "arm", "pll2_pfd2_396m", "step",
  66                                       "pll1_sw", "pll1_sys";
  67                         arm-supply = <&reg_arm>;
  68                         pu-supply = <&reg_pu>;
  69                         soc-supply = <&reg_soc>;
  70                 };
  71         };
  72
  73         intc: interrupt-controller@00a01000 {
  74                 compatible = "arm,cortex-a9-gic";
  75                 #interrupt-cells = <3>;
  76                 #address-cells = <1>;
  77                 #size-cells = <1>;
  78                 interrupt-controller;
  79                 reg = <0x00a01000 0x1000>,
  80                       <0x00a00100 0x100>;
  81         };
  82
  83         clocks {
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86
  87                 ckil {
  88                         compatible = "fixed-clock";
  89                         clock-frequency = <32768>;
  90                 };
  91
  92                 osc {
  93                         compatible = "fixed-clock";
  94                         clock-frequency = <24000000>;
  95                 };
  96         };
  97
  98         soc {
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 compatible = "simple-bus";
 102                 interrupt-parent = <&intc>;
 103                 ranges;
 104
 105                 busfreq { /* BUSFREQ */
 106                         compatible = "fsl,imx6_busfreq";
 107                         clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>,
 108                                         <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>,
 109                                         <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>,
 110                                         <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>,
 111                                         <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>,
 112                                         <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>,
 113                                         <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM>,
 114                                         <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
 115                                         <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>,
 116                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>,
 117                                         <&clks IMX6SL_CLK_PLL2>;
 118                         clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
 119                                 "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb",
 120                                 "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src",
 121                                 "pll2_bypass", "pll2";
 122                         fsl,max_ddr_freq = <400000000>;
 123                 };
 124
 125                 ocrams: sram@00900000 {
 126                         compatible = "fsl,lpm-sram";
 127                         reg = <0x00900000 0x4000>;
 128                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 129                 };
 130
 131                 ocrams_ddr: sram@00904000 {
 132                         compatible = "fsl,ddr-lpm-sram";
 133                         reg = <0x00904000 0x1000>;
 134                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 135                 };
 136
 137                 ocram: sram@00905000 {
 138                         compatible = "mmio-sram";
 139                         reg = <0x00905000 0x1B000>;
 140                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 141                 };
 142
 143                 L2: l2-cache@00a02000 {
 144                         compatible = "arm,pl310-cache";
 145                         reg = <0x00a02000 0x1000>;
 146                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 147                         cache-unified;
 148                         cache-level = <2>;
 149                         arm,tag-latency = <4 2 3>;
 150                         arm,data-latency = <4 2 3>;
 151                 };
 152
 153                 pmu {
 154                         compatible = "arm,cortex-a9-pmu";
 155                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 156                 };
 157
 158                 aips1: aips-bus@02000000 {
 159                         compatible = "fsl,aips-bus", "simple-bus";
 160                         #address-cells = <1>;
 161                         #size-cells = <1>;
 162                         reg = <0x02000000 0x100000>;
 163                         ranges;
 164
 165                         spba: spba-bus@02000000 {
 166                                 compatible = "fsl,spba-bus", "simple-bus";
 167                                 #address-cells = <1>;
 168                                 #size-cells = <1>;
 169                                 reg = <0x02000000 0x40000>;
 170                                 ranges;
 171
 172                                 spdif: spdif@02004000 {
 173                                         compatible = "fsl,imx6sl-spdif",
 174                                                 "fsl,imx35-spdif";
 175                                         reg = <0x02004000 0x4000>;
 176                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 177                                         dmas = <&sdma 14 18 0>,
 178                                                <&sdma 15 18 0>;
 179                                         dma-names = "rx", "tx";
 180                                         clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
 181                                                  <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
 182                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
 183                                                  <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
 184                                                  <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
 185                                         clock-names = "core", "rxtx0",
 186                                                 "rxtx1", "rxtx2",
 187                                                 "rxtx3", "rxtx4",
 188                                                 "rxtx5", "rxtx6",
 189                                                 "rxtx7", "dma";
 190                                         status = "disabled";
 191                                 };
 192
 193                                 ecspi1: ecspi@02008000 {
 194                                         #address-cells = <1>;
 195                                         #size-cells = <0>;
 196                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 197                                         reg = <0x02008000 0x4000>;
 198                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 199                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 200                                                  <&clks IMX6SL_CLK_ECSPI1>;
 201                                         clock-names = "ipg", "per";
 202                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 203                                         dma-names = "rx", "tx";
 204                                         status = "disabled";
 205                                 };
 206
 207                                 ecspi2: ecspi@0200c000 {
 208                                         #address-cells = <1>;
 209                                         #size-cells = <0>;
 210                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 211                                         reg = <0x0200c000 0x4000>;
 212                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 213                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 214                                                  <&clks IMX6SL_CLK_ECSPI2>;
 215                                         clock-names = "ipg", "per";
 216                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 217                                         dma-names = "rx", "tx";
 218                                         status = "disabled";
 219                                 };
 220
 221                                 ecspi3: ecspi@02010000 {
 222                                         #address-cells = <1>;
 223                                         #size-cells = <0>;
 224                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 225                                         reg = <0x02010000 0x4000>;
 226                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 227                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 228                                                  <&clks IMX6SL_CLK_ECSPI3>;
 229                                         clock-names = "ipg", "per";
 230                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 231                                         dma-names = "rx", "tx";
 232                                         status = "disabled";
 233                                 };
 234
 235                                 ecspi4: ecspi@02014000 {
 236                                         #address-cells = <1>;
 237                                         #size-cells = <0>;
 238                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 239                                         reg = <0x02014000 0x4000>;
 240                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 241                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 242                                                  <&clks IMX6SL_CLK_ECSPI4>;
 243                                         clock-names = "ipg", "per";
 244                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 245                                         dma-names = "rx", "tx";
 246                                         status = "disabled";
 247                                 };
 248
 249                                 uart5: serial@02018000 {
 250                                         compatible = "fsl,imx6sl-uart",
 251                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 252                                         reg = <0x02018000 0x4000>;
 253                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 254                                         clocks = <&clks IMX6SL_CLK_UART>,
 255                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 256                                         clock-names = "ipg", "per";
 257                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 258                                         dma-names = "rx", "tx";
 259                                         status = "disabled";
 260                                 };
 261
 262                                 uart1: serial@02020000 {
 263                                         compatible = "fsl,imx6sl-uart",
 264                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 265                                         reg = <0x02020000 0x4000>;
 266                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 267                                         clocks = <&clks IMX6SL_CLK_UART>,
 268                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 269                                         clock-names = "ipg", "per";
 270                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 271                                         dma-names = "rx", "tx";
 272                                         status = "disabled";
 273                                 };
 274
 275                                 uart2: serial@02024000 {
 276                                         compatible = "fsl,imx6sl-uart",
 277                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 278                                         reg = <0x02024000 0x4000>;
 279                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 280                                         clocks = <&clks IMX6SL_CLK_UART>,
 281                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 282                                         clock-names = "ipg", "per";
 283                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 284                                         dma-names = "rx", "tx";
 285                                         status = "disabled";
 286                                 };
 287
 288                                 ssi1: ssi@02028000 {
 289                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 290                                         reg = <0x02028000 0x4000>;
 291                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 292                                         clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 293                                                  <&clks IMX6SL_CLK_SSI1>;
 294                                         clock-names = "ipg", "baud";
 295                                         dmas = <&sdma 37 1 0>,
 296                                                <&sdma 38 1 0>;
 297                                         dma-names = "rx", "tx";
 298                                         fsl,fifo-depth = <15>;
 299                                         status = "disabled";
 300                                 };
 301
 302                                 ssi2: ssi@0202c000 {
 303                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 304                                         reg = <0x0202c000 0x4000>;
 305                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 306                                         clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 307                                                  <&clks IMX6SL_CLK_SSI2>;
 308                                         clock-names = "ipg", "baud";
 309                                         dmas = <&sdma 41 1 0>,
 310                                                <&sdma 42 1 0>;
 311                                         dma-names = "rx", "tx";
 312                                         fsl,fifo-depth = <15>;
 313                                         status = "disabled";
 314                                 };
 315
 316                                 ssi3: ssi@02030000 {
 317                                         compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
 318                                         reg = <0x02030000 0x4000>;
 319                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 320                                         clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 321                                                  <&clks IMX6SL_CLK_SSI3>;
 322                                         clock-names = "ipg", "baud";
 323                                         dmas = <&sdma 45 1 0>,
 324                                                <&sdma 46 1 0>;
 325                                         dma-names = "rx", "tx";
 326                                         fsl,fifo-depth = <15>;
 327                                         status = "disabled";
 328                                 };
 329
 330                                 uart3: serial@02034000 {
 331                                         compatible = "fsl,imx6sl-uart",
 332                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 333                                         reg = <0x02034000 0x4000>;
 334                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 335                                         clocks = <&clks IMX6SL_CLK_UART>,
 336                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 337                                         clock-names = "ipg", "per";
 338                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 339                                         dma-names = "rx", "tx";
 340                                         status = "disabled";
 341                                 };
 342
 343                                 uart4: serial@02038000 {
 344                                         compatible = "fsl,imx6sl-uart",
 345                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 346                                         reg = <0x02038000 0x4000>;
 347                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 348                                         clocks = <&clks IMX6SL_CLK_UART>,
 349                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 350                                         clock-names = "ipg", "per";
 351                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 352                                         dma-names = "rx", "tx";
 353                                         status = "disabled";
 354                                 };
 355                         };
 356
 357                         pwm1: pwm@02080000 {
 358                                 #pwm-cells = <2>;
 359                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 360                                 reg = <0x02080000 0x4000>;
 361                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 362                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 363                                          <&clks IMX6SL_CLK_PWM1>;
 364                                 clock-names = "ipg", "per";
 365                         };
 366
 367                         pwm2: pwm@02084000 {
 368                                 #pwm-cells = <2>;
 369                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 370                                 reg = <0x02084000 0x4000>;
 371                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 372                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 373                                          <&clks IMX6SL_CLK_PWM2>;
 374                                 clock-names = "ipg", "per";
 375                         };
 376
 377                         pwm3: pwm@02088000 {
 378                                 #pwm-cells = <2>;
 379                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 380                                 reg = <0x02088000 0x4000>;
 381                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 382                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 383                                          <&clks IMX6SL_CLK_PWM3>;
 384                                 clock-names = "ipg", "per";
 385                         };
 386
 387                         pwm4: pwm@0208c000 {
 388                                 #pwm-cells = <2>;
 389                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 390                                 reg = <0x0208c000 0x4000>;
 391                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 392                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 393                                          <&clks IMX6SL_CLK_PWM4>;
 394                                 clock-names = "ipg", "per";
 395                         };
 396
 397                         gpt: gpt@02098000 {
 398                                 compatible = "fsl,imx6sl-gpt";
 399                                 reg = <0x02098000 0x4000>;
 400                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 401                                 clocks = <&clks IMX6SL_CLK_GPT>,
 402                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 403                                 clock-names = "ipg", "per";
 404                         };
 405
 406                         gpio1: gpio@0209c000 {
 407                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 408                                 reg = <0x0209c000 0x4000>;
 409                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 410                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 411                                 gpio-controller;
 412                                 #gpio-cells = <2>;
 413                                 interrupt-controller;
 414                                 #interrupt-cells = <2>;
 415                         };
 416
 417                         gpio2: gpio@020a0000 {
 418                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 419                                 reg = <0x020a0000 0x4000>;
 420                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 421                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 422                                 gpio-controller;
 423                                 #gpio-cells = <2>;
 424                                 interrupt-controller;
 425                                 #interrupt-cells = <2>;
 426                         };
 427
 428                         gpio3: gpio@020a4000 {
 429                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 430                                 reg = <0x020a4000 0x4000>;
 431                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 433                                 gpio-controller;
 434                                 #gpio-cells = <2>;
 435                                 interrupt-controller;
 436                                 #interrupt-cells = <2>;
 437                         };
 438
 439                         gpio4: gpio@020a8000 {
 440                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 441                                 reg = <0x020a8000 0x4000>;
 442                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 443                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 444                                 gpio-controller;
 445                                 #gpio-cells = <2>;
 446                                 interrupt-controller;
 447                                 #interrupt-cells = <2>;
 448                         };
 449
 450                         gpio5: gpio@020ac000 {
 451                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 452                                 reg = <0x020ac000 0x4000>;
 453                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 454                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 455                                 gpio-controller;
 456                                 #gpio-cells = <2>;
 457                                 interrupt-controller;
 458                                 #interrupt-cells = <2>;
 459                         };
 460
 461                         kpp: kpp@020b8000 {
 462                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 463                                 reg = <0x020b8000 0x4000>;
 464                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 465                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 466                         };
 467
 468                         wdog1: wdog@020bc000 {
 469                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 470                                 reg = <0x020bc000 0x4000>;
 471                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 472                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 473                         };
 474
 475                         wdog2: wdog@020c0000 {
 476                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 477                                 reg = <0x020c0000 0x4000>;
 478                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 479                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 480                                 status = "disabled";
 481                         };
 482
 483                         clks: ccm@020c4000 {
 484                                 compatible = "fsl,imx6sl-ccm";
 485                                 reg = <0x020c4000 0x4000>;
 486                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 487                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 488                                 #clock-cells = <1>;
 489                         };
 490
 491                         anatop: anatop@020c8000 {
 492                                 compatible = "fsl,imx6sl-anatop",
 493                                              "fsl,imx6q-anatop",
 494                                              "syscon", "simple-bus";
 495                                 reg = <0x020c8000 0x1000>;
 496                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 497                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 498                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 499
 500                                 regulator-1p1@110 {
 501                                         compatible = "fsl,anatop-regulator";
 502                                         regulator-name = "vdd1p1";
 503                                         regulator-min-microvolt = <800000>;
 504                                         regulator-max-microvolt = <1375000>;
 505                                         regulator-always-on;
 506                                         anatop-reg-offset = <0x110>;
 507                                         anatop-vol-bit-shift = <8>;
 508                                         anatop-vol-bit-width = <5>;
 509                                         anatop-min-bit-val = <4>;
 510                                         anatop-min-voltage = <800000>;
 511                                         anatop-max-voltage = <1375000>;
 512                                 };
 513
 514                                 regulator-3p0@120 {
 515                                         compatible = "fsl,anatop-regulator";
 516                                         regulator-name = "vdd3p0";
 517                                         regulator-min-microvolt = <2800000>;
 518                                         regulator-max-microvolt = <3150000>;
 519                                         regulator-always-on;
 520                                         anatop-reg-offset = <0x120>;
 521                                         anatop-vol-bit-shift = <8>;
 522                                         anatop-vol-bit-width = <5>;
 523                                         anatop-min-bit-val = <0>;
 524                                         anatop-min-voltage = <2625000>;
 525                                         anatop-max-voltage = <3400000>;
 526                                 };
 527
 528                                 regulator-2p5@130 {
 529                                         compatible = "fsl,anatop-regulator";
 530                                         regulator-name = "vdd2p5";
 531                                         regulator-min-microvolt = <2100000>;
 532                                         regulator-max-microvolt = <2850000>;
 533                                         regulator-always-on;
 534                                         anatop-reg-offset = <0x130>;
 535                                         anatop-vol-bit-shift = <8>;
 536                                         anatop-vol-bit-width = <5>;
 537                                         anatop-min-bit-val = <0>;
 538                                         anatop-min-voltage = <2100000>;
 539                                         anatop-max-voltage = <2850000>;
 540                                 };
 541
 542                                 reg_arm: regulator-vddcore@140 {
 543                                         compatible = "fsl,anatop-regulator";
 544                                         regulator-name = "vddarm";
 545                                         regulator-min-microvolt = <725000>;
 546                                         regulator-max-microvolt = <1450000>;
 547                                         regulator-always-on;
 548                                         anatop-reg-offset = <0x140>;
 549                                         anatop-vol-bit-shift = <0>;
 550                                         anatop-vol-bit-width = <5>;
 551                                         anatop-delay-reg-offset = <0x170>;
 552                                         anatop-delay-bit-shift = <24>;
 553                                         anatop-delay-bit-width = <2>;
 554                                         anatop-min-bit-val = <1>;
 555                                         anatop-min-voltage = <725000>;
 556                                         anatop-max-voltage = <1450000>;
 557                                         regulator-allow-bypass;
 558                                 };
 559
 560                                 reg_pu: regulator-vddpu@140 {
 561                                         compatible = "fsl,anatop-regulator";
 562                                         regulator-name = "vddpu";
 563                                         regulator-min-microvolt = <725000>;
 564                                         regulator-max-microvolt = <1450000>;
 565                                         regulator-enable-ramp-delay = <150>;
 566                                         regulator-boot-on;
 567                                         anatop-reg-offset = <0x140>;
 568                                         anatop-vol-bit-shift = <9>;
 569                                         anatop-vol-bit-width = <5>;
 570                                         anatop-delay-reg-offset = <0x170>;
 571                                         anatop-delay-bit-shift = <26>;
 572                                         anatop-delay-bit-width = <2>;
 573                                         anatop-min-bit-val = <1>;
 574                                         anatop-min-voltage = <725000>;
 575                                         anatop-max-voltage = <1450000>;
 576                                         regulator-allow-bypass;
 577                                 };
 578
 579                                 reg_soc: regulator-vddsoc@140 {
 580                                         compatible = "fsl,anatop-regulator";
 581                                         regulator-name = "vddsoc";
 582                                         regulator-min-microvolt = <725000>;
 583                                         regulator-max-microvolt = <1450000>;
 584                                         regulator-always-on;
 585                                         anatop-reg-offset = <0x140>;
 586                                         anatop-vol-bit-shift = <18>;
 587                                         anatop-vol-bit-width = <5>;
 588                                         anatop-delay-reg-offset = <0x170>;
 589                                         anatop-delay-bit-shift = <28>;
 590                                         anatop-delay-bit-width = <2>;
 591                                         anatop-min-bit-val = <1>;
 592                                         anatop-min-voltage = <725000>;
 593                                         anatop-max-voltage = <1450000>;
 594                                         regulator-allow-bypass;
 595                                 };
 596                         };
 597
 598                         tempmon: tempmon {
 599                                 compatible = "fsl,imx6sl-tempmon", "fsl,imx6q-tempmon";
 600                                 interrupts = <0 49 0x04>;
 601                                 fsl,tempmon = <&anatop>;
 602                                 fsl,tempmon-data = <&ocotp>;
 603                                 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
 604                         };
 605
 606                         usbphy1: usbphy@020c9000 {
 607                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 608                                 reg = <0x020c9000 0x1000>;
 609                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 610                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 611                                 fsl,anatop = <&anatop>;
 612                         };
 613
 614                         usbphy2: usbphy@020ca000 {
 615                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 616                                 reg = <0x020ca000 0x1000>;
 617                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 618                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 619                                 fsl,anatop = <&anatop>;
 620                         };
 621
 622                         usbphy_nop1: usbphy_nop1 {
 623                                 compatible = "usb-nop-xceiv";
 624                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 625                                 clock-names = "main_clk";
 626                         };
 627
 628                         snvs@020cc000 {
 629                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 630                                 #address-cells = <1>;
 631                                 #size-cells = <1>;
 632                                 ranges = <0 0x020cc000 0x4000>;
 633
 634                                 snvs-rtc-lp@34 {
 635                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 636                                         reg = <0x34 0x58>;
 637                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 638                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 639                                 };
 640                         };
 641
 642                         epit1: epit@020d0000 {
 643                                 reg = <0x020d0000 0x4000>;
 644                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 645                         };
 646
 647                         epit2: epit@020d4000 {
 648                                 reg = <0x020d4000 0x4000>;
 649                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 650                         };
 651
 652                         src: src@020d8000 {
 653                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 654                                 reg = <0x020d8000 0x4000>;
 655                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 656                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 657                                 #reset-cells = <1>;
 658                         };
 659
 660                         gpc: gpc@020dc000 {
 661                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 662                                 reg = <0x020dc000 0x4000>;
 663                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 664                                 pu-supply = <&reg_pu>;
 665                                 clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>,
 666                                         <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>,
 667                                         <&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>,
 668                                         <&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>;
 669                                 clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi",
 670                                                 "lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi";
 671                                 #power-domain-cells = <1>;
 672                         };
 673
 674                         gpr: iomuxc-gpr@020e0000 {
 675                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 676                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 677                                 reg = <0x020e0000 0x38>;
 678                         };
 679
 680                         iomuxc: iomuxc@020e0000 {
 681                                 compatible = "fsl,imx6sl-iomuxc";
 682                                 reg = <0x020e0000 0x4000>;
 683                         };
 684
 685                         csi: csi@020e4000 {
 686                                 compatible = "fsl,imx6s-csi";
 687                                 reg = <0x020e4000 0x4000>;
 688                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 689                                 clocks = <&clks IMX6SL_CLK_DUMMY>,
 690                                         <&clks IMX6SL_CLK_DUMMY>,
 691                                         <&clks IMX6SL_CLK_DUMMY>;
 692                                 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
 693                                 power-domains = <&gpc 2>;
 694                                 status = "disabled";
 695                         };
 696
 697                         spdc: spdc@020e8000 {
 698                                 reg = <0x020e8000 0x4000>;
 699                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 700                         };
 701
 702                         sdma: sdma@020ec000 {
 703                                 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
 704                                 reg = <0x020ec000 0x4000>;
 705                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 706                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 707                                          <&clks IMX6SL_CLK_SDMA>;
 708                                 clock-names = "ipg", "ahb";
 709                                 #dma-cells = <3>;
 710                                 iram = <&ocram>;
 711                                 /* imx6sl reuses imx6q sdma firmware */
 712                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 713                         };
 714
 715                         pxp: pxp@020f0000 {
 716                                 compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
 717                                 reg = <0x020f0000 0x4000>;
 718                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 719                                 clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>;
 720                                 clock-names = "pxp-axi", "disp-axi";
 721                                 power-domains = <&gpc 2>;
 722                                 status = "disabled";
 723                         };
 724
 725                         epdc: epdc@020f4000 {
 726                                 compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
 727                                 reg = <0x020f4000 0x4000>;
 728                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 729                                 clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>;
 730                                 clock-names = "epdc_axi", "epdc_pix";
 731                                 power-domains = <&gpc 2>;
 732                         };
 733
 734                         lcdif: lcdif@020f8000 {
 735                                 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
 736                                 reg = <0x020f8000 0x4000>;
 737                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 738                                 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
 739                                          <&clks IMX6SL_CLK_LCDIF_AXI>,
 740                                          <&clks IMX6SL_CLK_DUMMY>;
 741                                 clock-names = "pix", "axi", "disp_axi";
 742                                 power-domains = <&gpc 2>;
 743                                 status = "disabled";
 744                         };
 745
 746
 747                         dcp: dcp@020fc000 {
 748                                 reg = <0x020fc000 0x4000>;
 749                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
 750                         };
 751                 };
 752
 753                 aips2: aips-bus@02100000 {
 754                         compatible = "fsl,aips-bus", "simple-bus";
 755                         #address-cells = <1>;
 756                         #size-cells = <1>;
 757                         reg = <0x02100000 0x100000>;
 758                         ranges;
 759
 760                         usbotg1: usb@02184000 {
 761                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 762                                 reg = <0x02184000 0x200>;
 763                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 764                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 765                                 fsl,usbphy = <&usbphy1>;
 766                                 fsl,usbmisc = <&usbmisc 0>;
 767                                 fsl,anatop = <&anatop>;
 768                                 status = "disabled";
 769                         };
 770
 771                         usbotg2: usb@02184200 {
 772                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 773                                 reg = <0x02184200 0x200>;
 774                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 775                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 776                                 fsl,usbphy = <&usbphy2>;
 777                                 fsl,usbmisc = <&usbmisc 1>;
 778                                 status = "disabled";
 779                         };
 780
 781                         usbh: usb@02184400 {
 782                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 783                                 reg = <0x02184400 0x200>;
 784                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 785                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 786                                 fsl,usbmisc = <&usbmisc 2>;
 787                                 phy_type = "hsic";
 788                                 fsl,usbphy = <&usbphy_nop1>;
 789                                 fsl,anatop = <&anatop>;
 790                                 status = "disabled";
 791                         };
 792
 793                         usbmisc: usbmisc@02184800 {
 794                                 #index-cells = <1>;
 795                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 796                                 reg = <0x02184800 0x200>;
 797                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 798                         };
 799
 800                         fec: ethernet@02188000 {
 801                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 802                                 reg = <0x02188000 0x4000>;
 803                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clks IMX6SL_CLK_ENET_REF>,
 805                                          <&clks IMX6SL_CLK_ENET_REF>;
 806                                 clock-names = "ipg", "ahb";
 807                                 status = "disabled";
 808                         };
 809
 810                         usdhc1: usdhc@02190000 {
 811                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 812                                 reg = <0x02190000 0x4000>;
 813                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 814                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 815                                          <&clks IMX6SL_CLK_USDHC1>,
 816                                          <&clks IMX6SL_CLK_USDHC1>;
 817                                 clock-names = "ipg", "ahb", "per";
 818                                 bus-width = <4>;
 819                                 status = "disabled";
 820                         };
 821
 822                         usdhc2: usdhc@02194000 {
 823                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 824                                 reg = <0x02194000 0x4000>;
 825                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 826                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 827                                          <&clks IMX6SL_CLK_USDHC2>,
 828                                          <&clks IMX6SL_CLK_USDHC2>;
 829                                 clock-names = "ipg", "ahb", "per";
 830                                 bus-width = <4>;
 831                                 status = "disabled";
 832                         };
 833
 834                         usdhc3: usdhc@02198000 {
 835                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 836                                 reg = <0x02198000 0x4000>;
 837                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 838                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 839                                          <&clks IMX6SL_CLK_USDHC3>,
 840                                          <&clks IMX6SL_CLK_USDHC3>;
 841                                 clock-names = "ipg", "ahb", "per";
 842                                 bus-width = <4>;
 843                                 status = "disabled";
 844                         };
 845
 846                         usdhc4: usdhc@0219c000 {
 847                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 848                                 reg = <0x0219c000 0x4000>;
 849                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 850                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 851                                          <&clks IMX6SL_CLK_USDHC4>,
 852                                          <&clks IMX6SL_CLK_USDHC4>;
 853                                 clock-names = "ipg", "ahb", "per";
 854                                 bus-width = <4>;
 855                                 status = "disabled";
 856                         };
 857
 858                         i2c1: i2c@021a0000 {
 859                                 #address-cells = <1>;
 860                                 #size-cells = <0>;
 861                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 862                                 reg = <0x021a0000 0x4000>;
 863                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 864                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 865                                 status = "disabled";
 866                         };
 867
 868                         i2c2: i2c@021a4000 {
 869                                 #address-cells = <1>;
 870                                 #size-cells = <0>;
 871                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 872                                 reg = <0x021a4000 0x4000>;
 873                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 875                                 status = "disabled";
 876                         };
 877
 878                         i2c3: i2c@021a8000 {
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 882                                 reg = <0x021a8000 0x4000>;
 883                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 884                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 885                                 status = "disabled";
 886                         };
 887
 888                         mmdc: mmdc@021b0000 {
 889                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 890                                 reg = <0x021b0000 0x4000>;
 891                         };
 892
 893                         rngb: rngb@021b4000 {
 894                                 reg = <0x021b4000 0x4000>;
 895                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 896                         };
 897
 898                         weim: weim@021b8000 {
 899                                 reg = <0x021b8000 0x4000>;
 900                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 901                         };
 902
 903                         ocotp: ocotp-ctrl@021bc000 {
 904                                 compatible = "syscon";
 905                                 reg = <0x021bc000 0x4000>;
 906                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 907                         };
 908
 909                         ocotp-fuse@021bc000 {
 910                                 compatible = "fsl,imx6sl-ocotp", "fsl,imx6q-ocotp";
 911                                 reg = <0x021bc000 0x4000>;
 912                                 clocks = <&clks IMX6SL_CLK_OCOTP>;
 913                         };
 914
 915                         audmux: audmux@021d8000 {
 916                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 917                                 reg = <0x021d8000 0x4000>;
 918                                 status = "disabled";
 919                         };
 920
 921                         gpu: gpu@02200000 {
 922                                 compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
 923                                 reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
 924                                           <0x80000000 0x0>;
 925                                 reg-names = "iobase_2d", "iobase_vg",
 926                                                 "phys_baseaddr";
 927                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 928                                 interrupt-names = "irq_2d", "irq_vg";
 929                                 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
 930                                                 <&clks IMX6SL_CLK_MMDC_ROOT>,
 931                                                 <&clks IMX6SL_CLK_GPU2D_OVG>;
 932                                 clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
 933                                                   "gpu2d_clk";
 934                                 resets = <&src 3>, <&src 3>;
 935                                 reset-names = "gpu2d", "gpuvg";
 936                                 power-domains = <&gpc 1>;
 937                         };
 938                 };
 939         };
 940 };