arch/arm/boot/dts/meson8.dtsi

   1 /*
   2  * Copyright 2014 Carlo Caione <carlo@caione.org>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public License
  20  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include <dt-bindings/clock/meson8b-clkc.h>
  47 #include <dt-bindings/gpio/meson8-gpio.h>
  48 /include/ "meson.dtsi"
  49
  50 / {
  51         model = "Amlogic Meson8 SoC";
  52         compatible = "amlogic,meson8";
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu@200 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a9";
  61                         next-level-cache = <&L2>;
  62                         reg = <0x200>;
  63                 };
  64
  65                 cpu@201 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a9";
  68                         next-level-cache = <&L2>;
  69                         reg = <0x201>;
  70                 };
  71
  72                 cpu@202 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a9";
  75                         next-level-cache = <&L2>;
  76                         reg = <0x202>;
  77                 };
  78
  79                 cpu@203 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a9";
  82                         next-level-cache = <&L2>;
  83                         reg = <0x203>;
  84                 };
  85         };
  86 }; /* end of / */
  87
  88 &aobus {
  89         pinctrl_aobus: pinctrl@84 {
  90                 compatible = "amlogic,meson8-aobus-pinctrl";
  91                 reg = <0x84 0xc>;
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 gpio_ao: ao-bank@14 {
  97                         reg = <0x14 0x4>,
  98                               <0x2c 0x4>,
  99                               <0x24 0x8>;
 100                         reg-names = "mux", "pull", "gpio";
 101                         gpio-controller;
 102                         #gpio-cells = <2>;
 103                         gpio-ranges = <&pinctrl_aobus 0 120 16>;
 104                 };
 105
 106                 uart_ao_a_pins: uart_ao_a {
 107                         mux {
 108                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 109                                 function = "uart_ao";
 110                         };
 111                 };
 112
 113                 i2c_ao_pins: i2c_mst_ao {
 114                         mux {
 115                                 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
 116                                 function = "i2c_mst_ao";
 117                         };
 118                 };
 119         };
 120 };
 121
 122 &cbus {
 123         clkc: clock-controller@4000 {
 124                 #clock-cells = <1>;
 125                 compatible = "amlogic,meson8-clkc";
 126                 reg = <0x8000 0x4>, <0x4000 0x460>;
 127         };
 128
 129         pinctrl_cbus: pinctrl@9880 {
 130                 compatible = "amlogic,meson8-cbus-pinctrl";
 131                 reg = <0x9880 0x10>;
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 ranges;
 135
 136                 gpio: banks@80b0 {
 137                         reg = <0x80b0 0x28>,
 138                               <0x80e8 0x18>,
 139                               <0x8120 0x18>,
 140                               <0x8030 0x30>;
 141                         reg-names = "mux", "pull", "pull-enable", "gpio";
 142                         gpio-controller;
 143                         #gpio-cells = <2>;
 144                         gpio-ranges = <&pinctrl_cbus 0 0 120>;
 145                 };
 146
 147                 spi_nor_pins: nor {
 148                         mux {
 149                                 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
 150                                 function = "nor";
 151                         };
 152                 };
 153
 154                 ir_recv_pins: remote {
 155                         mux {
 156                                 groups = "remote_input";
 157                                 function = "remote";
 158                         };
 159                 };
 160
 161                 eth_pins: ethernet {
 162                         mux {
 163                                 groups = "eth_tx_clk_50m", "eth_tx_en",
 164                                          "eth_txd1", "eth_txd0",
 165                                          "eth_rx_clk_in", "eth_rx_dv",
 166                                          "eth_rxd1", "eth_rxd0", "eth_mdio",
 167                                          "eth_mdc";
 168                                 function = "ethernet";
 169                         };
 170                 };
 171         };
 172 };
 173
 174 &ethmac {
 175         clocks = <&clkc CLKID_CLK81>;
 176         clock-names = "stmmaceth";
 177 };
 178
 179 &i2c_AO {
 180         clocks = <&clkc CLKID_CLK81>;
 181 };
 182
 183 &i2c_A {
 184         clocks = <&clkc CLKID_CLK81>;
 185 };
 186
 187 &i2c_B {
 188         clocks = <&clkc CLKID_CLK81>;
 189 };
 190
 191 &L2 {
 192         arm,data-latency = <3 3 3>;
 193         arm,tag-latency = <2 2 2>;
 194         arm,filter-ranges = <0x100000 0xc0000000>;
 195 };
 196
 197 &spifc {
 198         clocks = <&clkc CLKID_CLK81>;
 199 };
 200
 201 &uart_AO {
 202         clocks = <&clkc CLKID_CLK81>;
 203 };
 204
 205 &uart_A {
 206         clocks = <&clkc CLKID_CLK81>;
 207 };
 208
 209 &uart_B {
 210         clocks = <&clkc CLKID_CLK81>;
 211 };
 212
 213 &uart_C {
 214         clocks = <&clkc CLKID_CLK81>;
 215 };