arch/arm/boot/dts/omap2.dtsi

   1 /*
   2  * Device Tree Source for OMAP2 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
  19         interrupt-parent = <&intc>;
  20
  21         aliases {
  22                 serial0 = &uart1;
  23                 serial1 = &uart2;
  24                 serial2 = &uart3;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27         };
  28
  29         cpus {
  30                 #address-cells = <0>;
  31                 #size-cells = <0>;
  32
  33                 cpu {
  34                         compatible = "arm,arm1136jf-s";
  35                         device_type = "cpu";
  36                 };
  37         };
  38
  39         pmu {
  40                 compatible = "arm,arm1136-pmu";
  41                 interrupts = <3>;
  42         };
  43
  44         soc {
  45                 compatible = "ti,omap-infra";
  46                 mpu {
  47                         compatible = "ti,omap2-mpu";
  48                         ti,hwmods = "mpu";
  49                 };
  50         };
  51
  52         ocp {
  53                 compatible = "simple-bus";
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 ranges;
  57                 ti,hwmods = "l3_main";
  58
  59                 aes: aes@480a6000 {
  60                         compatible = "ti,omap2-aes";
  61                         ti,hwmods = "aes";
  62                         reg = <0x480a6000 0x50>;
  63                         dmas = <&sdma 9 &sdma 10>;
  64                         dma-names = "tx", "rx";
  65                 };
  66
  67                 hdq1w: 1w@480b2000 {
  68                         compatible = "ti,omap2420-1w";
  69                         ti,hwmods = "hdq1w";
  70                         reg = <0x480b2000 0x1000>;
  71                         interrupts = <58>;
  72                 };
  73
  74                 mailbox: mailbox@48094000 {
  75                         compatible = "ti,omap2-mailbox";
  76                         ti,hwmods = "mailbox";
  77                         reg = <0x48094000 0x200>;
  78                         interrupts = <26>;
  79                 };
  80
  81                 intc: interrupt-controller@1 {
  82                         compatible = "ti,omap2-intc";
  83                         interrupt-controller;
  84                         #interrupt-cells = <1>;
  85                         ti,intc-size = <96>;
  86                         reg = <0x480FE000 0x1000>;
  87                 };
  88
  89                 sdma: dma-controller@48056000 {
  90                         compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
  91                         ti,hwmods = "dma";
  92                         reg = <0x48056000 0x1000>;
  93                         interrupts = <12>,
  94                                      <13>,
  95                                      <14>,
  96                                      <15>;
  97                         #dma-cells = <1>;
  98                         #dma-channels = <32>;
  99                         #dma-requests = <64>;
 100                 };
 101
 102                 i2c1: i2c@48070000 {
 103                         compatible = "ti,omap2-i2c";
 104                         ti,hwmods = "i2c1";
 105                         reg = <0x48070000 0x80>;
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108                         interrupts = <56>;
 109                         dmas = <&sdma 27 &sdma 28>;
 110                         dma-names = "tx", "rx";
 111                 };
 112
 113                 i2c2: i2c@48072000 {
 114                         compatible = "ti,omap2-i2c";
 115                         ti,hwmods = "i2c2";
 116                         reg = <0x48072000 0x80>;
 117                         #address-cells = <1>;
 118                         #size-cells = <0>;
 119                         interrupts = <57>;
 120                         dmas = <&sdma 29 &sdma 30>;
 121                         dma-names = "tx", "rx";
 122                 };
 123
 124                 mcspi1: mcspi@48098000 {
 125                         compatible = "ti,omap2-mcspi";
 126                         ti,hwmods = "mcspi1";
 127                         reg = <0x48098000 0x100>;
 128                         interrupts = <65>;
 129                         dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
 130                                 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
 131                         dma-names = "tx0", "rx0", "tx1", "rx1",
 132                                     "tx2", "rx2", "tx3", "rx3";
 133                 };
 134
 135                 mcspi2: mcspi@4809a000 {
 136                         compatible = "ti,omap2-mcspi";
 137                         ti,hwmods = "mcspi2";
 138                         reg = <0x4809a000 0x100>;
 139                         interrupts = <66>;
 140                         dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
 141                         dma-names = "tx0", "rx0", "tx1", "rx1";
 142                 };
 143
 144                 rng: rng@480a0000 {
 145                         compatible = "ti,omap2-rng";
 146                         ti,hwmods = "rng";
 147                         reg = <0x480a0000 0x50>;
 148                         interrupts = <36>;
 149                 };
 150
 151                 sham: sham@480a4000 {
 152                         compatible = "ti,omap2-sham";
 153                         ti,hwmods = "sham";
 154                         reg = <0x480a4000 0x64>;
 155                         interrupts = <51>;
 156                         dmas = <&sdma 13>;
 157                         dma-names = "rx";
 158                 };
 159
 160                 uart1: serial@4806a000 {
 161                         compatible = "ti,omap2-uart";
 162                         ti,hwmods = "uart1";
 163                         reg = <0x4806a000 0x2000>;
 164                         interrupts = <72>;
 165                         dmas = <&sdma 49 &sdma 50>;
 166                         dma-names = "tx", "rx";
 167                         clock-frequency = <48000000>;
 168                 };
 169
 170                 uart2: serial@4806c000 {
 171                         compatible = "ti,omap2-uart";
 172                         ti,hwmods = "uart2";
 173                         reg = <0x4806c000 0x400>;
 174                         interrupts = <73>;
 175                         dmas = <&sdma 51 &sdma 52>;
 176                         dma-names = "tx", "rx";
 177                         clock-frequency = <48000000>;
 178                 };
 179
 180                 uart3: serial@4806e000 {
 181                         compatible = "ti,omap2-uart";
 182                         ti,hwmods = "uart3";
 183                         reg = <0x4806e000 0x400>;
 184                         interrupts = <74>;
 185                         dmas = <&sdma 53 &sdma 54>;
 186                         dma-names = "tx", "rx";
 187                         clock-frequency = <48000000>;
 188                 };
 189
 190                 timer2: timer@4802a000 {
 191                         compatible = "ti,omap2420-timer";
 192                         reg = <0x4802a000 0x400>;
 193                         interrupts = <38>;
 194                         ti,hwmods = "timer2";
 195                 };
 196
 197                 timer3: timer@48078000 {
 198                         compatible = "ti,omap2420-timer";
 199                         reg = <0x48078000 0x400>;
 200                         interrupts = <39>;
 201                         ti,hwmods = "timer3";
 202                 };
 203
 204                 timer4: timer@4807a000 {
 205                         compatible = "ti,omap2420-timer";
 206                         reg = <0x4807a000 0x400>;
 207                         interrupts = <40>;
 208                         ti,hwmods = "timer4";
 209                 };
 210
 211                 timer5: timer@4807c000 {
 212                         compatible = "ti,omap2420-timer";
 213                         reg = <0x4807c000 0x400>;
 214                         interrupts = <41>;
 215                         ti,hwmods = "timer5";
 216                         ti,timer-dsp;
 217                 };
 218
 219                 timer6: timer@4807e000 {
 220                         compatible = "ti,omap2420-timer";
 221                         reg = <0x4807e000 0x400>;
 222                         interrupts = <42>;
 223                         ti,hwmods = "timer6";
 224                         ti,timer-dsp;
 225                 };
 226
 227                 timer7: timer@48080000 {
 228                         compatible = "ti,omap2420-timer";
 229                         reg = <0x48080000 0x400>;
 230                         interrupts = <43>;
 231                         ti,hwmods = "timer7";
 232                         ti,timer-dsp;
 233                 };
 234
 235                 timer8: timer@48082000 {
 236                         compatible = "ti,omap2420-timer";
 237                         reg = <0x48082000 0x400>;
 238                         interrupts = <44>;
 239                         ti,hwmods = "timer8";
 240                         ti,timer-dsp;
 241                 };
 242
 243                 timer9: timer@48084000 {
 244                         compatible = "ti,omap2420-timer";
 245                         reg = <0x48084000 0x400>;
 246                         interrupts = <45>;
 247                         ti,hwmods = "timer9";
 248                         ti,timer-pwm;
 249                 };
 250
 251                 timer10: timer@48086000 {
 252                         compatible = "ti,omap2420-timer";
 253                         reg = <0x48086000 0x400>;
 254                         interrupts = <46>;
 255                         ti,hwmods = "timer10";
 256                         ti,timer-pwm;
 257                 };
 258
 259                 timer11: timer@48088000 {
 260                         compatible = "ti,omap2420-timer";
 261                         reg = <0x48088000 0x400>;
 262                         interrupts = <47>;
 263                         ti,hwmods = "timer11";
 264                         ti,timer-pwm;
 265                 };
 266
 267                 timer12: timer@4808a000 {
 268                         compatible = "ti,omap2420-timer";
 269                         reg = <0x4808a000 0x400>;
 270                         interrupts = <48>;
 271                         ti,hwmods = "timer12";
 272                         ti,timer-pwm;
 273                 };
 274         };
 275 };