arch/arm/boot/dts/omap4.dtsi

   1 /*
   2  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "ti,omap4430", "ti,omap4";
  17         interrupt-parent = <&wakeupgen>;
  18
  19         aliases {
  20                 i2c0 = &i2c1;
  21                 i2c1 = &i2c2;
  22                 i2c2 = &i2c3;
  23                 i2c3 = &i2c4;
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 serial3 = &uart4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x0>;
  39
  40                         clocks = <&dpll_mpu_ck>;
  41                         clock-names = "cpu";
  42
  43                         clock-latency = <300000>; /* From omap-cpufreq driver */
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x1>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@48241000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 reg = <0x48241000 0x1000>,
  58                       <0x48240100 0x0100>;
  59                 interrupt-parent = <&gic>;
  60         };
  61
  62         L2: l2-cache-controller@48242000 {
  63                 compatible = "arm,pl310-cache";
  64                 reg = <0x48242000 0x1000>;
  65                 cache-unified;
  66                 cache-level = <2>;
  67         };
  68
  69         local-timer@48240600 {
  70                 compatible = "arm,cortex-a9-twd-timer";
  71                 clocks = <&mpu_periphclk>;
  72                 reg = <0x48240600 0x20>;
  73                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
  74                 interrupt-parent = <&gic>;
  75         };
  76
  77         wakeupgen: interrupt-controller@48281000 {
  78                 compatible = "ti,omap4-wugen-mpu";
  79                 interrupt-controller;
  80                 #interrupt-cells = <3>;
  81                 reg = <0x48281000 0x1000>;
  82                 interrupt-parent = <&gic>;
  83         };
  84
  85         /*
  86          * The soc node represents the soc top level view. It is used for IPs
  87          * that are not memory mapped in the MPU view or for the MPU itself.
  88          */
  89         soc {
  90                 compatible = "ti,omap-infra";
  91                 mpu {
  92                         compatible = "ti,omap4-mpu";
  93                         ti,hwmods = "mpu";
  94                         sram = <&ocmcram>;
  95                 };
  96
  97                 dsp {
  98                         compatible = "ti,omap3-c64";
  99                         ti,hwmods = "dsp";
 100                 };
 101
 102                 iva {
 103                         compatible = "ti,ivahd";
 104                         ti,hwmods = "iva";
 105                 };
 106         };
 107
 108         /*
 109          * XXX: Use a flat representation of the OMAP4 interconnect.
 110          * The real OMAP interconnect network is quite complex.
 111          * Since it will not bring real advantage to represent that in DT for
 112          * the moment, just use a fake OCP bus entry to represent the whole bus
 113          * hierarchy.
 114          */
 115         ocp {
 116                 compatible = "ti,omap4-l3-noc", "simple-bus";
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 ranges;
 120                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 121                 reg = <0x44000000 0x1000>,
 122                       <0x44800000 0x2000>,
 123                       <0x45000000 0x1000>;
 124                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 125                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 126
 127                 l4_cfg: l4@4a000000 {
 128                         compatible = "ti,omap4-l4-cfg", "simple-bus";
 129                         #address-cells = <1>;
 130                         #size-cells = <1>;
 131                         ranges = <0 0x4a000000 0x1000000>;
 132
 133                         cm1: cm1@4000 {
 134                                 compatible = "ti,omap4-cm1";
 135                                 reg = <0x4000 0x2000>;
 136
 137                                 cm1_clocks: clocks {
 138                                         #address-cells = <1>;
 139                                         #size-cells = <0>;
 140                                 };
 141
 142                                 cm1_clockdomains: clockdomains {
 143                                 };
 144                         };
 145
 146                         cm2: cm2@8000 {
 147                                 compatible = "ti,omap4-cm2";
 148                                 reg = <0x8000 0x3000>;
 149
 150                                 cm2_clocks: clocks {
 151                                         #address-cells = <1>;
 152                                         #size-cells = <0>;
 153                                 };
 154
 155                                 cm2_clockdomains: clockdomains {
 156                                 };
 157                         };
 158
 159                         omap4_scm_core: scm@2000 {
 160                                 compatible = "ti,omap4-scm-core", "simple-bus";
 161                                 reg = <0x2000 0x1000>;
 162                                 #address-cells = <1>;
 163                                 #size-cells = <1>;
 164                                 ranges = <0 0x2000 0x1000>;
 165
 166                                 scm_conf: scm_conf@0 {
 167                                         compatible = "syscon";
 168                                         reg = <0x0 0x800>;
 169                                         #address-cells = <1>;
 170                                         #size-cells = <1>;
 171                                 };
 172                         };
 173
 174                         omap4_padconf_core: scm@100000 {
 175                                 compatible = "ti,omap4-scm-padconf-core",
 176                                              "simple-bus";
 177                                 #address-cells = <1>;
 178                                 #size-cells = <1>;
 179                                 ranges = <0 0x100000 0x1000>;
 180
 181                                 omap4_pmx_core: pinmux@40 {
 182                                         compatible = "ti,omap4-padconf",
 183                                                      "pinctrl-single";
 184                                         reg = <0x40 0x0196>;
 185                                         #address-cells = <1>;
 186                                         #size-cells = <0>;
 187                                         #interrupt-cells = <1>;
 188                                         interrupt-controller;
 189                                         pinctrl-single,register-width = <16>;
 190                                         pinctrl-single,function-mask = <0x7fff>;
 191                                 };
 192
 193                                 omap4_padconf_global: omap4_padconf_global@5a0 {
 194                                         compatible = "syscon",
 195                                                      "simple-bus";
 196                                         reg = <0x5a0 0x170>;
 197                                         #address-cells = <1>;
 198                                         #size-cells = <1>;
 199                                         ranges = <0 0x5a0 0x170>;
 200
 201                                         pbias_regulator: pbias_regulator {
 202                                                 compatible = "ti,pbias-omap4", "ti,pbias-omap";
 203                                                 reg = <0x60 0x4>;
 204                                                 syscon = <&omap4_padconf_global>;
 205                                                 pbias_mmc_reg: pbias_mmc_omap4 {
 206                                                         regulator-name = "pbias_mmc_omap4";
 207                                                         regulator-min-microvolt = <1800000>;
 208                                                         regulator-max-microvolt = <3000000>;
 209                                                 };
 210                                         };
 211                                 };
 212                         };
 213
 214                         l4_wkup: l4@300000 {
 215                                 compatible = "ti,omap4-l4-wkup", "simple-bus";
 216                                 #address-cells = <1>;
 217                                 #size-cells = <1>;
 218                                 ranges = <0 0x300000 0x40000>;
 219
 220                                 counter32k: counter@4000 {
 221                                         compatible = "ti,omap-counter32k";
 222                                         reg = <0x4000 0x20>;
 223                                         ti,hwmods = "counter_32k";
 224                                 };
 225
 226                                 prm: prm@6000 {
 227                                         compatible = "ti,omap4-prm";
 228                                         reg = <0x6000 0x3000>;
 229                                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 230
 231                                         prm_clocks: clocks {
 232                                                 #address-cells = <1>;
 233                                                 #size-cells = <0>;
 234                                         };
 235
 236                                         prm_clockdomains: clockdomains {
 237                                         };
 238                                 };
 239
 240                                 scrm: scrm@a000 {
 241                                         compatible = "ti,omap4-scrm";
 242                                         reg = <0xa000 0x2000>;
 243
 244                                         scrm_clocks: clocks {
 245                                                 #address-cells = <1>;
 246                                                 #size-cells = <0>;
 247                                         };
 248
 249                                         scrm_clockdomains: clockdomains {
 250                                         };
 251                                 };
 252
 253                                 omap4_pmx_wkup: pinmux@1e040 {
 254                                         compatible = "ti,omap4-padconf",
 255                                                      "pinctrl-single";
 256                                         reg = <0x1e040 0x0038>;
 257                                         #address-cells = <1>;
 258                                         #size-cells = <0>;
 259                                         #interrupt-cells = <1>;
 260                                         interrupt-controller;
 261                                         pinctrl-single,register-width = <16>;
 262                                         pinctrl-single,function-mask = <0x7fff>;
 263                                 };
 264                         };
 265                 };
 266
 267                 ocmcram: ocmcram@40304000 {
 268                         compatible = "mmio-sram";
 269                         reg = <0x40304000 0xa000>; /* 40k */
 270                 };
 271
 272                 sdma: dma-controller@4a056000 {
 273                         compatible = "ti,omap4430-sdma";
 274                         reg = <0x4a056000 0x1000>;
 275                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 277                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 279                         #dma-cells = <1>;
 280                         dma-channels = <32>;
 281                         dma-requests = <127>;
 282                 };
 283
 284                 gpio1: gpio@4a310000 {
 285                         compatible = "ti,omap4-gpio";
 286                         reg = <0x4a310000 0x200>;
 287                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 288                         ti,hwmods = "gpio1";
 289                         ti,gpio-always-on;
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                         interrupt-controller;
 293                         #interrupt-cells = <2>;
 294                 };
 295
 296                 gpio2: gpio@48055000 {
 297                         compatible = "ti,omap4-gpio";
 298                         reg = <0x48055000 0x200>;
 299                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 300                         ti,hwmods = "gpio2";
 301                         gpio-controller;
 302                         #gpio-cells = <2>;
 303                         interrupt-controller;
 304                         #interrupt-cells = <2>;
 305                 };
 306
 307                 gpio3: gpio@48057000 {
 308                         compatible = "ti,omap4-gpio";
 309                         reg = <0x48057000 0x200>;
 310                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 311                         ti,hwmods = "gpio3";
 312                         gpio-controller;
 313                         #gpio-cells = <2>;
 314                         interrupt-controller;
 315                         #interrupt-cells = <2>;
 316                 };
 317
 318                 gpio4: gpio@48059000 {
 319                         compatible = "ti,omap4-gpio";
 320                         reg = <0x48059000 0x200>;
 321                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 322                         ti,hwmods = "gpio4";
 323                         gpio-controller;
 324                         #gpio-cells = <2>;
 325                         interrupt-controller;
 326                         #interrupt-cells = <2>;
 327                 };
 328
 329                 gpio5: gpio@4805b000 {
 330                         compatible = "ti,omap4-gpio";
 331                         reg = <0x4805b000 0x200>;
 332                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 333                         ti,hwmods = "gpio5";
 334                         gpio-controller;
 335                         #gpio-cells = <2>;
 336                         interrupt-controller;
 337                         #interrupt-cells = <2>;
 338                 };
 339
 340                 gpio6: gpio@4805d000 {
 341                         compatible = "ti,omap4-gpio";
 342                         reg = <0x4805d000 0x200>;
 343                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 344                         ti,hwmods = "gpio6";
 345                         gpio-controller;
 346                         #gpio-cells = <2>;
 347                         interrupt-controller;
 348                         #interrupt-cells = <2>;
 349                 };
 350
 351                 elm: elm@48078000 {
 352                         compatible = "ti,am3352-elm";
 353                         reg = <0x48078000 0x2000>;
 354                         interrupts = <4>;
 355                         ti,hwmods = "elm";
 356                         status = "disabled";
 357                 };
 358
 359                 gpmc: gpmc@50000000 {
 360                         compatible = "ti,omap4430-gpmc";
 361                         reg = <0x50000000 0x1000>;
 362                         #address-cells = <2>;
 363                         #size-cells = <1>;
 364                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 365                         dmas = <&sdma 4>;
 366                         dma-names = "rxtx";
 367                         gpmc,num-cs = <8>;
 368                         gpmc,num-waitpins = <4>;
 369                         ti,hwmods = "gpmc";
 370                         ti,no-idle-on-init;
 371                         clocks = <&l3_div_ck>;
 372                         clock-names = "fck";
 373                 };
 374
 375                 uart1: serial@4806a000 {
 376                         compatible = "ti,omap4-uart";
 377                         reg = <0x4806a000 0x100>;
 378                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 379                         ti,hwmods = "uart1";
 380                         clock-frequency = <48000000>;
 381                 };
 382
 383                 uart2: serial@4806c000 {
 384                         compatible = "ti,omap4-uart";
 385                         reg = <0x4806c000 0x100>;
 386                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 387                         ti,hwmods = "uart2";
 388                         clock-frequency = <48000000>;
 389                 };
 390
 391                 uart3: serial@48020000 {
 392                         compatible = "ti,omap4-uart";
 393                         reg = <0x48020000 0x100>;
 394                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 395                         ti,hwmods = "uart3";
 396                         clock-frequency = <48000000>;
 397                 };
 398
 399                 uart4: serial@4806e000 {
 400                         compatible = "ti,omap4-uart";
 401                         reg = <0x4806e000 0x100>;
 402                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 403                         ti,hwmods = "uart4";
 404                         clock-frequency = <48000000>;
 405                 };
 406
 407                 hwspinlock: spinlock@4a0f6000 {
 408                         compatible = "ti,omap4-hwspinlock";
 409                         reg = <0x4a0f6000 0x1000>;
 410                         ti,hwmods = "spinlock";
 411                         #hwlock-cells = <1>;
 412                 };
 413
 414                 i2c1: i2c@48070000 {
 415                         compatible = "ti,omap4-i2c";
 416                         reg = <0x48070000 0x100>;
 417                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         ti,hwmods = "i2c1";
 421                 };
 422
 423                 i2c2: i2c@48072000 {
 424                         compatible = "ti,omap4-i2c";
 425                         reg = <0x48072000 0x100>;
 426                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         ti,hwmods = "i2c2";
 430                 };
 431
 432                 i2c3: i2c@48060000 {
 433                         compatible = "ti,omap4-i2c";
 434                         reg = <0x48060000 0x100>;
 435                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         ti,hwmods = "i2c3";
 439                 };
 440
 441                 i2c4: i2c@48350000 {
 442                         compatible = "ti,omap4-i2c";
 443                         reg = <0x48350000 0x100>;
 444                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         ti,hwmods = "i2c4";
 448                 };
 449
 450                 mcspi1: spi@48098000 {
 451                         compatible = "ti,omap4-mcspi";
 452                         reg = <0x48098000 0x200>;
 453                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                         ti,hwmods = "mcspi1";
 457                         ti,spi-num-cs = <4>;
 458                         dmas = <&sdma 35>,
 459                                <&sdma 36>,
 460                                <&sdma 37>,
 461                                <&sdma 38>,
 462                                <&sdma 39>,
 463                                <&sdma 40>,
 464                                <&sdma 41>,
 465                                <&sdma 42>;
 466                         dma-names = "tx0", "rx0", "tx1", "rx1",
 467                                     "tx2", "rx2", "tx3", "rx3";
 468                 };
 469
 470                 mcspi2: spi@4809a000 {
 471                         compatible = "ti,omap4-mcspi";
 472                         reg = <0x4809a000 0x200>;
 473                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         ti,hwmods = "mcspi2";
 477                         ti,spi-num-cs = <2>;
 478                         dmas = <&sdma 43>,
 479                                <&sdma 44>,
 480                                <&sdma 45>,
 481                                <&sdma 46>;
 482                         dma-names = "tx0", "rx0", "tx1", "rx1";
 483                 };
 484
 485                 mcspi3: spi@480b8000 {
 486                         compatible = "ti,omap4-mcspi";
 487                         reg = <0x480b8000 0x200>;
 488                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 489                         #address-cells = <1>;
 490                         #size-cells = <0>;
 491                         ti,hwmods = "mcspi3";
 492                         ti,spi-num-cs = <2>;
 493                         dmas = <&sdma 15>, <&sdma 16>;
 494                         dma-names = "tx0", "rx0";
 495                 };
 496
 497                 mcspi4: spi@480ba000 {
 498                         compatible = "ti,omap4-mcspi";
 499                         reg = <0x480ba000 0x200>;
 500                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 501                         #address-cells = <1>;
 502                         #size-cells = <0>;
 503                         ti,hwmods = "mcspi4";
 504                         ti,spi-num-cs = <1>;
 505                         dmas = <&sdma 70>, <&sdma 71>;
 506                         dma-names = "tx0", "rx0";
 507                 };
 508
 509                 mmc1: mmc@4809c000 {
 510                         compatible = "ti,omap4-hsmmc";
 511                         reg = <0x4809c000 0x400>;
 512                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 513                         ti,hwmods = "mmc1";
 514                         ti,dual-volt;
 515                         ti,needs-special-reset;
 516                         dmas = <&sdma 61>, <&sdma 62>;
 517                         dma-names = "tx", "rx";
 518                         pbias-supply = <&pbias_mmc_reg>;
 519                 };
 520
 521                 mmc2: mmc@480b4000 {
 522                         compatible = "ti,omap4-hsmmc";
 523                         reg = <0x480b4000 0x400>;
 524                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 525                         ti,hwmods = "mmc2";
 526                         ti,needs-special-reset;
 527                         dmas = <&sdma 47>, <&sdma 48>;
 528                         dma-names = "tx", "rx";
 529                 };
 530
 531                 mmc3: mmc@480ad000 {
 532                         compatible = "ti,omap4-hsmmc";
 533                         reg = <0x480ad000 0x400>;
 534                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 535                         ti,hwmods = "mmc3";
 536                         ti,needs-special-reset;
 537                         dmas = <&sdma 77>, <&sdma 78>;
 538                         dma-names = "tx", "rx";
 539                 };
 540
 541                 mmc4: mmc@480d1000 {
 542                         compatible = "ti,omap4-hsmmc";
 543                         reg = <0x480d1000 0x400>;
 544                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 545                         ti,hwmods = "mmc4";
 546                         ti,needs-special-reset;
 547                         dmas = <&sdma 57>, <&sdma 58>;
 548                         dma-names = "tx", "rx";
 549                 };
 550
 551                 mmc5: mmc@480d5000 {
 552                         compatible = "ti,omap4-hsmmc";
 553                         reg = <0x480d5000 0x400>;
 554                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 555                         ti,hwmods = "mmc5";
 556                         ti,needs-special-reset;
 557                         dmas = <&sdma 59>, <&sdma 60>;
 558                         dma-names = "tx", "rx";
 559                 };
 560
 561                 mmu_dsp: mmu@4a066000 {
 562                         compatible = "ti,omap4-iommu";
 563                         reg = <0x4a066000 0x100>;
 564                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 565                         ti,hwmods = "mmu_dsp";
 566                         #iommu-cells = <0>;
 567                 };
 568
 569                 mmu_ipu: mmu@55082000 {
 570                         compatible = "ti,omap4-iommu";
 571                         reg = <0x55082000 0x100>;
 572                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 573                         ti,hwmods = "mmu_ipu";
 574                         #iommu-cells = <0>;
 575                         ti,iommu-bus-err-back;
 576                 };
 577
 578                 wdt2: wdt@4a314000 {
 579                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
 580                         reg = <0x4a314000 0x80>;
 581                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 582                         ti,hwmods = "wd_timer2";
 583                 };
 584
 585                 mcpdm: mcpdm@40132000 {
 586                         compatible = "ti,omap4-mcpdm";
 587                         reg = <0x40132000 0x7f>, /* MPU private access */
 588                               <0x49032000 0x7f>; /* L3 Interconnect */
 589                         reg-names = "mpu", "dma";
 590                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 591                         ti,hwmods = "mcpdm";
 592                         dmas = <&sdma 65>,
 593                                <&sdma 66>;
 594                         dma-names = "up_link", "dn_link";
 595                         status = "disabled";
 596                 };
 597
 598                 dmic: dmic@4012e000 {
 599                         compatible = "ti,omap4-dmic";
 600                         reg = <0x4012e000 0x7f>, /* MPU private access */
 601                               <0x4902e000 0x7f>; /* L3 Interconnect */
 602                         reg-names = "mpu", "dma";
 603                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 604                         ti,hwmods = "dmic";
 605                         dmas = <&sdma 67>;
 606                         dma-names = "up_link";
 607                         status = "disabled";
 608                 };
 609
 610                 mcbsp1: mcbsp@40122000 {
 611                         compatible = "ti,omap4-mcbsp";
 612                         reg = <0x40122000 0xff>, /* MPU private access */
 613                               <0x49022000 0xff>; /* L3 Interconnect */
 614                         reg-names = "mpu", "dma";
 615                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 616                         interrupt-names = "common";
 617                         ti,buffer-size = <128>;
 618                         ti,hwmods = "mcbsp1";
 619                         dmas = <&sdma 33>,
 620                                <&sdma 34>;
 621                         dma-names = "tx", "rx";
 622                         status = "disabled";
 623                 };
 624
 625                 mcbsp2: mcbsp@40124000 {
 626                         compatible = "ti,omap4-mcbsp";
 627                         reg = <0x40124000 0xff>, /* MPU private access */
 628                               <0x49024000 0xff>; /* L3 Interconnect */
 629                         reg-names = "mpu", "dma";
 630                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 631                         interrupt-names = "common";
 632                         ti,buffer-size = <128>;
 633                         ti,hwmods = "mcbsp2";
 634                         dmas = <&sdma 17>,
 635                                <&sdma 18>;
 636                         dma-names = "tx", "rx";
 637                         status = "disabled";
 638                 };
 639
 640                 mcbsp3: mcbsp@40126000 {
 641                         compatible = "ti,omap4-mcbsp";
 642                         reg = <0x40126000 0xff>, /* MPU private access */
 643                               <0x49026000 0xff>; /* L3 Interconnect */
 644                         reg-names = "mpu", "dma";
 645                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 646                         interrupt-names = "common";
 647                         ti,buffer-size = <128>;
 648                         ti,hwmods = "mcbsp3";
 649                         dmas = <&sdma 19>,
 650                                <&sdma 20>;
 651                         dma-names = "tx", "rx";
 652                         status = "disabled";
 653                 };
 654
 655                 mcbsp4: mcbsp@48096000 {
 656                         compatible = "ti,omap4-mcbsp";
 657                         reg = <0x48096000 0xff>; /* L4 Interconnect */
 658                         reg-names = "mpu";
 659                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 660                         interrupt-names = "common";
 661                         ti,buffer-size = <128>;
 662                         ti,hwmods = "mcbsp4";
 663                         dmas = <&sdma 31>,
 664                                <&sdma 32>;
 665                         dma-names = "tx", "rx";
 666                         status = "disabled";
 667                 };
 668
 669                 keypad: keypad@4a31c000 {
 670                         compatible = "ti,omap4-keypad";
 671                         reg = <0x4a31c000 0x80>;
 672                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 673                         reg-names = "mpu";
 674                         ti,hwmods = "kbd";
 675                 };
 676
 677                 dmm@4e000000 {
 678                         compatible = "ti,omap4-dmm";
 679                         reg = <0x4e000000 0x800>;
 680                         interrupts = <0 113 0x4>;
 681                         ti,hwmods = "dmm";
 682                 };
 683
 684                 emif1: emif@4c000000 {
 685                         compatible = "ti,emif-4d";
 686                         reg = <0x4c000000 0x100>;
 687                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 688                         ti,hwmods = "emif1";
 689                         ti,no-idle-on-init;
 690                         phy-type = <1>;
 691                         hw-caps-read-idle-ctrl;
 692                         hw-caps-ll-interface;
 693                         hw-caps-temp-alert;
 694                 };
 695
 696                 emif2: emif@4d000000 {
 697                         compatible = "ti,emif-4d";
 698                         reg = <0x4d000000 0x100>;
 699                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 700                         ti,hwmods = "emif2";
 701                         ti,no-idle-on-init;
 702                         phy-type = <1>;
 703                         hw-caps-read-idle-ctrl;
 704                         hw-caps-ll-interface;
 705                         hw-caps-temp-alert;
 706                 };
 707
 708                 ocp2scp@4a0ad000 {
 709                         compatible = "ti,omap-ocp2scp";
 710                         reg = <0x4a0ad000 0x1f>;
 711                         #address-cells = <1>;
 712                         #size-cells = <1>;
 713                         ranges;
 714                         ti,hwmods = "ocp2scp_usb_phy";
 715                         usb2_phy: usb2phy@4a0ad080 {
 716                                 compatible = "ti,omap-usb2";
 717                                 reg = <0x4a0ad080 0x58>;
 718                                 ctrl-module = <&omap_control_usb2phy>;
 719                                 clocks = <&usb_phy_cm_clk32k>;
 720                                 clock-names = "wkupclk";
 721                                 #phy-cells = <0>;
 722                         };
 723                 };
 724
 725                 mailbox: mailbox@4a0f4000 {
 726                         compatible = "ti,omap4-mailbox";
 727                         reg = <0x4a0f4000 0x200>;
 728                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 729                         ti,hwmods = "mailbox";
 730                         #mbox-cells = <1>;
 731                         ti,mbox-num-users = <3>;
 732                         ti,mbox-num-fifos = <8>;
 733                         mbox_ipu: mbox_ipu {
 734                                 ti,mbox-tx = <0 0 0>;
 735                                 ti,mbox-rx = <1 0 0>;
 736                         };
 737                         mbox_dsp: mbox_dsp {
 738                                 ti,mbox-tx = <3 0 0>;
 739                                 ti,mbox-rx = <2 0 0>;
 740                         };
 741                 };
 742
 743                 timer1: timer@4a318000 {
 744                         compatible = "ti,omap3430-timer";
 745                         reg = <0x4a318000 0x80>;
 746                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 747                         ti,hwmods = "timer1";
 748                         ti,timer-alwon;
 749                 };
 750
 751                 timer2: timer@48032000 {
 752                         compatible = "ti,omap3430-timer";
 753                         reg = <0x48032000 0x80>;
 754                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 755                         ti,hwmods = "timer2";
 756                 };
 757
 758                 timer3: timer@48034000 {
 759                         compatible = "ti,omap4430-timer";
 760                         reg = <0x48034000 0x80>;
 761                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 762                         ti,hwmods = "timer3";
 763                 };
 764
 765                 timer4: timer@48036000 {
 766                         compatible = "ti,omap4430-timer";
 767                         reg = <0x48036000 0x80>;
 768                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 769                         ti,hwmods = "timer4";
 770                 };
 771
 772                 timer5: timer@40138000 {
 773                         compatible = "ti,omap4430-timer";
 774                         reg = <0x40138000 0x80>,
 775                               <0x49038000 0x80>;
 776                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 777                         ti,hwmods = "timer5";
 778                         ti,timer-dsp;
 779                 };
 780
 781                 timer6: timer@4013a000 {
 782                         compatible = "ti,omap4430-timer";
 783                         reg = <0x4013a000 0x80>,
 784                               <0x4903a000 0x80>;
 785                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 786                         ti,hwmods = "timer6";
 787                         ti,timer-dsp;
 788                 };
 789
 790                 timer7: timer@4013c000 {
 791                         compatible = "ti,omap4430-timer";
 792                         reg = <0x4013c000 0x80>,
 793                               <0x4903c000 0x80>;
 794                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 795                         ti,hwmods = "timer7";
 796                         ti,timer-dsp;
 797                 };
 798
 799                 timer8: timer@4013e000 {
 800                         compatible = "ti,omap4430-timer";
 801                         reg = <0x4013e000 0x80>,
 802                               <0x4903e000 0x80>;
 803                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 804                         ti,hwmods = "timer8";
 805                         ti,timer-pwm;
 806                         ti,timer-dsp;
 807                 };
 808
 809                 timer9: timer@4803e000 {
 810                         compatible = "ti,omap4430-timer";
 811                         reg = <0x4803e000 0x80>;
 812                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 813                         ti,hwmods = "timer9";
 814                         ti,timer-pwm;
 815                 };
 816
 817                 timer10: timer@48086000 {
 818                         compatible = "ti,omap3430-timer";
 819                         reg = <0x48086000 0x80>;
 820                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 821                         ti,hwmods = "timer10";
 822                         ti,timer-pwm;
 823                 };
 824
 825                 timer11: timer@48088000 {
 826                         compatible = "ti,omap4430-timer";
 827                         reg = <0x48088000 0x80>;
 828                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 829                         ti,hwmods = "timer11";
 830                         ti,timer-pwm;
 831                 };
 832
 833                 usbhstll: usbhstll@4a062000 {
 834                         compatible = "ti,usbhs-tll";
 835                         reg = <0x4a062000 0x1000>;
 836                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 837                         ti,hwmods = "usb_tll_hs";
 838                 };
 839
 840                 usbhshost: usbhshost@4a064000 {
 841                         compatible = "ti,usbhs-host";
 842                         reg = <0x4a064000 0x800>;
 843                         ti,hwmods = "usb_host_hs";
 844                         #address-cells = <1>;
 845                         #size-cells = <1>;
 846                         ranges;
 847                         clocks = <&init_60m_fclk>,
 848                                  <&xclk60mhsp1_ck>,
 849                                  <&xclk60mhsp2_ck>;
 850                         clock-names = "refclk_60m_int",
 851                                       "refclk_60m_ext_p1",
 852                                       "refclk_60m_ext_p2";
 853
 854                         usbhsohci: ohci@4a064800 {
 855                                 compatible = "ti,ohci-omap3";
 856                                 reg = <0x4a064800 0x400>;
 857                                 interrupt-parent = <&gic>;
 858                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 859                         };
 860
 861                         usbhsehci: ehci@4a064c00 {
 862                                 compatible = "ti,ehci-omap";
 863                                 reg = <0x4a064c00 0x400>;
 864                                 interrupt-parent = <&gic>;
 865                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 866                         };
 867                 };
 868
 869                 omap_control_usb2phy: control-phy@4a002300 {
 870                         compatible = "ti,control-phy-usb2";
 871                         reg = <0x4a002300 0x4>;
 872                         reg-names = "power";
 873                 };
 874
 875                 omap_control_usbotg: control-phy@4a00233c {
 876                         compatible = "ti,control-phy-otghs";
 877                         reg = <0x4a00233c 0x4>;
 878                         reg-names = "otghs_control";
 879                 };
 880
 881                 usb_otg_hs: usb_otg_hs@4a0ab000 {
 882                         compatible = "ti,omap4-musb";
 883                         reg = <0x4a0ab000 0x7ff>;
 884                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 885                         interrupt-names = "mc", "dma";
 886                         ti,hwmods = "usb_otg_hs";
 887                         usb-phy = <&usb2_phy>;
 888                         phys = <&usb2_phy>;
 889                         phy-names = "usb2-phy";
 890                         multipoint = <1>;
 891                         num-eps = <16>;
 892                         ram-bits = <12>;
 893                         ctrl-module = <&omap_control_usbotg>;
 894                 };
 895
 896                 aes: aes@4b501000 {
 897                         compatible = "ti,omap4-aes";
 898                         ti,hwmods = "aes";
 899                         reg = <0x4b501000 0xa0>;
 900                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 901                         dmas = <&sdma 111>, <&sdma 110>;
 902                         dma-names = "tx", "rx";
 903                 };
 904
 905                 des: des@480a5000 {
 906                         compatible = "ti,omap4-des";
 907                         ti,hwmods = "des";
 908                         reg = <0x480a5000 0xa0>;
 909                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 910                         dmas = <&sdma 117>, <&sdma 116>;
 911                         dma-names = "tx", "rx";
 912                 };
 913
 914                 abb_mpu: regulator-abb-mpu {
 915                         compatible = "ti,abb-v2";
 916                         regulator-name = "abb_mpu";
 917                         #address-cells = <0>;
 918                         #size-cells = <0>;
 919                         ti,tranxdone-status-mask = <0x80>;
 920                         clocks = <&sys_clkin_ck>;
 921                         ti,settling-time = <50>;
 922                         ti,clock-cycles = <16>;
 923
 924                         status = "disabled";
 925                 };
 926
 927                 abb_iva: regulator-abb-iva {
 928                         compatible = "ti,abb-v2";
 929                         regulator-name = "abb_iva";
 930                         #address-cells = <0>;
 931                         #size-cells = <0>;
 932                         ti,tranxdone-status-mask = <0x80000000>;
 933                         clocks = <&sys_clkin_ck>;
 934                         ti,settling-time = <50>;
 935                         ti,clock-cycles = <16>;
 936
 937                         status = "disabled";
 938                 };
 939
 940                 dss: dss@58000000 {
 941                         compatible = "ti,omap4-dss";
 942                         reg = <0x58000000 0x80>;
 943                         status = "disabled";
 944                         ti,hwmods = "dss_core";
 945                         clocks = <&dss_dss_clk>;
 946                         clock-names = "fck";
 947                         #address-cells = <1>;
 948                         #size-cells = <1>;
 949                         ranges;
 950
 951                         dispc@58001000 {
 952                                 compatible = "ti,omap4-dispc";
 953                                 reg = <0x58001000 0x1000>;
 954                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 955                                 ti,hwmods = "dss_dispc";
 956                                 clocks = <&dss_dss_clk>;
 957                                 clock-names = "fck";
 958                         };
 959
 960                         rfbi: encoder@58002000  {
 961                                 compatible = "ti,omap4-rfbi";
 962                                 reg = <0x58002000 0x1000>;
 963                                 status = "disabled";
 964                                 ti,hwmods = "dss_rfbi";
 965                                 clocks = <&dss_dss_clk>, <&l3_div_ck>;
 966                                 clock-names = "fck", "ick";
 967                         };
 968
 969                         venc: encoder@58003000 {
 970                                 compatible = "ti,omap4-venc";
 971                                 reg = <0x58003000 0x1000>;
 972                                 status = "disabled";
 973                                 ti,hwmods = "dss_venc";
 974                                 clocks = <&dss_tv_clk>;
 975                                 clock-names = "fck";
 976                         };
 977
 978                         dsi1: encoder@58004000 {
 979                                 compatible = "ti,omap4-dsi";
 980                                 reg = <0x58004000 0x200>,
 981                                       <0x58004200 0x40>,
 982                                       <0x58004300 0x20>;
 983                                 reg-names = "proto", "phy", "pll";
 984                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 985                                 status = "disabled";
 986                                 ti,hwmods = "dss_dsi1";
 987                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 988                                 clock-names = "fck", "sys_clk";
 989                         };
 990
 991                         dsi2: encoder@58005000 {
 992                                 compatible = "ti,omap4-dsi";
 993                                 reg = <0x58005000 0x200>,
 994                                       <0x58005200 0x40>,
 995                                       <0x58005300 0x20>;
 996                                 reg-names = "proto", "phy", "pll";
 997                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 998                                 status = "disabled";
 999                                 ti,hwmods = "dss_dsi2";
1000                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1001                                 clock-names = "fck", "sys_clk";
1002                         };
1003
1004                         hdmi: encoder@58006000 {
1005                                 compatible = "ti,omap4-hdmi";
1006                                 reg = <0x58006000 0x200>,
1007                                       <0x58006200 0x100>,
1008                                       <0x58006300 0x100>,
1009                                       <0x58006400 0x1000>;
1010                                 reg-names = "wp", "pll", "phy", "core";
1011                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1012                                 status = "disabled";
1013                                 ti,hwmods = "dss_hdmi";
1014                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1015                                 clock-names = "fck", "sys_clk";
1016                                 dmas = <&sdma 76>;
1017                                 dma-names = "audio_tx";
1018                         };
1019                 };
1020         };
1021 };
1022
1023 /include/ "omap44xx-clocks.dtsi"