arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,rpmcc.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 / {
  12         model = "Qualcomm APQ8064";
  13         compatible = "qcom,apq8064";
  14         interrupt-parent = <&intc>;
  15
  16         reserved-memory {
  17                 #address-cells = <1>;
  18                 #size-cells = <1>;
  19                 ranges;
  20
  21                 smem_region: smem@80000000 {
  22                         reg = <0x80000000 0x200000>;
  23                         no-map;
  24                 };
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         compatible = "qcom,krait";
  33                         enable-method = "qcom,kpss-acc-v1";
  34                         device_type = "cpu";
  35                         reg = <0>;
  36                         next-level-cache = <&L2>;
  37                         qcom,acc = <&acc0>;
  38                         qcom,saw = <&saw0>;
  39                         cpu-idle-states = <&CPU_SPC>;
  40                 };
  41
  42                 cpu@1 {
  43                         compatible = "qcom,krait";
  44                         enable-method = "qcom,kpss-acc-v1";
  45                         device_type = "cpu";
  46                         reg = <1>;
  47                         next-level-cache = <&L2>;
  48                         qcom,acc = <&acc1>;
  49                         qcom,saw = <&saw1>;
  50                         cpu-idle-states = <&CPU_SPC>;
  51                 };
  52
  53                 cpu@2 {
  54                         compatible = "qcom,krait";
  55                         enable-method = "qcom,kpss-acc-v1";
  56                         device_type = "cpu";
  57                         reg = <2>;
  58                         next-level-cache = <&L2>;
  59                         qcom,acc = <&acc2>;
  60                         qcom,saw = <&saw2>;
  61                         cpu-idle-states = <&CPU_SPC>;
  62                 };
  63
  64                 cpu@3 {
  65                         compatible = "qcom,krait";
  66                         enable-method = "qcom,kpss-acc-v1";
  67                         device_type = "cpu";
  68                         reg = <3>;
  69                         next-level-cache = <&L2>;
  70                         qcom,acc = <&acc3>;
  71                         qcom,saw = <&saw3>;
  72                         cpu-idle-states = <&CPU_SPC>;
  73                 };
  74
  75                 L2: l2-cache {
  76                         compatible = "cache";
  77                         cache-level = <2>;
  78                 };
  79
  80                 idle-states {
  81                         CPU_SPC: spc {
  82                                 compatible = "qcom,idle-state-spc",
  83                                                 "arm,idle-state";
  84                                 entry-latency-us = <400>;
  85                                 exit-latency-us = <900>;
  86                                 min-residency-us = <3000>;
  87                         };
  88                 };
  89         };
  90
  91         thermal-zones {
  92                 cpu-thermal0 {
  93                         polling-delay-passive = <250>;
  94                         polling-delay = <1000>;
  95
  96                         thermal-sensors = <&gcc 7>;
  97                         coefficients = <1199 0>;
  98
  99                         trips {
 100                                 cpu_alert0: trip0 {
 101                                         temperature = <75000>;
 102                                         hysteresis = <2000>;
 103                                         type = "passive";
 104                                 };
 105                                 cpu_crit0: trip1 {
 106                                         temperature = <110000>;
 107                                         hysteresis = <2000>;
 108                                         type = "critical";
 109                                 };
 110                         };
 111                 };
 112
 113                 cpu-thermal1 {
 114                         polling-delay-passive = <250>;
 115                         polling-delay = <1000>;
 116
 117                         thermal-sensors = <&gcc 8>;
 118                         coefficients = <1132 0>;
 119
 120                         trips {
 121                                 cpu_alert1: trip0 {
 122                                         temperature = <75000>;
 123                                         hysteresis = <2000>;
 124                                         type = "passive";
 125                                 };
 126                                 cpu_crit1: trip1 {
 127                                         temperature = <110000>;
 128                                         hysteresis = <2000>;
 129                                         type = "critical";
 130                                 };
 131                         };
 132                 };
 133
 134                 cpu-thermal2 {
 135                         polling-delay-passive = <250>;
 136                         polling-delay = <1000>;
 137
 138                         thermal-sensors = <&gcc 9>;
 139                         coefficients = <1199 0>;
 140
 141                         trips {
 142                                 cpu_alert2: trip0 {
 143                                         temperature = <75000>;
 144                                         hysteresis = <2000>;
 145                                         type = "passive";
 146                                 };
 147                                 cpu_crit2: trip1 {
 148                                         temperature = <110000>;
 149                                         hysteresis = <2000>;
 150                                         type = "critical";
 151                                 };
 152                         };
 153                 };
 154
 155                 cpu-thermal3 {
 156                         polling-delay-passive = <250>;
 157                         polling-delay = <1000>;
 158
 159                         thermal-sensors = <&gcc 10>;
 160                         coefficients = <1132 0>;
 161
 162                         trips {
 163                                 cpu_alert3: trip0 {
 164                                         temperature = <75000>;
 165                                         hysteresis = <2000>;
 166                                         type = "passive";
 167                                 };
 168                                 cpu_crit3: trip1 {
 169                                         temperature = <110000>;
 170                                         hysteresis = <2000>;
 171                                         type = "critical";
 172                                 };
 173                         };
 174                 };
 175         };
 176
 177         cpu-pmu {
 178                 compatible = "qcom,krait-pmu";
 179                 interrupts = <1 10 0x304>;
 180         };
 181
 182         clocks {
 183                 cxo_board {
 184                         compatible = "fixed-clock";
 185                         #clock-cells = <0>;
 186                         clock-frequency = <19200000>;
 187                 };
 188
 189                 pxo_board {
 190                         compatible = "fixed-clock";
 191                         #clock-cells = <0>;
 192                         clock-frequency = <27000000>;
 193                 };
 194
 195                 sleep_clk {
 196                         compatible = "fixed-clock";
 197                         #clock-cells = <0>;
 198                         clock-frequency = <32768>;
 199                 };
 200         };
 201
 202         sfpb_mutex: hwmutex {
 203                 compatible = "qcom,sfpb-mutex";
 204                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 205                 #hwlock-cells = <1>;
 206         };
 207
 208         smem {
 209                 compatible = "qcom,smem";
 210                 memory-region = <&smem_region>;
 211
 212                 hwlocks = <&sfpb_mutex 3>;
 213         };
 214
 215         smd {
 216                 compatible = "qcom,smd";
 217
 218                 modem@0 {
 219                         interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
 220
 221                         qcom,ipc = <&l2cc 8 3>;
 222                         qcom,smd-edge = <0>;
 223
 224                         status = "disabled";
 225                 };
 226
 227                 q6@1 {
 228                         interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
 229
 230                         qcom,ipc = <&l2cc 8 15>;
 231                         qcom,smd-edge = <1>;
 232
 233                         status = "disabled";
 234                 };
 235
 236                 dsps@3 {
 237                         interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
 238
 239                         qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
 240                         qcom,smd-edge = <3>;
 241
 242                         status = "disabled";
 243                 };
 244
 245                 riva@6 {
 246                         interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
 247
 248                         qcom,ipc = <&l2cc 8 25>;
 249                         qcom,smd-edge = <6>;
 250
 251                         status = "disabled";
 252                 };
 253         };
 254
 255         smsm {
 256                 compatible = "qcom,smsm";
 257
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260
 261                 qcom,ipc-1 = <&l2cc 8 4>;
 262                 qcom,ipc-2 = <&l2cc 8 14>;
 263                 qcom,ipc-3 = <&l2cc 8 23>;
 264                 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
 265
 266                 apps_smsm: apps@0 {
 267                         reg = <0>;
 268                         #qcom,smem-state-cells = <1>;
 269                 };
 270
 271                 modem_smsm: modem@1 {
 272                         reg = <1>;
 273                         interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
 274
 275                         interrupt-controller;
 276                         #interrupt-cells = <2>;
 277                 };
 278
 279                 q6_smsm: q6@2 {
 280                         reg = <2>;
 281                         interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
 282
 283                         interrupt-controller;
 284                         #interrupt-cells = <2>;
 285                 };
 286
 287                 wcnss_smsm: wcnss@3 {
 288                         reg = <3>;
 289                         interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
 290
 291                         interrupt-controller;
 292                         #interrupt-cells = <2>;
 293                 };
 294
 295                 dsps_smsm: dsps@4 {
 296                         reg = <4>;
 297                         interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
 298
 299                         interrupt-controller;
 300                         #interrupt-cells = <2>;
 301                 };
 302         };
 303
 304         firmware {
 305                 scm {
 306                         compatible = "qcom,scm-apq8064";
 307
 308                         clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
 309                         clock-names = "core";
 310                 };
 311         };
 312
 313         soc: soc {
 314                 #address-cells = <1>;
 315                 #size-cells = <1>;
 316                 ranges;
 317                 compatible = "simple-bus";
 318
 319                 tlmm_pinmux: pinctrl@800000 {
 320                         compatible = "qcom,apq8064-pinctrl";
 321                         reg = <0x800000 0x4000>;
 322
 323                         gpio-controller;
 324                         #gpio-cells = <2>;
 325                         interrupt-controller;
 326                         #interrupt-cells = <2>;
 327                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 328
 329                         pinctrl-names = "default";
 330                         pinctrl-0 = <&ps_hold>;
 331                 };
 332
 333                 sfpb_wrapper_mutex: syscon@1200000 {
 334                         compatible = "syscon";
 335                         reg = <0x01200000 0x8000>;
 336                 };
 337
 338                 intc: interrupt-controller@2000000 {
 339                         compatible = "qcom,msm-qgic2";
 340                         interrupt-controller;
 341                         #interrupt-cells = <3>;
 342                         reg = <0x02000000 0x1000>,
 343                               <0x02002000 0x1000>;
 344                 };
 345
 346                 timer@200a000 {
 347                         compatible = "qcom,kpss-timer",
 348                                      "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
 349                         interrupts = <1 1 0x301>,
 350                                      <1 2 0x301>,
 351                                      <1 3 0x301>;
 352                         reg = <0x0200a000 0x100>;
 353                         clock-frequency = <27000000>,
 354                                           <32768>;
 355                         cpu-offset = <0x80000>;
 356                 };
 357
 358                 acc0: clock-controller@2088000 {
 359                         compatible = "qcom,kpss-acc-v1";
 360                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 361                 };
 362
 363                 acc1: clock-controller@2098000 {
 364                         compatible = "qcom,kpss-acc-v1";
 365                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 366                 };
 367
 368                 acc2: clock-controller@20a8000 {
 369                         compatible = "qcom,kpss-acc-v1";
 370                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 371                 };
 372
 373                 acc3: clock-controller@20b8000 {
 374                         compatible = "qcom,kpss-acc-v1";
 375                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 376                 };
 377
 378                 saw0: power-controller@2089000 {
 379                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 380                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 381                         regulator;
 382                 };
 383
 384                 saw1: power-controller@2099000 {
 385                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 386                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 387                         regulator;
 388                 };
 389
 390                 saw2: power-controller@20a9000 {
 391                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 392                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 393                         regulator;
 394                 };
 395
 396                 saw3: power-controller@20b9000 {
 397                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 398                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 399                         regulator;
 400                 };
 401
 402                 sps_sic_non_secure: sps-sic-non-secure@12100000 {
 403                         compatible      = "syscon";
 404                         reg             = <0x12100000 0x10000>;
 405                 };
 406
 407                 gsbi1: gsbi@12440000 {
 408                         status = "disabled";
 409                         compatible = "qcom,gsbi-v1.0.0";
 410                         cell-index = <1>;
 411                         reg = <0x12440000 0x100>;
 412                         clocks = <&gcc GSBI1_H_CLK>;
 413                         clock-names = "iface";
 414                         #address-cells = <1>;
 415                         #size-cells = <1>;
 416                         ranges;
 417
 418                         syscon-tcsr = <&tcsr>;
 419
 420                         gsbi1_serial: serial@12450000 {
 421                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 422                                 reg = <0x12450000 0x100>,
 423                                       <0x12400000 0x03>;
 424                                 interrupts = <0 193 0x0>;
 425                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
 426                                 clock-names = "core", "iface";
 427                                 status = "disabled";
 428                         };
 429
 430                         gsbi1_i2c: i2c@12460000 {
 431                                 compatible = "qcom,i2c-qup-v1.1.1";
 432                                 pinctrl-0 = <&i2c1_pins>;
 433                                 pinctrl-1 = <&i2c1_pins_sleep>;
 434                                 pinctrl-names = "default", "sleep";
 435                                 reg = <0x12460000 0x1000>;
 436                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 437                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 438                                 clock-names = "core", "iface";
 439                                 #address-cells = <1>;
 440                                 #size-cells = <0>;
 441                         };
 442
 443                 };
 444
 445                 gsbi2: gsbi@12480000 {
 446                         status = "disabled";
 447                         compatible = "qcom,gsbi-v1.0.0";
 448                         cell-index = <2>;
 449                         reg = <0x12480000 0x100>;
 450                         clocks = <&gcc GSBI2_H_CLK>;
 451                         clock-names = "iface";
 452                         #address-cells = <1>;
 453                         #size-cells = <1>;
 454                         ranges;
 455
 456                         syscon-tcsr = <&tcsr>;
 457
 458                         gsbi2_i2c: i2c@124a0000 {
 459                                 compatible = "qcom,i2c-qup-v1.1.1";
 460                                 reg = <0x124a0000 0x1000>;
 461                                 pinctrl-0 = <&i2c2_pins>;
 462                                 pinctrl-1 = <&i2c2_pins_sleep>;
 463                                 pinctrl-names = "default", "sleep";
 464                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 465                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 466                                 clock-names = "core", "iface";
 467                                 #address-cells = <1>;
 468                                 #size-cells = <0>;
 469                         };
 470                 };
 471
 472                 gsbi3: gsbi@16200000 {
 473                         status = "disabled";
 474                         compatible = "qcom,gsbi-v1.0.0";
 475                         cell-index = <3>;
 476                         reg = <0x16200000 0x100>;
 477                         clocks = <&gcc GSBI3_H_CLK>;
 478                         clock-names = "iface";
 479                         #address-cells = <1>;
 480                         #size-cells = <1>;
 481                         ranges;
 482                         gsbi3_i2c: i2c@16280000 {
 483                                 compatible = "qcom,i2c-qup-v1.1.1";
 484                                 pinctrl-0 = <&i2c3_pins>;
 485                                 pinctrl-1 = <&i2c3_pins_sleep>;
 486                                 pinctrl-names = "default", "sleep";
 487                                 reg = <0x16280000 0x1000>;
 488                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 489                                 clocks = <&gcc GSBI3_QUP_CLK>,
 490                                          <&gcc GSBI3_H_CLK>;
 491                                 clock-names = "core", "iface";
 492                                 #address-cells = <1>;
 493                                 #size-cells = <0>;
 494                         };
 495                 };
 496
 497                 gsbi4: gsbi@16300000 {
 498                         status = "disabled";
 499                         compatible = "qcom,gsbi-v1.0.0";
 500                         cell-index = <4>;
 501                         reg = <0x16300000 0x03>;
 502                         clocks = <&gcc GSBI4_H_CLK>;
 503                         clock-names = "iface";
 504                         #address-cells = <1>;
 505                         #size-cells = <1>;
 506                         ranges;
 507
 508                         gsbi4_i2c: i2c@16380000 {
 509                                 compatible = "qcom,i2c-qup-v1.1.1";
 510                                 pinctrl-0 = <&i2c4_pins>;
 511                                 pinctrl-1 = <&i2c4_pins_sleep>;
 512                                 pinctrl-names = "default", "sleep";
 513                                 reg = <0x16380000 0x1000>;
 514                                 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
 515                                 clocks = <&gcc GSBI4_QUP_CLK>,
 516                                          <&gcc GSBI4_H_CLK>;
 517                                 clock-names = "core", "iface";
 518                         };
 519                 };
 520
 521                 gsbi5: gsbi@1a200000 {
 522                         status = "disabled";
 523                         compatible = "qcom,gsbi-v1.0.0";
 524                         cell-index = <5>;
 525                         reg = <0x1a200000 0x03>;
 526                         clocks = <&gcc GSBI5_H_CLK>;
 527                         clock-names = "iface";
 528                         #address-cells = <1>;
 529                         #size-cells = <1>;
 530                         ranges;
 531
 532                         gsbi5_serial: serial@1a240000 {
 533                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 534                                 reg = <0x1a240000 0x100>,
 535                                       <0x1a200000 0x03>;
 536                                 interrupts = <0 154 0x0>;
 537                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
 538                                 clock-names = "core", "iface";
 539                                 status = "disabled";
 540                         };
 541
 542                         gsbi5_spi: spi@1a280000 {
 543                                 compatible = "qcom,spi-qup-v1.1.1";
 544                                 reg = <0x1a280000 0x1000>;
 545                                 interrupts = <0 155 0>;
 546                                 pinctrl-0 = <&spi5_default>;
 547                                 pinctrl-1 = <&spi5_sleep>;
 548                                 pinctrl-names = "default", "sleep";
 549                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
 550                                 clock-names = "core", "iface";
 551                                 status = "disabled";
 552                                 #address-cells = <1>;
 553                                 #size-cells = <0>;
 554                         };
 555                 };
 556
 557                 gsbi6: gsbi@16500000 {
 558                         status = "disabled";
 559                         compatible = "qcom,gsbi-v1.0.0";
 560                         cell-index = <6>;
 561                         reg = <0x16500000 0x03>;
 562                         clocks = <&gcc GSBI6_H_CLK>;
 563                         clock-names = "iface";
 564                         #address-cells = <1>;
 565                         #size-cells = <1>;
 566                         ranges;
 567
 568                         gsbi6_serial: serial@16540000 {
 569                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 570                                 reg = <0x16540000 0x100>,
 571                                       <0x16500000 0x03>;
 572                                 interrupts = <0 156 0x0>;
 573                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 574                                 clock-names = "core", "iface";
 575                                 status = "disabled";
 576                         };
 577
 578                         gsbi6_i2c: i2c@16580000 {
 579                                 compatible = "qcom,i2c-qup-v1.1.1";
 580                                 pinctrl-0 = <&i2c6_pins>;
 581                                 pinctrl-1 = <&i2c6_pins_sleep>;
 582                                 pinctrl-names = "default", "sleep";
 583                                 reg = <0x16580000 0x1000>;
 584                                 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
 585                                 clocks = <&gcc GSBI6_QUP_CLK>,
 586                                          <&gcc GSBI6_H_CLK>;
 587                                 clock-names = "core", "iface";
 588                         };
 589                 };
 590
 591                 gsbi7: gsbi@16600000 {
 592                         status = "disabled";
 593                         compatible = "qcom,gsbi-v1.0.0";
 594                         cell-index = <7>;
 595                         reg = <0x16600000 0x100>;
 596                         clocks = <&gcc GSBI7_H_CLK>;
 597                         clock-names = "iface";
 598                         #address-cells = <1>;
 599                         #size-cells = <1>;
 600                         ranges;
 601                         syscon-tcsr = <&tcsr>;
 602
 603                         gsbi7_serial: serial@16640000 {
 604                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 605                                 reg = <0x16640000 0x1000>,
 606                                       <0x16600000 0x1000>;
 607                                 interrupts = <0 158 0x0>;
 608                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 609                                 clock-names = "core", "iface";
 610                                 status = "disabled";
 611                         };
 612
 613                         gsbi7_i2c: i2c@16680000 {
 614                                 compatible = "qcom,i2c-qup-v1.1.1";
 615                                 pinctrl-0 = <&i2c7_pins>;
 616                                 pinctrl-1 = <&i2c7_pins_sleep>;
 617                                 pinctrl-names = "default", "sleep";
 618                                 reg = <0x16680000 0x1000>;
 619                                 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
 620                                 clocks = <&gcc GSBI7_QUP_CLK>,
 621                                          <&gcc GSBI7_H_CLK>;
 622                                 clock-names = "core", "iface";
 623                                 status = "disabled";
 624                         };
 625                 };
 626
 627                 rng@1a500000 {
 628                         compatible = "qcom,prng";
 629                         reg = <0x1a500000 0x200>;
 630                         clocks = <&gcc PRNG_CLK>;
 631                         clock-names = "core";
 632                 };
 633
 634                 qcom,ssbi@500000 {
 635                         compatible = "qcom,ssbi";
 636                         reg = <0x00500000 0x1000>;
 637                         qcom,controller-type = "pmic-arbiter";
 638
 639                         pmicintc: pmic@0 {
 640                                 compatible = "qcom,pm8921";
 641                                 interrupt-parent = <&tlmm_pinmux>;
 642                                 interrupts = <74 8>;
 643                                 #interrupt-cells = <2>;
 644                                 interrupt-controller;
 645                                 #address-cells = <1>;
 646                                 #size-cells = <0>;
 647
 648                                 pm8921_gpio: gpio@150 {
 649
 650                                         compatible = "qcom,pm8921-gpio",
 651                                                      "qcom,ssbi-gpio";
 652                                         reg = <0x150>;
 653                                         interrupts = <192 IRQ_TYPE_NONE>,
 654                                                      <193 IRQ_TYPE_NONE>,
 655                                                      <194 IRQ_TYPE_NONE>,
 656                                                      <195 IRQ_TYPE_NONE>,
 657                                                      <196 IRQ_TYPE_NONE>,
 658                                                      <197 IRQ_TYPE_NONE>,
 659                                                      <198 IRQ_TYPE_NONE>,
 660                                                      <199 IRQ_TYPE_NONE>,
 661                                                      <200 IRQ_TYPE_NONE>,
 662                                                      <201 IRQ_TYPE_NONE>,
 663                                                      <202 IRQ_TYPE_NONE>,
 664                                                      <203 IRQ_TYPE_NONE>,
 665                                                      <204 IRQ_TYPE_NONE>,
 666                                                      <205 IRQ_TYPE_NONE>,
 667                                                      <206 IRQ_TYPE_NONE>,
 668                                                      <207 IRQ_TYPE_NONE>,
 669                                                      <208 IRQ_TYPE_NONE>,
 670                                                      <209 IRQ_TYPE_NONE>,
 671                                                      <210 IRQ_TYPE_NONE>,
 672                                                      <211 IRQ_TYPE_NONE>,
 673                                                      <212 IRQ_TYPE_NONE>,
 674                                                      <213 IRQ_TYPE_NONE>,
 675                                                      <214 IRQ_TYPE_NONE>,
 676                                                      <215 IRQ_TYPE_NONE>,
 677                                                      <216 IRQ_TYPE_NONE>,
 678                                                      <217 IRQ_TYPE_NONE>,
 679                                                      <218 IRQ_TYPE_NONE>,
 680                                                      <219 IRQ_TYPE_NONE>,
 681                                                      <220 IRQ_TYPE_NONE>,
 682                                                      <221 IRQ_TYPE_NONE>,
 683                                                      <222 IRQ_TYPE_NONE>,
 684                                                      <223 IRQ_TYPE_NONE>,
 685                                                      <224 IRQ_TYPE_NONE>,
 686                                                      <225 IRQ_TYPE_NONE>,
 687                                                      <226 IRQ_TYPE_NONE>,
 688                                                      <227 IRQ_TYPE_NONE>,
 689                                                      <228 IRQ_TYPE_NONE>,
 690                                                      <229 IRQ_TYPE_NONE>,
 691                                                      <230 IRQ_TYPE_NONE>,
 692                                                      <231 IRQ_TYPE_NONE>,
 693                                                      <232 IRQ_TYPE_NONE>,
 694                                                      <233 IRQ_TYPE_NONE>,
 695                                                      <234 IRQ_TYPE_NONE>,
 696                                                      <235 IRQ_TYPE_NONE>;
 697                                         gpio-controller;
 698                                         #gpio-cells = <2>;
 699
 700                                 };
 701
 702                                 pm8921_mpps: mpps@50 {
 703                                         compatible = "qcom,pm8921-mpp",
 704                                                      "qcom,ssbi-mpp";
 705                                         reg = <0x50>;
 706                                         gpio-controller;
 707                                         #gpio-cells = <2>;
 708                                         interrupts =
 709                                         <128 IRQ_TYPE_NONE>,
 710                                         <129 IRQ_TYPE_NONE>,
 711                                         <130 IRQ_TYPE_NONE>,
 712                                         <131 IRQ_TYPE_NONE>,
 713                                         <132 IRQ_TYPE_NONE>,
 714                                         <133 IRQ_TYPE_NONE>,
 715                                         <134 IRQ_TYPE_NONE>,
 716                                         <135 IRQ_TYPE_NONE>,
 717                                         <136 IRQ_TYPE_NONE>,
 718                                         <137 IRQ_TYPE_NONE>,
 719                                         <138 IRQ_TYPE_NONE>,
 720                                         <139 IRQ_TYPE_NONE>;
 721                                 };
 722
 723                                 rtc@11d {
 724                                         compatible = "qcom,pm8921-rtc";
 725                                         interrupt-parent = <&pmicintc>;
 726                                         interrupts = <39 1>;
 727                                         reg = <0x11d>;
 728                                         allow-set-time;
 729                                 };
 730
 731                                 pwrkey@1c {
 732                                         compatible = "qcom,pm8921-pwrkey";
 733                                         reg = <0x1c>;
 734                                         interrupt-parent = <&pmicintc>;
 735                                         interrupts = <50 1>, <51 1>;
 736                                         debounce = <15625>;
 737                                         pull-up;
 738                                 };
 739                         };
 740                 };
 741
 742                 qfprom: qfprom@700000 {
 743                         compatible      = "qcom,qfprom";
 744                         reg             = <0x00700000 0x1000>;
 745                         #address-cells  = <1>;
 746                         #size-cells     = <1>;
 747                         ranges;
 748                         tsens_calib: calib {
 749                                 reg = <0x404 0x10>;
 750                         };
 751                         tsens_backup: backup_calib {
 752                                 reg = <0x414 0x10>;
 753                         };
 754                 };
 755
 756                 gcc: clock-controller@900000 {
 757                         compatible = "qcom,gcc-apq8064";
 758                         reg = <0x00900000 0x4000>;
 759                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 760                         nvmem-cell-names = "calib", "calib_backup";
 761                         #clock-cells = <1>;
 762                         #reset-cells = <1>;
 763                         #thermal-sensor-cells = <1>;
 764                 };
 765
 766                 lcc: clock-controller@28000000 {
 767                         compatible = "qcom,lcc-apq8064";
 768                         reg = <0x28000000 0x1000>;
 769                         #clock-cells = <1>;
 770                         #reset-cells = <1>;
 771                 };
 772
 773                 mmcc: clock-controller@4000000 {
 774                         compatible = "qcom,mmcc-apq8064";
 775                         reg = <0x4000000 0x1000>;
 776                         #clock-cells = <1>;
 777                         #reset-cells = <1>;
 778                 };
 779
 780                 l2cc: clock-controller@2011000 {
 781                         compatible      = "syscon";
 782                         reg             = <0x2011000 0x1000>;
 783                 };
 784
 785                 rpm@108000 {
 786                         compatible      = "qcom,rpm-apq8064";
 787                         reg             = <0x108000 0x1000>;
 788                         qcom,ipc        = <&l2cc 0x8 2>;
 789
 790                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 791                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 792                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 793                         interrupt-names = "ack", "err", "wakeup";
 794
 795                         rpmcc: clock-controller {
 796                                 compatible      = "qcom,rpmcc-apq8064", "qcom,rpmcc";
 797                                 #clock-cells = <1>;
 798                         };
 799
 800                         regulators {
 801                                 compatible = "qcom,rpm-pm8921-regulators";
 802
 803                                 pm8921_s1: s1 {};
 804                                 pm8921_s2: s2 {};
 805                                 pm8921_s3: s3 {};
 806                                 pm8921_s4: s4 {};
 807                                 pm8921_s7: s7 {};
 808                                 pm8921_s8: s8 {};
 809
 810                                 pm8921_l1: l1 {};
 811                                 pm8921_l2: l2 {};
 812                                 pm8921_l3: l3 {};
 813                                 pm8921_l4: l4 {};
 814                                 pm8921_l5: l5 {};
 815                                 pm8921_l6: l6 {};
 816                                 pm8921_l7: l7 {};
 817                                 pm8921_l8: l8 {};
 818                                 pm8921_l9: l9 {};
 819                                 pm8921_l10: l10 {};
 820                                 pm8921_l11: l11 {};
 821                                 pm8921_l12: l12 {};
 822                                 pm8921_l14: l14 {};
 823                                 pm8921_l15: l15 {};
 824                                 pm8921_l16: l16 {};
 825                                 pm8921_l17: l17 {};
 826                                 pm8921_l18: l18 {};
 827                                 pm8921_l21: l21 {};
 828                                 pm8921_l22: l22 {};
 829                                 pm8921_l23: l23 {};
 830                                 pm8921_l24: l24 {};
 831                                 pm8921_l25: l25 {};
 832                                 pm8921_l26: l26 {};
 833                                 pm8921_l27: l27 {};
 834                                 pm8921_l28: l28 {};
 835                                 pm8921_l29: l29 {};
 836
 837                                 pm8921_lvs1: lvs1 {};
 838                                 pm8921_lvs2: lvs2 {};
 839                                 pm8921_lvs3: lvs3 {};
 840                                 pm8921_lvs4: lvs4 {};
 841                                 pm8921_lvs5: lvs5 {};
 842                                 pm8921_lvs6: lvs6 {};
 843                                 pm8921_lvs7: lvs7 {};
 844
 845                                 pm8921_usb_switch: usb-switch {};
 846
 847                                 pm8921_hdmi_switch: hdmi-switch {
 848                                         bias-pull-down;
 849                                 };
 850
 851                                 pm8921_ncp: ncp {};
 852                         };
 853                 };
 854
 855                 usb1_phy: phy@12500000 {
 856                         compatible      = "qcom,usb-otg-ci";
 857                         reg             = <0x12500000 0x400>;
 858                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 859                         status          = "disabled";
 860
 861                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 862                                           <&gcc USB_HS1_H_CLK>;
 863                         clock-names     = "core", "iface";
 864
 865                         resets          = <&gcc USB_HS1_RESET>;
 866                         reset-names     = "link";
 867                 };
 868
 869                 usb3_phy: phy@12520000 {
 870                         compatible      = "qcom,usb-otg-ci";
 871                         reg             = <0x12520000 0x400>;
 872                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 873                         status          = "disabled";
 874                         dr_mode         = "host";
 875
 876                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 877                                           <&gcc USB_HS3_H_CLK>;
 878                         clock-names     = "core", "iface";
 879
 880                         resets          = <&gcc USB_HS3_RESET>;
 881                         reset-names     = "link";
 882                 };
 883
 884                 usb4_phy: phy@12530000 {
 885                         compatible      = "qcom,usb-otg-ci";
 886                         reg             = <0x12530000 0x400>;
 887                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 888                         status          = "disabled";
 889                         dr_mode         = "host";
 890
 891                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 892                                           <&gcc USB_HS4_H_CLK>;
 893                         clock-names     = "core", "iface";
 894
 895                         resets          = <&gcc USB_HS4_RESET>;
 896                         reset-names     = "link";
 897                 };
 898
 899                 gadget1: gadget@12500000 {
 900                         compatible      = "qcom,ci-hdrc";
 901                         reg             = <0x12500000 0x400>;
 902                         status          = "disabled";
 903                         dr_mode         = "peripheral";
 904                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 905                         usb-phy         = <&usb1_phy>;
 906                 };
 907
 908                 usb1: usb@12500000 {
 909                         compatible      = "qcom,ehci-host";
 910                         reg             = <0x12500000 0x400>;
 911                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 912                         status          = "disabled";
 913                         usb-phy         = <&usb1_phy>;
 914                 };
 915
 916                 usb3: usb@12520000 {
 917                         compatible      = "qcom,ehci-host";
 918                         reg             = <0x12520000 0x400>;
 919                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 920                         status          = "disabled";
 921                         usb-phy         = <&usb3_phy>;
 922                 };
 923
 924                 usb4: usb@12530000 {
 925                         compatible      = "qcom,ehci-host";
 926                         reg             = <0x12530000 0x400>;
 927                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 928                         status          = "disabled";
 929                         usb-phy         = <&usb4_phy>;
 930                 };
 931
 932                 sata_phy0: phy@1b400000 {
 933                         compatible      = "qcom,apq8064-sata-phy";
 934                         status          = "disabled";
 935                         reg             = <0x1b400000 0x200>;
 936                         reg-names       = "phy_mem";
 937                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 938                         clock-names     = "cfg";
 939                         #phy-cells      = <0>;
 940                 };
 941
 942                 sata0: sata@29000000 {
 943                         compatible              = "qcom,apq8064-ahci", "generic-ahci";
 944                         status                  = "disabled";
 945                         reg                     = <0x29000000 0x180>;
 946                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 947
 948                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 949                                                 <&gcc SATA_H_CLK>,
 950                                                 <&gcc SATA_A_CLK>,
 951                                                 <&gcc SATA_RXOOB_CLK>,
 952                                                 <&gcc SATA_PMALIVE_CLK>;
 953                         clock-names             = "slave_iface",
 954                                                 "iface",
 955                                                 "bus",
 956                                                 "rxoob",
 957                                                 "core_pmalive";
 958
 959                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 960                                                 <&gcc SATA_PMALIVE_CLK>;
 961                         assigned-clock-rates    = <100000000>, <100000000>;
 962
 963                         phys                    = <&sata_phy0>;
 964                         phy-names               = "sata-phy";
 965                         ports-implemented       = <0x1>;
 966                 };
 967
 968                 /* Temporary fixed regulator */
 969                 sdcc1bam:dma@12402000{
 970                         compatible = "qcom,bam-v1.3.0";
 971                         reg = <0x12402000 0x8000>;
 972                         interrupts = <0 98 0>;
 973                         clocks = <&gcc SDC1_H_CLK>;
 974                         clock-names = "bam_clk";
 975                         #dma-cells = <1>;
 976                         qcom,ee = <0>;
 977                 };
 978
 979                 sdcc3bam:dma@12182000{
 980                         compatible = "qcom,bam-v1.3.0";
 981                         reg = <0x12182000 0x8000>;
 982                         interrupts = <0 96 0>;
 983                         clocks = <&gcc SDC3_H_CLK>;
 984                         clock-names = "bam_clk";
 985                         #dma-cells = <1>;
 986                         qcom,ee = <0>;
 987                 };
 988
 989                 sdcc4bam:dma@121c2000{
 990                         compatible = "qcom,bam-v1.3.0";
 991                         reg = <0x121c2000 0x8000>;
 992                         interrupts = <0 95 0>;
 993                         clocks = <&gcc SDC4_H_CLK>;
 994                         clock-names = "bam_clk";
 995                         #dma-cells = <1>;
 996                         qcom,ee = <0>;
 997                 };
 998
 999                 amba {
1000                         compatible = "simple-bus";
1001                         #address-cells = <1>;
1002                         #size-cells = <1>;
1003                         ranges;
1004                         sdcc1: sdcc@12400000 {
1005                                 status          = "disabled";
1006                                 compatible      = "arm,pl18x", "arm,primecell";
1007                                 pinctrl-names   = "default";
1008                                 pinctrl-0       = <&sdcc1_pins>;
1009                                 arm,primecell-periphid = <0x00051180>;
1010                                 reg             = <0x12400000 0x2000>;
1011                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1012                                 interrupt-names = "cmd_irq";
1013                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1014                                 clock-names     = "mclk", "apb_pclk";
1015                                 bus-width       = <8>;
1016                                 max-frequency   = <96000000>;
1017                                 non-removable;
1018                                 cap-sd-highspeed;
1019                                 cap-mmc-highspeed;
1020                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1021                                 dma-names = "tx", "rx";
1022                         };
1023
1024                         sdcc3: sdcc@12180000 {
1025                                 compatible      = "arm,pl18x", "arm,primecell";
1026                                 arm,primecell-periphid = <0x00051180>;
1027                                 status          = "disabled";
1028                                 reg             = <0x12180000 0x2000>;
1029                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1030                                 interrupt-names = "cmd_irq";
1031                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1032                                 clock-names     = "mclk", "apb_pclk";
1033                                 bus-width       = <4>;
1034                                 cap-sd-highspeed;
1035                                 cap-mmc-highspeed;
1036                                 max-frequency   = <192000000>;
1037                                 no-1-8-v;
1038                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1039                                 dma-names = "tx", "rx";
1040                         };
1041
1042                         sdcc4: sdcc@121c0000 {
1043                                 compatible      = "arm,pl18x", "arm,primecell";
1044                                 arm,primecell-periphid = <0x00051180>;
1045                                 status          = "disabled";
1046                                 reg             = <0x121c0000 0x2000>;
1047                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1048                                 interrupt-names = "cmd_irq";
1049                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1050                                 clock-names     = "mclk", "apb_pclk";
1051                                 bus-width       = <4>;
1052                                 cap-sd-highspeed;
1053                                 cap-mmc-highspeed;
1054                                 max-frequency   = <48000000>;
1055                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1056                                 dma-names = "tx", "rx";
1057                                 pinctrl-names = "default";
1058                                 pinctrl-0 = <&sdc4_gpios>;
1059                         };
1060                 };
1061
1062                 tcsr: syscon@1a400000 {
1063                         compatible = "qcom,tcsr-apq8064", "syscon";
1064                         reg = <0x1a400000 0x100>;
1065                 };
1066
1067                 gpu: adreno-3xx@4300000 {
1068                         compatible = "qcom,adreno-3xx";
1069                         reg = <0x04300000 0x20000>;
1070                         reg-names = "kgsl_3d0_reg_memory";
1071                         interrupts = <GIC_SPI 80 0>;
1072                         interrupt-names = "kgsl_3d0_irq";
1073                         clock-names =
1074                             "core_clk",
1075                             "iface_clk",
1076                             "mem_clk",
1077                             "mem_iface_clk";
1078                         clocks =
1079                             <&mmcc GFX3D_CLK>,
1080                             <&mmcc GFX3D_AHB_CLK>,
1081                             <&mmcc GFX3D_AXI_CLK>,
1082                             <&mmcc MMSS_IMEM_AHB_CLK>;
1083                         qcom,chipid = <0x03020002>;
1084
1085                         iommus = <&gfx3d 0
1086                                   &gfx3d 1
1087                                   &gfx3d 2
1088                                   &gfx3d 3
1089                                   &gfx3d 4
1090                                   &gfx3d 5
1091                                   &gfx3d 6
1092                                   &gfx3d 7
1093                                   &gfx3d 8
1094                                   &gfx3d 9
1095                                   &gfx3d 10
1096                                   &gfx3d 11
1097                                   &gfx3d 12
1098                                   &gfx3d 13
1099                                   &gfx3d 14
1100                                   &gfx3d 15
1101                                   &gfx3d 16
1102                                   &gfx3d 17
1103                                   &gfx3d 18
1104                                   &gfx3d 19
1105                                   &gfx3d 20
1106                                   &gfx3d 21
1107                                   &gfx3d 22
1108                                   &gfx3d 23
1109                                   &gfx3d 24
1110                                   &gfx3d 25
1111                                   &gfx3d 26
1112                                   &gfx3d 27
1113                                   &gfx3d 28
1114                                   &gfx3d 29
1115                                   &gfx3d 30
1116                                   &gfx3d 31
1117                                   &gfx3d1 0
1118                                   &gfx3d1 1
1119                                   &gfx3d1 2
1120                                   &gfx3d1 3
1121                                   &gfx3d1 4
1122                                   &gfx3d1 5
1123                                   &gfx3d1 6
1124                                   &gfx3d1 7
1125                                   &gfx3d1 8
1126                                   &gfx3d1 9
1127                                   &gfx3d1 10
1128                                   &gfx3d1 11
1129                                   &gfx3d1 12
1130                                   &gfx3d1 13
1131                                   &gfx3d1 14
1132                                   &gfx3d1 15
1133                                   &gfx3d1 16
1134                                   &gfx3d1 17
1135                                   &gfx3d1 18
1136                                   &gfx3d1 19
1137                                   &gfx3d1 20
1138                                   &gfx3d1 21
1139                                   &gfx3d1 22
1140                                   &gfx3d1 23
1141                                   &gfx3d1 24
1142                                   &gfx3d1 25
1143                                   &gfx3d1 26
1144                                   &gfx3d1 27
1145                                   &gfx3d1 28
1146                                   &gfx3d1 29
1147                                   &gfx3d1 30
1148                                   &gfx3d1 31>;
1149
1150                         qcom,gpu-pwrlevels {
1151                                 compatible = "qcom,gpu-pwrlevels";
1152                                 qcom,gpu-pwrlevel@0 {
1153                                         qcom,gpu-freq = <450000000>;
1154                                 };
1155                                 qcom,gpu-pwrlevel@1 {
1156                                         qcom,gpu-freq = <27000000>;
1157                                 };
1158                         };
1159                 };
1160
1161                 mmss_sfpb: syscon@5700000 {
1162                         compatible = "syscon";
1163                         reg = <0x5700000 0x70>;
1164                 };
1165
1166                 dsi0: mdss_dsi@4700000 {
1167                         compatible = "qcom,mdss-dsi-ctrl";
1168                         label = "MDSS DSI CTRL->0";
1169                         #address-cells = <1>;
1170                         #size-cells = <0>;
1171                         interrupts = <GIC_SPI 82 0>;
1172                         reg = <0x04700000 0x200>;
1173                         reg-names = "dsi_ctrl";
1174
1175                         clocks = <&mmcc DSI_M_AHB_CLK>,
1176                                 <&mmcc DSI_S_AHB_CLK>,
1177                                 <&mmcc AMP_AHB_CLK>,
1178                                 <&mmcc DSI_CLK>,
1179                                 <&mmcc DSI1_BYTE_CLK>,
1180                                 <&mmcc DSI_PIXEL_CLK>,
1181                                 <&mmcc DSI1_ESC_CLK>;
1182                         clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1183                                         "src_clk", "byte_clk", "pixel_clk",
1184                                         "core_clk";
1185
1186                         assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1187                                         <&mmcc DSI1_ESC_SRC>,
1188                                         <&mmcc DSI_SRC>,
1189                                         <&mmcc DSI_PIXEL_SRC>;
1190                         assigned-clock-parents = <&dsi0_phy 0>,
1191                                                 <&dsi0_phy 0>,
1192                                                 <&dsi0_phy 1>,
1193                                                 <&dsi0_phy 1>;
1194                         syscon-sfpb = <&mmss_sfpb>;
1195                         phys = <&dsi0_phy>;
1196                         ports {
1197                                 #address-cells = <1>;
1198                                 #size-cells = <0>;
1199
1200                                 port@0 {
1201                                         reg = <0>;
1202                                         dsi0_in: endpoint {
1203                                         };
1204                                 };
1205
1206                                 port@1 {
1207                                         reg = <1>;
1208                                         dsi0_out: endpoint {
1209                                         };
1210                                 };
1211                         };
1212                 };
1213
1214
1215                 dsi0_phy: dsi-phy@4700200 {
1216                         compatible = "qcom,dsi-phy-28nm-8960";
1217                         #clock-cells = <1>;
1218
1219                         reg = <0x04700200 0x100>,
1220                                 <0x04700300 0x200>,
1221                                 <0x04700500 0x5c>;
1222                         reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1223                         clock-names = "iface_clk";
1224                         clocks = <&mmcc DSI_M_AHB_CLK>;
1225                 };
1226
1227
1228                 mdp_port0: iommu@7500000 {
1229                         compatible = "qcom,apq8064-iommu";
1230                         #iommu-cells = <1>;
1231                         clock-names =
1232                             "smmu_pclk",
1233                             "iommu_clk";
1234                         clocks =
1235                             <&mmcc SMMU_AHB_CLK>,
1236                             <&mmcc MDP_AXI_CLK>;
1237                         reg = <0x07500000 0x100000>;
1238                         interrupts =
1239                             <GIC_SPI 63 0>,
1240                             <GIC_SPI 64 0>;
1241                         qcom,ncb = <2>;
1242                 };
1243
1244                 mdp_port1: iommu@7600000 {
1245                         compatible = "qcom,apq8064-iommu";
1246                         #iommu-cells = <1>;
1247                         clock-names =
1248                             "smmu_pclk",
1249                             "iommu_clk";
1250                         clocks =
1251                             <&mmcc SMMU_AHB_CLK>,
1252                             <&mmcc MDP_AXI_CLK>;
1253                         reg = <0x07600000 0x100000>;
1254                         interrupts =
1255                             <GIC_SPI 61 0>,
1256                             <GIC_SPI 62 0>;
1257                         qcom,ncb = <2>;
1258                 };
1259
1260                 gfx3d: iommu@7c00000 {
1261                         compatible = "qcom,apq8064-iommu";
1262                         #iommu-cells = <1>;
1263                         clock-names =
1264                             "smmu_pclk",
1265                             "iommu_clk";
1266                         clocks =
1267                             <&mmcc SMMU_AHB_CLK>,
1268                             <&mmcc GFX3D_AXI_CLK>;
1269                         reg = <0x07c00000 0x100000>;
1270                         interrupts =
1271                             <GIC_SPI 69 0>,
1272                             <GIC_SPI 70 0>;
1273                         qcom,ncb = <3>;
1274                 };
1275
1276                 gfx3d1: iommu@7d00000 {
1277                         compatible = "qcom,apq8064-iommu";
1278                         #iommu-cells = <1>;
1279                         clock-names =
1280                             "smmu_pclk",
1281                             "iommu_clk";
1282                         clocks =
1283                             <&mmcc SMMU_AHB_CLK>,
1284                             <&mmcc GFX3D_AXI_CLK>;
1285                         reg = <0x07d00000 0x100000>;
1286                         interrupts =
1287                             <GIC_SPI 210 0>,
1288                             <GIC_SPI 211 0>;
1289                         qcom,ncb = <3>;
1290                 };
1291
1292                 pcie: pci@1b500000 {
1293                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1294                         reg = <0x1b500000 0x1000
1295                                0x1b502000 0x80
1296                                0x1b600000 0x100
1297                                0x0ff00000 0x100000>;
1298                         reg-names = "dbi", "elbi", "parf", "config";
1299                         device_type = "pci";
1300                         linux,pci-domain = <0>;
1301                         bus-range = <0x00 0xff>;
1302                         num-lanes = <1>;
1303                         #address-cells = <3>;
1304                         #size-cells = <2>;
1305                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
1306                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1307                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1308                         interrupt-names = "msi";
1309                         #interrupt-cells = <1>;
1310                         interrupt-map-mask = <0 0 0 0x7>;
1311                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1312                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1313                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1314                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1315                         clocks = <&gcc PCIE_A_CLK>,
1316                                  <&gcc PCIE_H_CLK>,
1317                                  <&gcc PCIE_PHY_REF_CLK>;
1318                         clock-names = "core", "iface", "phy";
1319                         resets = <&gcc PCIE_ACLK_RESET>,
1320                                  <&gcc PCIE_HCLK_RESET>,
1321                                  <&gcc PCIE_POR_RESET>,
1322                                  <&gcc PCIE_PCI_RESET>,
1323                                  <&gcc PCIE_PHY_RESET>;
1324                         reset-names = "axi", "ahb", "por", "pci", "phy";
1325                         status = "disabled";
1326                 };
1327
1328                 hdmi: hdmi-tx@4a00000 {
1329                         compatible = "qcom,hdmi-tx-8960";
1330                         reg = <0x04a00000 0x2f0>;
1331                         reg-names = "core_physical";
1332                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1333                         clocks = <&mmcc HDMI_APP_CLK>,
1334                                  <&mmcc HDMI_M_AHB_CLK>,
1335                                  <&mmcc HDMI_S_AHB_CLK>;
1336                         clock-names = "core_clk",
1337                                       "master_iface_clk",
1338                                       "slave_iface_clk";
1339
1340                         phys = <&hdmi_phy>;
1341                         phy-names = "hdmi-phy";
1342
1343                         ports {
1344                                 #address-cells = <1>;
1345                                 #size-cells = <0>;
1346
1347                                 port@0 {
1348                                         reg = <0>;
1349                                         hdmi_in: endpoint {
1350                                         };
1351                                 };
1352
1353                                 port@1 {
1354                                         reg = <1>;
1355                                         hdmi_out: endpoint {
1356                                         };
1357                                 };
1358                         };
1359                 };
1360
1361                 hdmi_phy: hdmi-phy@4a00400 {
1362                         compatible = "qcom,hdmi-phy-8960";
1363                         reg = <0x4a00400 0x60>,
1364                               <0x4a00500 0x100>;
1365                         reg-names = "hdmi_phy",
1366                                     "hdmi_pll";
1367
1368                         clocks = <&mmcc HDMI_S_AHB_CLK>;
1369                         clock-names = "slave_iface_clk";
1370                 };
1371
1372                 mdp: mdp@5100000 {
1373                         compatible = "qcom,mdp4";
1374                         reg = <0x05100000 0xf0000>;
1375                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1376                         clocks = <&mmcc MDP_CLK>,
1377                                  <&mmcc MDP_AHB_CLK>,
1378                                  <&mmcc MDP_AXI_CLK>,
1379                                  <&mmcc MDP_LUT_CLK>,
1380                                  <&mmcc HDMI_TV_CLK>,
1381                                  <&mmcc MDP_TV_CLK>;
1382                         clock-names = "core_clk",
1383                                       "iface_clk",
1384                                       "bus_clk",
1385                                       "lut_clk",
1386                                       "hdmi_clk",
1387                                       "tv_clk";
1388
1389                         iommus = <&mdp_port0 0
1390                                   &mdp_port0 2
1391                                   &mdp_port1 0
1392                                   &mdp_port1 2>;
1393
1394                         ports {
1395                                 #address-cells = <1>;
1396                                 #size-cells = <0>;
1397
1398                                 port@0 {
1399                                         reg = <0>;
1400                                         mdp_lvds_out: endpoint {
1401                                         };
1402                                 };
1403
1404                                 port@1 {
1405                                         reg = <1>;
1406                                         mdp_dsi1_out: endpoint {
1407                                         };
1408                                 };
1409
1410                                 port@2 {
1411                                         reg = <2>;
1412                                         mdp_dsi2_out: endpoint {
1413                                         };
1414                                 };
1415
1416                                 port@3 {
1417                                         reg = <3>;
1418                                         mdp_dtv_out: endpoint {
1419                                         };
1420                                 };
1421                         };
1422                 };
1423         };
1424 };
1425 #include "qcom-apq8064-pins.dtsi"