arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         model = "Qualcomm APQ8064";
  14         compatible = "qcom,apq8064";
  15         interrupt-parent = <&intc>;
  16
  17         reserved-memory {
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 ranges;
  21
  22                 smem_region: smem@80000000 {
  23                         reg = <0x80000000 0x200000>;
  24                         no-map;
  25                 };
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 CPU0: cpu@0 {
  33                         compatible = "qcom,krait";
  34                         enable-method = "qcom,kpss-acc-v1";
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                         next-level-cache = <&L2>;
  38                         qcom,acc = <&acc0>;
  39                         qcom,saw = <&saw0>;
  40                         cpu-idle-states = <&CPU_SPC>;
  41                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  42                         clock-names = "cpu", "l2";
  43                         clock-latency = <100000>;
  44                         cooling-min-level = <0>;
  45                         cooling-max-level = <7>;
  46                         #cooling-cells = <2>;
  47                 };
  48
  49                 CPU1: cpu@1 {
  50                         compatible = "qcom,krait";
  51                         enable-method = "qcom,kpss-acc-v1";
  52                         device_type = "cpu";
  53                         reg = <1>;
  54                         next-level-cache = <&L2>;
  55                         qcom,acc = <&acc1>;
  56                         qcom,saw = <&saw1>;
  57                         cpu-idle-states = <&CPU_SPC>;
  58                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  59                         clock-names = "cpu", "l2";
  60                         clock-latency = <100000>;
  61                         cooling-min-level = <0>;
  62                         cooling-max-level = <7>;
  63                         #cooling-cells = <2>;
  64                 };
  65
  66                 CPU2: cpu@2 {
  67                         compatible = "qcom,krait";
  68                         enable-method = "qcom,kpss-acc-v1";
  69                         device_type = "cpu";
  70                         reg = <2>;
  71                         next-level-cache = <&L2>;
  72                         qcom,acc = <&acc2>;
  73                         qcom,saw = <&saw2>;
  74                         cpu-idle-states = <&CPU_SPC>;
  75                         clocks = <&kraitcc 2>, <&kraitcc 4>;
  76                         clock-names = "cpu", "l2";
  77                         clock-latency = <100000>;
  78                         cooling-min-level = <0>;
  79                         cooling-max-level = <7>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 CPU3: cpu@3 {
  84                         compatible = "qcom,krait";
  85                         enable-method = "qcom,kpss-acc-v1";
  86                         device_type = "cpu";
  87                         reg = <3>;
  88                         next-level-cache = <&L2>;
  89                         qcom,acc = <&acc3>;
  90                         qcom,saw = <&saw3>;
  91                         cpu-idle-states = <&CPU_SPC>;
  92                         clocks = <&kraitcc 3>, <&kraitcc 4>;
  93                         clock-names = "cpu", "l2";
  94                         clock-latency = <100000>;
  95                         cooling-min-level = <0>;
  96                         cooling-max-level = <7>;
  97                         #cooling-cells = <2>;
  98                 };
  99
 100                 L2: l2-cache {
 101                         compatible = "cache";
 102                         cache-level = <2>;
 103                 };
 104
 105                 qcom,l2 {
 106                         qcom,l2-rates = <384000000 972000000 1188000000>;
 107                 };
 108
 109                 idle-states {
 110                         CPU_SPC: spc {
 111                                 compatible = "qcom,idle-state-spc",
 112                                                 "arm,idle-state";
 113                                 entry-latency-us = <400>;
 114                                 exit-latency-us = <900>;
 115                                 min-residency-us = <3000>;
 116                         };
 117                 };
 118         };
 119
 120         thermal-zones {
 121                 cpu-thermal0 {
 122                         polling-delay-passive = <250>;
 123                         polling-delay = <1000>;
 124
 125                         thermal-sensors = <&tsens 7>;
 126
 127                         trips {
 128                                 cpu_alert0: trip@0 {
 129                                         temperature = <75000>;
 130                                         hysteresis = <2000>;
 131                                         type = "passive";
 132                                 };
 133                                 cpu_crit0: trip@1 {
 134                                         temperature = <110000>;
 135                                         hysteresis = <2000>;
 136                                         type = "critical";
 137                                 };
 138                         };
 139
 140                         cooling-maps {
 141                                 map0 {
 142                                         trip = <&cpu_alert0>;
 143                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 144                                 };
 145                         };
 146                 };
 147
 148                 cpu-thermal1 {
 149                         polling-delay-passive = <250>;
 150                         polling-delay = <1000>;
 151
 152                         thermal-sensors = <&tsens 8>;
 153
 154                         trips {
 155                                 cpu_alert1: trip@0 {
 156                                         temperature = <75000>;
 157                                         hysteresis = <2000>;
 158                                         type = "passive";
 159                                 };
 160                                 cpu_crit1: trip@1 {
 161                                         temperature = <110000>;
 162                                         hysteresis = <2000>;
 163                                         type = "critical";
 164                                 };
 165                         };
 166
 167                         cooling-maps {
 168                                 map0 {
 169                                         trip = <&cpu_alert1>;
 170                                         cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 171                                 };
 172                         };
 173                 };
 174
 175                 cpu-thermal2 {
 176                         polling-delay-passive = <250>;
 177                         polling-delay = <1000>;
 178
 179                         thermal-sensors = <&tsens 9>;
 180
 181                         trips {
 182                                 cpu_alert2: trip@0 {
 183                                         temperature = <75000>;
 184                                         hysteresis = <2000>;
 185                                         type = "passive";
 186                                 };
 187                                 cpu_crit2: trip@1 {
 188                                         temperature = <110000>;
 189                                         hysteresis = <2000>;
 190                                         type = "critical";
 191                                 };
 192                         };
 193
 194                         cooling-maps {
 195                                 map0 {
 196                                         trip = <&cpu_alert2>;
 197                                         cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 198                                 };
 199                         };
 200                 };
 201
 202                 cpu-thermal3 {
 203                         polling-delay-passive = <250>;
 204                         polling-delay = <1000>;
 205
 206                         thermal-sensors = <&tsens 10>;
 207
 208                         trips {
 209                                 cpu_alert3: trip@0 {
 210                                         temperature = <75000>;
 211                                         hysteresis = <2000>;
 212                                         type = "passive";
 213                                 };
 214                                 cpu_crit3: trip@1 {
 215                                         temperature = <110000>;
 216                                         hysteresis = <2000>;
 217                                         type = "critical";
 218                                 };
 219                         };
 220
 221                         cooling-maps {
 222                                 map0 {
 223                                         trip = <&cpu_alert3>;
 224                                         cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 225                                 };
 226                         };
 227                 };
 228         };
 229
 230         thermal-zones {
 231                 cpu-thermal0 {
 232                         polling-delay-passive = <250>;
 233                         polling-delay = <1000>;
 234
 235                         thermal-sensors = <&gcc 7>;
 236
 237                         trips {
 238                                 cpu_alert0: trip@0 {
 239                                         temperature = <75000>;
 240                                         hysteresis = <2000>;
 241                                         type = "passive";
 242                                 };
 243                                 cpu_crit0: trip@1 {
 244                                         temperature = <95000>;
 245                                         hysteresis = <2000>;
 246                                         type = "critical";
 247                                 };
 248                         };
 249                 };
 250
 251                 cpu-thermal1 {
 252                         polling-delay-passive = <250>;
 253                         polling-delay = <1000>;
 254
 255                         thermal-sensors = <&gcc 8>;
 256
 257                         trips {
 258                                 cpu_alert1: trip@0 {
 259                                         temperature = <75000>;
 260                                         hysteresis = <2000>;
 261                                         type = "passive";
 262                                 };
 263                                 cpu_crit1: trip@1 {
 264                                         temperature = <95000>;
 265                                         hysteresis = <2000>;
 266                                         type = "critical";
 267                                 };
 268                         };
 269                 };
 270
 271                 cpu-thermal2 {
 272                         polling-delay-passive = <250>;
 273                         polling-delay = <1000>;
 274
 275                         thermal-sensors = <&gcc 9>;
 276
 277                         trips {
 278                                 cpu_alert2: trip@0 {
 279                                         temperature = <75000>;
 280                                         hysteresis = <2000>;
 281                                         type = "passive";
 282                                 };
 283                                 cpu_crit2: trip@1 {
 284                                         temperature = <95000>;
 285                                         hysteresis = <2000>;
 286                                         type = "critical";
 287                                 };
 288                         };
 289                 };
 290
 291                 cpu-thermal3 {
 292                         polling-delay-passive = <250>;
 293                         polling-delay = <1000>;
 294
 295                         thermal-sensors = <&gcc 10>;
 296
 297                         trips {
 298                                 cpu_alert3: trip@0 {
 299                                         temperature = <75000>;
 300                                         hysteresis = <2000>;
 301                                         type = "passive";
 302                                 };
 303                                 cpu_crit3: trip@1 {
 304                                         temperature = <95000>;
 305                                         hysteresis = <2000>;
 306                                         type = "critical";
 307                                 };
 308                         };
 309                 };
 310         };
 311
 312         cpu-pmu {
 313                 compatible = "qcom,krait-pmu";
 314                 interrupts = <1 10 0x304>;
 315         };
 316
 317         clocks {
 318                 cxo_board {
 319                         compatible = "fixed-clock";
 320                         #clock-cells = <0>;
 321                         clock-frequency = <19200000>;
 322                 };
 323
 324                 pxo_board {
 325                         compatible = "fixed-clock";
 326                         #clock-cells = <0>;
 327                         clock-frequency = <27000000>;
 328                 };
 329
 330                 sleep_clk {
 331                         compatible = "fixed-clock";
 332                         #clock-cells = <0>;
 333                         clock-frequency = <32768>;
 334                 };
 335         };
 336
 337         sfpb_mutex: hwmutex {
 338                 compatible = "qcom,sfpb-mutex";
 339                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 340                 #hwlock-cells = <1>;
 341         };
 342
 343         smem {
 344                 compatible = "qcom,smem";
 345                 memory-region = <&smem_region>;
 346
 347                 hwlocks = <&sfpb_mutex 3>;
 348         };
 349
 350         qcom,pvs {
 351                 qcom,pvs-format-a;
 352                 qcom,speed0-pvs0-bin-v0 =
 353                         < 384000000 950000  >,
 354                         < 486000000 975000  >,
 355                         < 594000000 1000000  >,
 356                         < 702000000 1025000  >,
 357                         < 810000000 1075000  >,
 358                         < 918000000 1100000  >,
 359                         < 1026000000 1125000 >,
 360                         < 1080000000 1175000 >,
 361                         < 1134000000 1175000 >,
 362                         < 1188000000 1200000 >,
 363                         < 1242000000 1200000 >,
 364                         < 1296000000 1225000 >,
 365                         < 1350000000 1225000 >,
 366                         < 1404000000 1237500 >,
 367                         < 1458000000 1237500 >,
 368                         < 1512000000 1250000 >;
 369
 370                 qcom,speed0-pvs1-bin-v0 =
 371                         < 384000000 900000  >,
 372                         < 486000000 925000  >,
 373                         < 594000000 950000  >,
 374                         < 702000000 975000  >,
 375                         < 810000000 1025000  >,
 376                         < 918000000 1050000  >,
 377                         < 1026000000 1075000 >,
 378                         < 1080000000 1125000 >,
 379                         < 1134000000 1125000 >,
 380                         < 1188000000 1150000 >,
 381                         < 1242000000 1150000 >,
 382                         < 1296000000 1175000 >,
 383                         < 1350000000 1175000 >,
 384                         < 1404000000 1187500 >,
 385                         < 1458000000 1187500 >,
 386                         < 1512000000 1200000 >;
 387
 388                 qcom,speed0-pvs3-bin-v0 =
 389                         < 384000000 850000  >,
 390                         < 486000000 875000  >,
 391                         < 594000000 900000  >,
 392                         < 702000000 925000  >,
 393                         < 810000000 975000  >,
 394                         < 918000000 1000000  >,
 395                         < 1026000000 1025000 >,
 396                         < 1080000000 1075000 >,
 397                         < 1134000000 1075000 >,
 398                         < 1188000000 1100000 >,
 399                         < 1242000000 1100000 >,
 400                         < 1296000000 1125000 >,
 401                         < 1350000000 1125000 >,
 402                         < 1404000000 1137500 >,
 403                         < 1458000000 1137500 >,
 404                         < 1512000000 1150000 >;
 405
 406                 qcom,speed0-pvs4-bin-v0 =
 407                         < 384000000 850000  >,
 408                         < 486000000 875000  >,
 409                         < 594000000 900000  >,
 410                         < 702000000 925000  >,
 411                         < 810000000 962500  >,
 412                         < 918000000 975000  >,
 413                         < 1026000000 1000000 >,
 414                         < 1080000000 1050000 >,
 415                         < 1134000000 1050000 >,
 416                         < 1188000000 1075000 >,
 417                         < 1242000000 1075000 >,
 418                         < 1296000000 1100000 >,
 419                         < 1350000000 1100000 >,
 420                         < 1404000000 1112500 >,
 421                         < 1458000000 1112500 >,
 422                         < 1512000000 1125000 >;
 423
 424                 qcom,speed1-pvs0-bin-v0 =
 425                         < 384000000 950000  >,
 426                         < 486000000 950000  >,
 427                         < 594000000 950000  >,
 428                         < 702000000 962500  >,
 429                         < 810000000 1000000  >,
 430                         < 918000000 1025000  >,
 431                         < 1026000000 1037500 >,
 432                         < 1134000000 1075000 >,
 433                         < 1242000000 1087500 >,
 434                         < 1350000000 1125000 >,
 435                         < 1458000000 1150000 >,
 436                         < 1566000000 1175000 >,
 437                         < 1674000000 1225000 >,
 438                         < 1728000000 1250000 >;
 439
 440                 qcom,speed1-pvs1-bin-v0 =
 441                         < 384000000 950000  >,
 442                         < 486000000 950000  >,
 443                         < 594000000 950000  >,
 444                         < 702000000 962500  >,
 445                         < 810000000 975000  >,
 446                         < 918000000 1000000 >,
 447                         < 1026000000 1012500 >,
 448                         < 1134000000 1037500 >,
 449                         < 1242000000 1050000 >,
 450                         < 1350000000 1087500 >,
 451                         < 1458000000 1112500 >,
 452                         < 1566000000 1150000 >,
 453                         < 1674000000 1187500 >,
 454                         < 1728000000 1200000 >;
 455
 456                 qcom,speed1-pvs2-bin-v0 =
 457                         < 384000000 925000  >,
 458                         < 486000000 925000  >,
 459                         < 594000000 925000  >,
 460                         < 702000000 925000  >,
 461                         < 810000000 937500  >,
 462                         < 918000000 950000  >,
 463                         < 1026000000 975000 >,
 464                         < 1134000000 1000000 >,
 465                         < 1242000000 1012500 >,
 466                         < 1350000000 1037500 >,
 467                         < 1458000000 1075000 >,
 468                         < 1566000000 1100000 >,
 469                         < 1674000000 1137500 >,
 470                         < 1728000000 1162500 >;
 471
 472                 qcom,speed1-pvs3-bin-v0 =
 473                         < 384000000 900000  >,
 474                         < 486000000 900000  >,
 475                         < 594000000 900000  >,
 476                         < 702000000 900000  >,
 477                         < 810000000 900000  >,
 478                         < 918000000 925000  >,
 479                         < 1026000000 950000 >,
 480                         < 1134000000 975000 >,
 481                         < 1242000000 987500 >,
 482                         < 1350000000 1000000 >,
 483                         < 1458000000 1037500 >,
 484                         < 1566000000 1062500 >,
 485                         < 1674000000 1100000 >,
 486                         < 1728000000 1125000 >;
 487
 488                 qcom,speed1-pvs4-bin-v0 =
 489                         < 384000000 875000  >,
 490                         < 486000000 875000  >,
 491                         < 594000000 875000  >,
 492                         < 702000000 875000  >,
 493                         < 810000000 887500  >,
 494                         < 918000000 900000  >,
 495                         < 1026000000 925000 >,
 496                         < 1134000000 950000 >,
 497                         < 1242000000 962500 >,
 498                         < 1350000000 975000 >,
 499                         < 1458000000 1000000 >,
 500                         < 1566000000 1037500 >,
 501                         < 1674000000 1075000 >,
 502                         < 1728000000 1100000 >;
 503
 504                 qcom,speed1-pvs5-bin-v0 =
 505                         < 384000000 875000  >,
 506                         < 486000000 875000  >,
 507                         < 594000000 875000  >,
 508                         < 702000000 875000  >,
 509                         < 810000000 887500  >,
 510                         < 918000000 900000  >,
 511                         < 1026000000 925000 >,
 512                         < 1134000000 937500 >,
 513                         < 1242000000 950000 >,
 514                         < 1350000000 962500 >,
 515                         < 1458000000 987500 >,
 516                         < 1566000000 1012500 >,
 517                         < 1674000000 1050000 >,
 518                         < 1728000000 1075000 >;
 519
 520                 qcom,speed1-pvs6-bin-v0 =
 521                         < 384000000 875000  >,
 522                         < 486000000 875000  >,
 523                         < 594000000 875000  >,
 524                         < 702000000 875000  >,
 525                         < 810000000 887500  >,
 526                         < 918000000 900000  >,
 527                         < 1026000000 925000 >,
 528                         < 1134000000 937500 >,
 529                         < 1242000000 950000 >,
 530                         < 1350000000 962500 >,
 531                         < 1458000000 975000 >,
 532                         < 1566000000 1000000 >,
 533                         < 1674000000 1025000 >,
 534                         < 1728000000 1050000 >;
 535
 536                 qcom,speed2-pvs0-bin-v0 =
 537                         < 384000000 950000  >,
 538                         < 486000000 950000  >,
 539                         < 594000000 950000  >,
 540                         < 702000000 950000  >,
 541                         < 810000000 962500  >,
 542                         < 918000000 975000  >,
 543                         < 1026000000 1000000 >,
 544                         < 1134000000 1025000 >,
 545                         < 1242000000 1037500 >,
 546                         < 1350000000 1062500 >,
 547                         < 1458000000 1100000 >,
 548                         < 1566000000 1125000 >,
 549                         < 1674000000 1175000 >,
 550                         < 1782000000 1225000 >,
 551                         < 1890000000 1287500 >;
 552
 553                 qcom,speed2-pvs1-bin-v0 =
 554                         < 384000000 925000  >,
 555                         < 486000000 925000  >,
 556                         < 594000000 925000  >,
 557                         < 702000000 925000  >,
 558                         < 810000000 937500  >,
 559                         < 918000000 950000  >,
 560                         < 1026000000 975000 >,
 561                         < 1134000000 1000000 >,
 562                         < 1242000000 1012500 >,
 563                         < 1350000000 1037500 >,
 564                         < 1458000000 1075000 >,
 565                         < 1566000000 1100000 >,
 566                         < 1674000000 1137500 >,
 567                         < 1782000000 1187500 >,
 568                         < 1890000000 1250000 >;
 569
 570                 qcom,speed2-pvs2-bin-v0 =
 571                         < 384000000 900000  >,
 572                         < 486000000 900000  >,
 573                         < 594000000 900000  >,
 574                         < 702000000 900000  >,
 575                         < 810000000 912500  >,
 576                         < 918000000 925000  >,
 577                         < 1026000000 950000 >,
 578                         < 1134000000 975000 >,
 579                         < 1242000000 987500 >,
 580                         < 1350000000 1012500 >,
 581                         < 1458000000 1050000 >,
 582                         < 1566000000 1075000 >,
 583                         < 1674000000 1112500 >,
 584                         < 1782000000 1162500 >,
 585                         < 1890000000 1212500 >;
 586
 587                 qcom,speed2-pvs3-bin-v0 =
 588                         < 384000000 900000  >,
 589                         < 486000000 900000  >,
 590                         < 594000000 900000  >,
 591                         < 702000000 900000  >,
 592                         < 810000000 900000  >,
 593                         < 918000000 912500  >,
 594                         < 1026000000 937500 >,
 595                         < 1134000000 962500 >,
 596                         < 1242000000 975000 >,
 597                         < 1350000000 1000000 >,
 598                         < 1458000000 1025000 >,
 599                         < 1566000000 1050000 >,
 600                         < 1674000000 1087500 >,
 601                         < 1782000000 1137500 >,
 602                         < 1890000000 1175000 >;
 603
 604                 qcom,speed2-pvs4-bin-v0 =
 605                         < 384000000 875000  >,
 606                         < 486000000 875000  >,
 607                         < 594000000 875000  >,
 608                         < 702000000 875000  >,
 609                         < 810000000 887500  >,
 610                         < 918000000 900000  >,
 611                         < 1026000000 925000 >,
 612                         < 1134000000 950000 >,
 613                         < 1242000000 962500 >,
 614                         < 1350000000 975000 >,
 615                         < 1458000000 1000000 >,
 616                         < 1566000000 1037500 >,
 617                         < 1674000000 1075000 >,
 618                         < 1782000000 1112500 >,
 619                         < 1890000000 1150000 >;
 620
 621                 qcom,speed2-pvs5-bin-v0 =
 622                         < 384000000 875000  >,
 623                         < 486000000 875000  >,
 624                         < 594000000 875000  >,
 625                         < 702000000 875000  >,
 626                         < 810000000 887500  >,
 627                         < 918000000 900000  >,
 628                         < 1026000000 925000 >,
 629                         < 1134000000 937500 >,
 630                         < 1242000000 950000 >,
 631                         < 1350000000 962500 >,
 632                         < 1458000000 987500 >,
 633                         < 1566000000 1012500 >,
 634                         < 1674000000 1050000 >,
 635                         < 1782000000 1087500 >,
 636                         < 1890000000 1125000 >;
 637
 638                 qcom,speed2-pvs6-bin-v0 =
 639                         < 384000000 875000  >,
 640                         < 486000000 875000  >,
 641                         < 594000000 875000  >,
 642                         < 702000000 875000  >,
 643                         < 810000000 887500  >,
 644                         < 918000000 900000  >,
 645                         < 1026000000 925000 >,
 646                         < 1134000000 937500 >,
 647                         < 1242000000 950000 >,
 648                         < 1350000000 962500 >,
 649                         < 1458000000 975000 >,
 650                         < 1566000000 1000000 >,
 651                         < 1674000000 1025000 >,
 652                         < 1782000000 1062500 >,
 653                         < 1890000000 1100000 >;
 654
 655                 qcom,speed14-pvs0-bin-v0 =
 656                         < 384000000 950000 >,
 657                         < 486000000 950000 >,
 658                         < 594000000 950000 >,
 659                         < 702000000 962500 >,
 660                         < 810000000 1000000 >,
 661                         < 918000000 1025000 >,
 662                         < 1026000000 1037500 >,
 663                         < 1134000000 1075000 >,
 664                         < 1242000000 1087500 >,
 665                         < 1350000000 1125000 >,
 666                         < 1458000000 1150000 >,
 667                         < 1512000000 1162500 >;
 668
 669                 qcom,speed14-pvs1-bin-v0 =
 670                         < 384000000 950000 >,
 671                         < 486000000 950000 >,
 672                         < 594000000 950000 >,
 673                         < 702000000 962500 >,
 674                         < 810000000 975000 >,
 675                         < 918000000 1000000 >,
 676                         < 1026000000 1012500 >,
 677                         < 1134000000 1037500 >,
 678                         < 1242000000 1050000 >,
 679                         < 1350000000 1087500 >,
 680                         < 1458000000 1112500 >,
 681                         < 1512000000 1125000 >;
 682
 683                 qcom,speed14-pvs2-bin-v0 =
 684                         < 384000000 925000 >,
 685                         < 486000000 925000 >,
 686                         < 594000000 925000 >,
 687                         < 702000000 925000 >,
 688                         < 810000000 937500 >,
 689                         < 918000000 950000 >,
 690                         < 1026000000 975000 >,
 691                         < 1134000000 1000000 >,
 692                         < 1242000000 1012500 >,
 693                         < 1350000000 1037500 >,
 694                         < 1458000000 1075000 >,
 695                         < 1512000000 1087500 >;
 696
 697                 qcom,speed14-pvs3-bin-v0 =
 698                         < 384000000 900000 >,
 699                         < 486000000 900000 >,
 700                         < 594000000 900000 >,
 701                         < 702000000 900000 >,
 702                         < 810000000 900000 >,
 703                         < 918000000 925000 >,
 704                         < 1026000000 950000 >,
 705                         < 1134000000 975000 >,
 706                         < 1242000000 987500 >,
 707                         < 1350000000 1000000 >,
 708                         < 1458000000 1037500 >,
 709                         < 1512000000 1050000 >;
 710
 711                 qcom,speed14-pvs4-bin-v0 =
 712                         < 384000000 875000 >,
 713                         < 486000000 875000 >,
 714                         < 594000000 875000 >,
 715                         < 702000000 875000 >,
 716                         < 810000000 887500 >,
 717                         < 918000000 900000 >,
 718                         < 1026000000 925000 >,
 719                         < 1134000000 950000 >,
 720                         < 1242000000 962500 >,
 721                         < 1350000000 975000 >,
 722                         < 1458000000 1000000 >,
 723                         < 1512000000 1012500 >;
 724
 725                 qcom,speed14-pvs5-bin-v0 =
 726                         < 384000000 875000 >,
 727                         < 486000000 875000 >,
 728                         < 594000000 875000 >,
 729                         < 702000000 875000 >,
 730                         < 810000000 887500 >,
 731                         < 918000000 900000 >,
 732                         < 1026000000 925000 >,
 733                         < 1134000000 937500 >,
 734                         < 1242000000 950000 >,
 735                         < 1350000000 962500 >,
 736                         < 1458000000 987500 >,
 737                         < 1512000000 1000000 >;
 738
 739                 qcom,speed14-pvs6-bin-v0 =
 740                         < 384000000 875000 >,
 741                         < 486000000 875000 >,
 742                         < 594000000 875000 >,
 743                         < 702000000 875000 >,
 744                         < 810000000 887500 >,
 745                         < 918000000 900000 >,
 746                         < 1026000000 925000 >,
 747                         < 1134000000 937500 >,
 748                         < 1242000000 950000 >,
 749                         < 1350000000 962500 >,
 750                         < 1458000000 975000 >,
 751                         < 1512000000 987500 >;
 752         };
 753
 754         kraitcc: clock-controller {
 755                 compatible = "qcom,krait-cc-v1";
 756                 #clock-cells = <1>;
 757         };
 758
 759         clocks {
 760                 sleep_clk: sleep_clk {
 761                         compatible = "fixed-clock";
 762                         clock-frequency = <32768>;
 763                         #clock-cells = <0>;
 764                 };
 765         };
 766
 767         clocks {
 768                 cxo_board {
 769                         compatible = "fixed-clock";
 770                         #clock-cells = <0>;
 771                         clock-frequency = <19200000>;
 772                 };
 773
 774                 pxo_board {
 775                         compatible = "fixed-clock";
 776                         #clock-cells = <0>;
 777                         clock-frequency = <27000000>;
 778                 };
 779
 780                 sleep_clk {
 781                         compatible = "fixed-clock";
 782                         #clock-cells = <0>;
 783                         clock-frequency = <32768>;
 784                 };
 785         };
 786
 787         firmware {
 788                 compatible = "simple-bus";
 789
 790                 scm {
 791                         compatible = "qcom,scm";
 792                 };
 793         };
 794
 795         soc: soc {
 796                 #address-cells = <1>;
 797                 #size-cells = <1>;
 798                 ranges;
 799                 compatible = "simple-bus";
 800
 801                 tlmm_pinmux: pinctrl@800000 {
 802                         compatible = "qcom,apq8064-pinctrl";
 803                         reg = <0x800000 0x4000>;
 804
 805                         gpio-controller;
 806                         #gpio-cells = <2>;
 807                         interrupt-controller;
 808                         #interrupt-cells = <2>;
 809                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 810
 811                         pinctrl-names = "default";
 812                         pinctrl-0 = <&ps_hold>;
 813
 814                         sdc4_gpios: sdc4-gpios {
 815                                 pios {
 816                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 817                                         function = "sdc4";
 818                                 };
 819                         };
 820
 821                         hdmi_pinctrl: hdmi-pinctrl {
 822                                 mux1 {
 823                                         pins = "gpio69", "gpio70", "gpio71";
 824                                         function = "hdmi";
 825                                         bias-pull-up;
 826                                         drive-strength = <2>;
 827                                 };
 828                                 mux2 {
 829                                         pins = "gpio72";
 830                                         function = "hdmi";
 831                                         bias-pull-down;
 832                                         drive-strength = <16>;
 833                                 };
 834                         };
 835                         ps_hold: ps_hold {
 836                                 mux {
 837                                         pins = "gpio78";
 838                                         function = "ps_hold";
 839                                 };
 840                         };
 841
 842                         i2c1_pins: i2c1 {
 843                                 mux {
 844                                         pins = "gpio20", "gpio21";
 845                                         function = "gsbi1";
 846                                 };
 847                         };
 848
 849                         i2c3_pins: i2c3 {
 850                                 mux {
 851                                         pins = "gpio8", "gpio9";
 852                                         function = "gsbi3";
 853                                 };
 854                         };
 855
 856                         gsbi6_uart_2pins: gsbi6_uart_2pins {
 857                                 mux {
 858                                         pins = "gpio14", "gpio15";
 859                                         function = "gsbi6";
 860                                 };
 861                         };
 862
 863                         gsbi6_uart_4pins: gsbi6_uart_4pins {
 864                                 mux {
 865                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 866                                         function = "gsbi6";
 867                                 };
 868                         };
 869
 870                         gsbi7_uart_2pins: gsbi7_uart_2pins {
 871                                 mux {
 872                                         pins = "gpio82", "gpio83";
 873                                         function = "gsbi7";
 874                                 };
 875                         };
 876
 877                         gsbi7_uart_4pins: gsbi7_uart_4pins {
 878                                 mux {
 879                                         pins = "gpio82", "gpio83", "gpio84", "gpio85";
 880                                         function = "gsbi7";
 881                                 };
 882                         };
 883                 };
 884
 885                 sfpb_wrapper_mutex: syscon@1200000 {
 886                         compatible = "syscon";
 887                         reg = <0x01200000 0x8000>;
 888                 };
 889
 890                 intc: interrupt-controller@2000000 {
 891                         compatible = "qcom,msm-qgic2";
 892                         interrupt-controller;
 893                         #interrupt-cells = <3>;
 894                         reg = <0x02000000 0x1000>,
 895                               <0x02002000 0x1000>;
 896                 };
 897
 898                 timer@200a000 {
 899                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 900                         interrupts = <1 1 0x301>,
 901                                      <1 2 0x301>,
 902                                      <1 3 0x301>;
 903                         reg = <0x0200a000 0x100>;
 904                         clock-frequency = <27000000>,
 905                                           <32768>;
 906                         cpu-offset = <0x80000>;
 907                 };
 908
 909                 watchdog@208a038 {
 910                         compatible = "qcom,kpss-wdt-apq8064";
 911                         reg = <0x0208a038 0x40>;
 912                         clocks = <&sleep_clk>;
 913                         timeout-sec = <10>;
 914                 };
 915
 916                 acc0: clock-controller@2088000 {
 917                         compatible = "qcom,kpss-acc-v1";
 918                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 919                         clock-output-names = "acpu0_aux";
 920                 };
 921
 922                 acc1: clock-controller@2098000 {
 923                         compatible = "qcom,kpss-acc-v1";
 924                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 925                         clock-output-names = "acpu1_aux";
 926                 };
 927
 928                 acc2: clock-controller@20a8000 {
 929                         compatible = "qcom,kpss-acc-v1";
 930                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 931                         clock-output-names = "acpu2_aux";
 932                 };
 933
 934                 acc3: clock-controller@20b8000 {
 935                         compatible = "qcom,kpss-acc-v1";
 936                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 937                         clock-output-names = "acpu3_aux";
 938                 };
 939
 940                 saw0: power-controller@2089000 {
 941                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 942                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 943                         regulator;
 944                         regulator-name = "krait0";
 945                         regulator-always-on;
 946                         regulator-min-microvolt = <825000>;
 947                         regulator-max-microvolt = <1250000>;
 948                 };
 949
 950                 saw1: power-controller@2099000 {
 951                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 952                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 953                         regulator;
 954                         regulator-name = "krait1";
 955                         regulator-always-on;
 956                         regulator-min-microvolt = <825000>;
 957                         regulator-max-microvolt = <1250000>;
 958                 };
 959
 960                 saw2: power-controller@20a9000 {
 961                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 962                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 963                         regulator;
 964                         regulator-name = "krait2";
 965                         regulator-always-on;
 966                         regulator-min-microvolt = <825000>;
 967                         regulator-max-microvolt = <1250000>;
 968                 };
 969
 970                 saw3: power-controller@20b9000 {
 971                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 972                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 973                         regulator;
 974                         regulator-name = "krait3";
 975                         regulator-always-on;
 976                         regulator-min-microvolt = <825000>;
 977                         regulator-max-microvolt = <1250000>;
 978                 };
 979
 980                 gsbi1: gsbi@12440000 {
 981                         status = "disabled";
 982                         compatible = "qcom,gsbi-v1.0.0";
 983                         cell-index = <1>;
 984                         reg = <0x12440000 0x100>;
 985                         clocks = <&gcc GSBI1_H_CLK>;
 986                         clock-names = "iface";
 987                         #address-cells = <1>;
 988                         #size-cells = <1>;
 989                         ranges;
 990
 991                         syscon-tcsr = <&tcsr>;
 992
 993                         i2c1: i2c@12460000 {
 994                                 compatible = "qcom,i2c-qup-v1.1.1";
 995                                 pinctrl-0 = <&i2c1_pins>;
 996                                 pinctrl-names = "default";
 997                                 reg = <0x12460000 0x1000>;
 998                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 999                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
1000                                 clock-names = "core", "iface";
1001                                 #address-cells = <1>;
1002                                 #size-cells = <0>;
1003                         };
1004                 };
1005
1006                 gsbi2: gsbi@12480000 {
1007                         status = "disabled";
1008                         compatible = "qcom,gsbi-v1.0.0";
1009                         cell-index = <2>;
1010                         reg = <0x12480000 0x100>;
1011                         clocks = <&gcc GSBI2_H_CLK>;
1012                         clock-names = "iface";
1013                         #address-cells = <1>;
1014                         #size-cells = <1>;
1015                         ranges;
1016
1017                         syscon-tcsr = <&tcsr>;
1018
1019                         i2c2: i2c@124a0000 {
1020                                 compatible = "qcom,i2c-qup-v1.1.1";
1021                                 reg = <0x124a0000 0x1000>;
1022                                 interrupts = <0 196 IRQ_TYPE_NONE>;
1023                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
1024                                 clock-names = "core", "iface";
1025                                 #address-cells = <1>;
1026                                 #size-cells = <0>;
1027                         };
1028                 };
1029
1030                 gsbi3: gsbi@16200000 {
1031                         status = "disabled";
1032                         compatible = "qcom,gsbi-v1.0.0";
1033                         cell-index = <3>;
1034                         reg = <0x16200000 0x100>;
1035                         clocks = <&gcc GSBI3_H_CLK>;
1036                         clock-names = "iface";
1037                         #address-cells = <1>;
1038                         #size-cells = <1>;
1039                         ranges;
1040                         i2c3: i2c@16280000 {
1041                                 compatible = "qcom,i2c-qup-v1.1.1";
1042                                 pinctrl-0 = <&i2c3_pins>;
1043                                 pinctrl-names = "default";
1044                                 reg = <0x16280000 0x1000>;
1045                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
1046                                 clocks = <&gcc GSBI3_QUP_CLK>,
1047                                          <&gcc GSBI3_H_CLK>;
1048                                 clock-names = "core", "iface";
1049                         };
1050                 };
1051
1052                 gsbi5: gsbi@1a200000 {
1053                         status = "disabled";
1054                         compatible = "qcom,gsbi-v1.0.0";
1055                         cell-index = <5>;
1056                         reg = <0x1a200000 0x03>;
1057                         clocks = <&gcc GSBI5_H_CLK>;
1058                         clock-names = "iface";
1059                         #address-cells = <1>;
1060                         #size-cells = <1>;
1061                         ranges;
1062
1063                         gsbi5_serial: serial@1a240000 {
1064                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1065                                 reg = <0x1a240000 0x100>,
1066                                       <0x1a200000 0x03>;
1067                                 interrupts = <0 154 0x0>;
1068                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1069                                 clock-names = "core", "iface";
1070                                 status = "disabled";
1071                         };
1072                 };
1073
1074                 gsbi6: gsbi@16500000 {
1075                         status = "disabled";
1076                         compatible = "qcom,gsbi-v1.0.0";
1077                         cell-index = <6>;
1078                         reg = <0x16500000 0x03>;
1079                         clocks = <&gcc GSBI6_H_CLK>;
1080                         clock-names = "iface";
1081                         #address-cells = <1>;
1082                         #size-cells = <1>;
1083                         ranges;
1084                         syscon-tcsr = <&tcsr>;
1085
1086                         gsbi6_serial: serial@16540000 {
1087                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1088                                 reg = <0x16540000 0x100>,
1089                                       <0x16500000 0x03>;
1090                                 interrupts = <0 156 0x0>;
1091                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
1092                                 clock-names = "core", "iface";
1093
1094                                 qcom,rx-crci = <11>;
1095                                 qcom,tx-crci = <6>;
1096
1097                                 dmas = <&adm 6>, <&adm 7>;
1098                                 dma-names = "rx", "tx";
1099
1100                                 status = "disabled";
1101                         };
1102                 };
1103
1104                 gsbi7: gsbi@16600000 {
1105                         status = "disabled";
1106                         compatible = "qcom,gsbi-v1.0.0";
1107                         cell-index = <7>;
1108                         reg = <0x16600000 0x100>;
1109                         clocks = <&gcc GSBI7_H_CLK>;
1110                         clock-names = "iface";
1111                         #address-cells = <1>;
1112                         #size-cells = <1>;
1113                         ranges;
1114                         syscon-tcsr = <&tcsr>;
1115
1116                         gsbi7_serial: serial@16640000 {
1117                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1118                                 reg = <0x16640000 0x1000>,
1119                                       <0x16600000 0x1000>;
1120                                 interrupts = <0 158 0x0>;
1121                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
1122                                 clock-names = "core", "iface";
1123                                 status = "disabled";
1124                         };
1125                 };
1126
1127                 rng@1a500000 {
1128                         compatible = "qcom,prng";
1129                         reg = <0x1a500000 0x200>;
1130                         clocks = <&gcc PRNG_CLK>;
1131                         clock-names = "core";
1132                 };
1133
1134                 qcom,ssbi@500000 {
1135                         compatible = "qcom,ssbi";
1136                         reg = <0x00500000 0x1000>;
1137                         qcom,controller-type = "pmic-arbiter";
1138
1139                         pmicintc: pmic@0 {
1140                                 compatible = "qcom,pm8921";
1141                                 interrupt-parent = <&tlmm_pinmux>;
1142                                 interrupts = <74 8>;
1143                                 #interrupt-cells = <2>;
1144                                 interrupt-controller;
1145                                 #address-cells = <1>;
1146                                 #size-cells = <0>;
1147
1148                                 pm8921_gpio: gpio@150 {
1149
1150                                         compatible = "qcom,pm8921-gpio",
1151                                                      "qcom,ssbi-gpio";
1152                                         reg = <0x150>;
1153                                         interrupts = <192 1>, <193 1>, <194 1>,
1154                                                      <195 1>, <196 1>, <197 1>,
1155                                                      <198 1>, <199 1>, <200 1>,
1156                                                      <201 1>, <202 1>, <203 1>,
1157                                                      <204 1>, <205 1>, <206 1>,
1158                                                      <207 1>, <208 1>, <209 1>,
1159                                                      <210 1>, <211 1>, <212 1>,
1160                                                      <213 1>, <214 1>, <215 1>,
1161                                                      <216 1>, <217 1>, <218 1>,
1162                                                      <219 1>, <220 1>, <221 1>,
1163                                                      <222 1>, <223 1>, <224 1>,
1164                                                      <225 1>, <226 1>, <227 1>,
1165                                                      <228 1>, <229 1>, <230 1>,
1166                                                      <231 1>, <232 1>, <233 1>,
1167                                                      <234 1>, <235 1>;
1168
1169                                         gpio-controller;
1170                                         #gpio-cells = <2>;
1171
1172                                 };
1173
1174                                 pm8921_mpps: mpps@50 {
1175                                         compatible = "qcom,pm8921-mpp",
1176                                                      "qcom,ssbi-mpp";
1177                                         reg = <0x50>;
1178                                         gpio-controller;
1179                                         #gpio-cells = <2>;
1180                                         interrupts =
1181                                         <128 1>, <129 1>, <130 1>, <131 1>,
1182                                         <132 1>, <133 1>, <134 1>, <135 1>,
1183                                         <136 1>, <137 1>, <138 1>, <139 1>;
1184                                 };
1185
1186                                 rtc@11d {
1187                                         compatible = "qcom,pm8921-rtc";
1188                                         interrupt-parent = <&pmicintc>;
1189                                         interrupts = <39 1>;
1190                                         reg = <0x11d>;
1191                                         allow-set-time;
1192                                 };
1193
1194                                 pwrkey@1c {
1195                                         compatible = "qcom,pm8921-pwrkey";
1196                                         reg = <0x1c>;
1197                                         interrupt-parent = <&pmicintc>;
1198                                         interrupts = <50 1>, <51 1>;
1199                                         debounce = <15625>;
1200                                         pull-up;
1201                                 };
1202                         };
1203                 };
1204
1205                 qfprom: qfprom@00700000 {
1206                         compatible      = "qcom,qfprom";
1207                         reg             = <0x00700000 0x1000>;
1208                         #address-cells  = <1>;
1209                         #size-cells     = <1>;
1210                         ranges;
1211                         tsens_calib: calib {
1212                                 reg = <0x404 0x10>;
1213                         };
1214                         tsens_backup: backup_calib {
1215                                 reg = <0x414 0x10>;
1216                         };
1217                 };
1218
1219                 gcc: clock-controller@900000 {
1220                         compatible = "qcom,gcc-apq8064";
1221                         reg = <0x00900000 0x4000>;
1222                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1223                         nvmem-cell-names = "calib", "calib_backup";
1224                         qcom,tsens-slopes = <1176 1176 1154 1176 1111
1225                                 1132 1132 1199 1132 1199 1132>;
1226                         #clock-cells = <1>;
1227                         #reset-cells = <1>;
1228                         #thermal-sensor-cells = <1>;
1229                 };
1230
1231                 lcc: clock-controller@28000000 {
1232                         compatible = "qcom,lcc-apq8064";
1233                         reg = <0x28000000 0x1000>;
1234                         #clock-cells = <1>;
1235                         #reset-cells = <1>;
1236                 };
1237
1238                 mmcc: clock-controller@4000000 {
1239                         compatible = "qcom,mmcc-apq8064";
1240                         reg = <0x4000000 0x1000>;
1241                         #clock-cells = <1>;
1242                         #reset-cells = <1>;
1243                 };
1244
1245                 l2cc: clock-controller@2011000 {
1246                         compatible      = "syscon";
1247                         reg             = <0x2011000 0x1000>;
1248                 };
1249
1250                 rpm@108000 {
1251                         compatible      = "qcom,rpm-apq8064";
1252                         reg             = <0x108000 0x1000>;
1253                         qcom,ipc        = <&l2cc 0x8 2>;
1254
1255                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
1256                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
1257                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
1258                         interrupt-names = "ack", "err", "wakeup";
1259
1260                         rpmcc: clock-controller {
1261                                 compatible      = "qcom,rpmcc-apq8064", "qcom,rpmcc";
1262                                 #clock-cells = <1>;
1263                         };
1264
1265                         regulators {
1266                                 compatible = "qcom,rpm-pm8921-regulators";
1267
1268                                 pm8921_s1: s1 {};
1269                                 pm8921_s2: s2 {};
1270                                 pm8921_s3: s3 {};
1271                                 pm8921_s4: s4 {};
1272                                 pm8921_s7: s7 {};
1273                                 pm8921_s8: s8 {};
1274
1275                                 pm8921_l1: l1 {};
1276                                 pm8921_l2: l2 {};
1277                                 pm8921_l3: l3 {};
1278                                 pm8921_l4: l4 {};
1279                                 pm8921_l5: l5 {};
1280                                 pm8921_l6: l6 {};
1281                                 pm8921_l7: l7 {};
1282                                 pm8921_l8: l8 {};
1283                                 pm8921_l9: l9 {};
1284                                 pm8921_l10: l10 {};
1285                                 pm8921_l11: l11 {};
1286                                 pm8921_l12: l12 {};
1287                                 pm8921_l14: l14 {};
1288                                 pm8921_l15: l15 {};
1289                                 pm8921_l16: l16 {};
1290                                 pm8921_l17: l17 {};
1291                                 pm8921_l18: l18 {};
1292                                 pm8921_l21: l21 {};
1293                                 pm8921_l22: l22 {};
1294                                 pm8921_l23: l23 {};
1295                                 pm8921_l24: l24 {};
1296                                 pm8921_l25: l25 {};
1297                                 pm8921_l26: l26 {};
1298                                 pm8921_l27: l27 {};
1299                                 pm8921_l28: l28 {};
1300                                 pm8921_l29: l29 {};
1301
1302                                 pm8921_lvs1: lvs1 {};
1303                                 pm8921_lvs2: lvs2 {};
1304                                 pm8921_lvs3: lvs3 {};
1305                                 pm8921_lvs4: lvs4 {};
1306                                 pm8921_lvs5: lvs5 {};
1307                                 pm8921_lvs6: lvs6 {};
1308                                 pm8921_lvs7: lvs7 {};
1309
1310                                 pm8921_usb_switch: usb-switch {};
1311
1312                                 pm8921_hdmi_switch: hdmi-switch {
1313                                         bias-pull-down;
1314                                 };
1315
1316                                 pm8921_ncp: ncp {};
1317                         };
1318                 };
1319
1320                 usb1_phy: phy@12500000 {
1321                         compatible      = "qcom,usb-otg-ci";
1322                         reg             = <0x12500000 0x400>;
1323                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1324                         status          = "disabled";
1325                         dr_mode         = "host";
1326
1327                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
1328                                           <&gcc USB_HS1_H_CLK>;
1329                         clock-names     = "core", "iface";
1330
1331                         resets          = <&gcc USB_HS1_RESET>;
1332                         reset-names     = "link";
1333                 };
1334
1335                 usb3_phy: phy@12520000 {
1336                         compatible      = "qcom,usb-otg-ci";
1337                         reg             = <0x12520000 0x400>;
1338                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
1339                         status          = "disabled";
1340                         dr_mode         = "host";
1341
1342                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
1343                                           <&gcc USB_HS3_H_CLK>;
1344                         clock-names     = "core", "iface";
1345
1346                         resets          = <&gcc USB_HS3_RESET>;
1347                         reset-names     = "link";
1348                 };
1349
1350                 usb4_phy: phy@12530000 {
1351                         compatible      = "qcom,usb-otg-ci";
1352                         reg             = <0x12530000 0x400>;
1353                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
1354                         status          = "disabled";
1355                         dr_mode         = "host";
1356
1357                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
1358                                           <&gcc USB_HS4_H_CLK>;
1359                         clock-names     = "core", "iface";
1360
1361                         resets          = <&gcc USB_HS4_RESET>;
1362                         reset-names     = "link";
1363                 };
1364
1365                 gadget1: gadget@12500000 {
1366                         compatible      = "qcom,ci-hdrc";
1367                         reg             = <0x12500000 0x400>;
1368                         status          = "disabled";
1369                         dr_mode         = "peripheral";
1370                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1371                         usb-phy         = <&usb1_phy>;
1372                 };
1373
1374                 usb1: usb@12500000 {
1375                         compatible      = "qcom,ehci-host";
1376                         reg             = <0x12500000 0x400>;
1377                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1378                         status          = "disabled";
1379                         usb-phy         = <&usb1_phy>;
1380                 };
1381
1382                 usb3: usb@12520000 {
1383                         compatible      = "qcom,ehci-host";
1384                         reg             = <0x12520000 0x400>;
1385                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
1386                         status          = "disabled";
1387                         usb-phy         = <&usb3_phy>;
1388                 };
1389
1390                 usb4: usb@12530000 {
1391                         compatible      = "qcom,ehci-host";
1392                         reg             = <0x12530000 0x400>;
1393                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
1394                         status          = "disabled";
1395                         usb-phy         = <&usb4_phy>;
1396                 };
1397
1398                 sata_phy0: phy@1b400000 {
1399                         compatible      = "qcom,apq8064-sata-phy";
1400                         status          = "disabled";
1401                         reg             = <0x1b400000 0x200>;
1402                         reg-names       = "phy_mem";
1403                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
1404                         clock-names     = "cfg";
1405                         #phy-cells      = <0>;
1406                 };
1407
1408                 sata0: sata@29000000 {
1409                         compatible              = "generic-ahci";
1410                         status                  = "disabled";
1411                         reg                     = <0x29000000 0x180>;
1412                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
1413
1414                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
1415                                                 <&gcc SATA_H_CLK>,
1416                                                 <&gcc SATA_A_CLK>,
1417                                                 <&gcc SATA_RXOOB_CLK>,
1418                                                 <&gcc SATA_PMALIVE_CLK>;
1419                         clock-names             = "slave_iface",
1420                                                 "iface",
1421                                                 "bus",
1422                                                 "rxoob",
1423                                                 "core_pmalive";
1424
1425                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
1426                                                 <&gcc SATA_PMALIVE_CLK>;
1427                         assigned-clock-rates    = <100000000>, <100000000>;
1428
1429                         phys                    = <&sata_phy0>;
1430                         phy-names               = "sata-phy";
1431                 };
1432
1433                 /* Temporary fixed regulator */
1434                 sdcc1bam:dma@12402000{
1435                         compatible = "qcom,bam-v1.3.0";
1436                         reg = <0x12402000 0x8000>;
1437                         interrupts = <0 98 0>;
1438                         clocks = <&gcc SDC1_H_CLK>;
1439                         clock-names = "bam_clk";
1440                         #dma-cells = <1>;
1441                         qcom,ee = <0>;
1442                 };
1443
1444                 sdcc3bam:dma@12182000{
1445                         compatible = "qcom,bam-v1.3.0";
1446                         reg = <0x12182000 0x8000>;
1447                         interrupts = <0 96 0>;
1448                         clocks = <&gcc SDC3_H_CLK>;
1449                         clock-names = "bam_clk";
1450                         #dma-cells = <1>;
1451                         qcom,ee = <0>;
1452                 };
1453
1454                 sdcc4bam:dma@121c2000{
1455                         compatible = "qcom,bam-v1.3.0";
1456                         reg = <0x121c2000 0x8000>;
1457                         interrupts = <0 95 0>;
1458                         clocks = <&gcc SDC4_H_CLK>;
1459                         clock-names = "bam_clk";
1460                         #dma-cells = <1>;
1461                         qcom,ee = <0>;
1462                 };
1463
1464                 amba {
1465                         compatible = "arm,amba-bus";
1466                         #address-cells = <1>;
1467                         #size-cells = <1>;
1468                         ranges;
1469                         sdcc1: sdcc@12400000 {
1470                                 status          = "disabled";
1471                                 compatible      = "arm,pl18x", "arm,primecell";
1472                                 arm,primecell-periphid = <0x00051180>;
1473                                 reg             = <0x12400000 0x2000>;
1474                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1475                                 interrupt-names = "cmd_irq";
1476                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1477                                 clock-names     = "mclk", "apb_pclk";
1478                                 bus-width       = <8>;
1479                                 max-frequency   = <96000000>;
1480                                 non-removable;
1481                                 cap-sd-highspeed;
1482                                 cap-mmc-highspeed;
1483                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1484                                 dma-names = "tx", "rx";
1485                         };
1486
1487                         sdcc3: sdcc@12180000 {
1488                                 compatible      = "arm,pl18x", "arm,primecell";
1489                                 arm,primecell-periphid = <0x00051180>;
1490                                 status          = "disabled";
1491                                 reg             = <0x12180000 0x2000>;
1492                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1493                                 interrupt-names = "cmd_irq";
1494                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1495                                 clock-names     = "mclk", "apb_pclk";
1496                                 bus-width       = <4>;
1497                                 cap-sd-highspeed;
1498                                 cap-mmc-highspeed;
1499                                 max-frequency   = <192000000>;
1500                                 no-1-8-v;
1501                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1502                                 dma-names = "tx", "rx";
1503                         };
1504
1505                         sdcc4: sdcc@121c0000 {
1506                                 compatible      = "arm,pl18x", "arm,primecell";
1507                                 arm,primecell-periphid = <0x00051180>;
1508                                 status          = "disabled";
1509                                 reg             = <0x121c0000 0x2000>;
1510                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1511                                 interrupt-names = "cmd_irq";
1512                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1513                                 clock-names     = "mclk", "apb_pclk";
1514                                 bus-width       = <4>;
1515                                 cap-sd-highspeed;
1516                                 cap-mmc-highspeed;
1517                                 max-frequency   = <48000000>;
1518                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1519                                 dma-names = "tx", "rx";
1520                                 pinctrl-names = "default";
1521                                 pinctrl-0 = <&sdc4_gpios>;
1522                         };
1523                 };
1524
1525                 adm: dma@18320000 {
1526                         compatible = "qcom,adm";
1527                         reg = <0x18320000 0xE0000>;
1528                         interrupts = <GIC_SPI 171 IRQ_TYPE_NONE>;
1529                         #dma-cells = <1>;
1530
1531                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1532                         clock-names = "core", "iface";
1533
1534                         resets = <&gcc ADM0_RESET>,
1535                                  <&gcc ADM0_PBUS_RESET>,
1536                                  <&gcc ADM0_C0_RESET>,
1537                                  <&gcc ADM0_C1_RESET>,
1538                                  <&gcc ADM0_C2_RESET>;
1539                         reset-names = "clk", "pbus", "c0", "c1", "c2";
1540                         qcom,ee = <1>;
1541
1542                         status = "disabled";
1543                 };
1544
1545                 tcsr: syscon@1a400000 {
1546                         compatible = "qcom,tcsr-apq8064", "syscon";
1547                         reg = <0x1a400000 0x100>;
1548                 };
1549
1550                 pcie: pci@1b500000 {
1551                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1552                         reg = <0x1b500000 0x1000
1553                                0x1b502000 0x80
1554                                0x1b600000 0x100
1555                                0x0ff00000 0x100000>;
1556                         reg-names = "dbi", "elbi", "parf", "config";
1557                         device_type = "pci";
1558                         linux,pci-domain = <0>;
1559                         bus-range = <0x00 0xff>;
1560                         num-lanes = <1>;
1561                         #address-cells = <3>;
1562                         #size-cells = <2>;
1563                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
1564                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1565                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1566                         interrupt-names = "msi";
1567                         #interrupt-cells = <1>;
1568                         interrupt-map-mask = <0 0 0 0x7>;
1569                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1570                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1571                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1572                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1573                         clocks = <&gcc PCIE_A_CLK>,
1574                                  <&gcc PCIE_H_CLK>,
1575                                  <&gcc PCIE_PHY_REF_CLK>;
1576                         clock-names = "core", "iface", "phy";
1577                         resets = <&gcc PCIE_ACLK_RESET>,
1578                                  <&gcc PCIE_HCLK_RESET>,
1579                                  <&gcc PCIE_POR_RESET>,
1580                                  <&gcc PCIE_PCI_RESET>,
1581                                  <&gcc PCIE_PHY_RESET>;
1582                         reset-names = "axi", "ahb", "por", "pci", "phy";
1583                         status = "disabled";
1584                 };
1585
1586                 pil_q6v4: pil@28800000 {
1587                         compatible      = "qcom,tz-pil", "qcom,apq8064-tz-pil";
1588                         qcom,firmware-name = "q6";
1589                         reg             = <0x28800000 0x100>;
1590                         reg-names       = "qdsp6_base";
1591                         qcom,pas-id             = <1>; /* PAS_Q6 */
1592                 };
1593
1594                 smd {
1595                         compatible = "qcom,smd";
1596                         adsp_a11 {
1597                                 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
1598                                 qcom,ipc = <&l2cc 8 15>;
1599                                 qcom,smd-edge = <1>;
1600                                 qcom,remote-pid = <0x2>;
1601                                 q6_requests {
1602                                         compatible      = "qcom,apr";
1603                                         qcom,smd-channels = "apr_audio_svc";
1604                                         rproc = <&pil_q6v4>;
1605                                 };
1606                         };
1607                 };
1608
1609                 dai_fe: dai_fe {
1610                         compatible      = "qcom,msm-dai-fe";
1611                         #sound-dai-cells = <0>;
1612                 };
1613
1614                 hdmi_dai: dai_hdmi {
1615                         compatible = "qcom,msm-dai-q6-hdmi";
1616                         #sound-dai-cells = <0>;
1617                 };
1618
1619                 hdmi_codec: codec_hdmi {
1620                         compatible = "linux,hdmi-audio";
1621                         #sound-dai-cells = <0>;
1622                 };
1623
1624                 q6_pcm: msm_pcm {
1625                         compatible = "qcom,msm-pcm-dsp";
1626                         #sound-dai-cells = <0>;
1627                 };
1628
1629                 q6_route: msm_pcm_routing {
1630                         compatible = "qcom,msm-pcm-routing";
1631                         #sound-dai-cells = <0>;
1632                 };
1633
1634                 snd {
1635                         compatible      = "qcom,snd-apq8064";
1636                 };
1637
1638
1639                 hdmi: qcom,hdmi-tx@4a00000 {
1640                         compatible = "qcom,hdmi-tx-8960";
1641                         reg-names = "core_physical";
1642                         reg = <0x04a00000 0x1000>;
1643                         interrupts = <GIC_SPI 79 0>;
1644                         clock-names =
1645                             "core_clk",
1646                             "master_iface_clk",
1647                             "slave_iface_clk";
1648                         clocks =
1649                             <&mmcc HDMI_APP_CLK>,
1650                             <&mmcc HDMI_M_AHB_CLK>,
1651                             <&mmcc HDMI_S_AHB_CLK>;
1652                         qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
1653                         qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
1654                         qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
1655                         pinctrl-names = "default";
1656                         pinctrl-0 = <&hdmi_pinctrl>;
1657                 };
1658
1659                 gpu: qcom,adreno-3xx@4300000 {
1660                         compatible = "qcom,adreno-3xx";
1661                         reg = <0x04300000 0x20000>;
1662                         reg-names = "kgsl_3d0_reg_memory";
1663                         interrupts = <GIC_SPI 80 0>;
1664                         interrupt-names = "kgsl_3d0_irq";
1665                         clock-names =
1666                             "core_clk",
1667                             "iface_clk",
1668                             "mem_clk",
1669                             "mem_iface_clk";
1670                         clocks =
1671                             <&mmcc GFX3D_CLK>,
1672                             <&mmcc GFX3D_AHB_CLK>,
1673                             <&mmcc GFX3D_AXI_CLK>,
1674                             <&mmcc MMSS_IMEM_AHB_CLK>;
1675                         qcom,chipid = <0x03020002>;
1676
1677                          iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1678                                    &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1679                                    &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1680                                    &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
1681
1682                         qcom,gpu-pwrlevels {
1683                                 compatible = "qcom,gpu-pwrlevels";
1684                                 qcom,gpu-pwrlevel@0 {
1685                                         qcom,gpu-freq = <450000000>;
1686                                 };
1687                                 qcom,gpu-pwrlevel@1 {
1688                                         qcom,gpu-freq = <27000000>;
1689                                 };
1690                         };
1691                 };
1692
1693                 mdp: qcom,mdp@5100000 {
1694                         compatible = "qcom,mdp";
1695                         reg = <0x05100000 0xf0000>;
1696                         interrupts = <GIC_SPI 75 0>;
1697                         connectors = <&hdmi>;
1698                         gpus = <&gpu>;
1699                         clock-names =
1700                             "core_clk",
1701                             "iface_clk",
1702                             "lut_clk",
1703                             "src_clk",
1704                             "hdmi_clk",
1705                             "mdp_clk",
1706                             "mdp_axi_clk";
1707                         clocks =
1708                             <&mmcc MDP_CLK>,
1709                             <&mmcc MDP_AHB_CLK>,
1710                             <&mmcc MDP_LUT_CLK>,
1711                             <&mmcc TV_SRC>,
1712                             <&mmcc HDMI_TV_CLK>,
1713                             <&mmcc MDP_TV_CLK>,
1714                             <&mmcc MDP_AXI_CLK>;
1715
1716                         iommus = <&mdp_port0 0 2
1717                                   &mdp_port1 0 2>;
1718                 };
1719
1720                 mdp_port0: qcom,iommu@7500000 {
1721                         compatible = "qcom,iommu-v0";
1722                         #iommu-cells = <2>;
1723                         clock-names =
1724                             "smmu_pclk",
1725                             "iommu_clk";
1726                         clocks =
1727                             <&mmcc SMMU_AHB_CLK>,
1728                             <&mmcc MDP_AXI_CLK>;
1729                         reg = <0x07500000 0x100000>;
1730                         interrupts =
1731                             <GIC_SPI 63 0>,
1732                             <GIC_SPI 64 0>;
1733                         ncb = <2>;
1734                 };
1735
1736                 mdp_port1: qcom,iommu@7600000 {
1737                         compatible = "qcom,iommu";
1738                         #iommu-cells = <2>;
1739                         clock-names =
1740                             "smmu_pclk",
1741                             "iommu_clk";
1742                         clocks =
1743                             <&mmcc SMMU_AHB_CLK>,
1744                             <&mmcc MDP_AXI_CLK>;
1745                         reg = <0x07600000 0x100000>;
1746                         interrupts =
1747                             <GIC_SPI 61 0>,
1748                             <GIC_SPI 62 0>;
1749                         ncb = <2>;
1750                 };
1751
1752                 gfx3d: qcom,iommu@7c00000 {
1753                         compatible = "qcom,iommu-v0";
1754                         #iommu-cells = <16>;
1755                         clock-names =
1756                             "smmu_pclk",
1757                             "iommu_clk";
1758                         clocks =
1759                             <&mmcc SMMU_AHB_CLK>,
1760                             <&mmcc GFX3D_AXI_CLK>;
1761                         reg = <0x07c00000 0x100000>;
1762                         interrupts =
1763                             <GIC_SPI 69 0>,
1764                             <GIC_SPI 70 0>;
1765                         ncb = <3>;
1766                 };
1767
1768                 gfx3d1: qcom,iommu@7d00000 {
1769                         compatible = "qcom,iommu-v0";
1770                         #iommu-cells = <16>;
1771                         clock-names =
1772                             "smmu_pclk",
1773                             "iommu_clk";
1774                         clocks =
1775                             <&mmcc SMMU_AHB_CLK>,
1776                             <&mmcc GFX3D_AXI_CLK>;
1777                         reg = <0x07d00000 0x100000>;
1778                         interrupts =
1779                             <GIC_SPI 210 0>,
1780                             <GIC_SPI 211 0>;
1781                         ncb = <3>;
1782                 };
1783         };
1784 };
1785
1786 #include "qcom-apq8064-coresight.dtsi"