3 #include "skeleton.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "Qualcomm APQ8064";
14 compatible = "qcom,apq8064";
15 interrupt-parent = <&intc>;
22 smem_region: smem@80000000 {
23 reg = <0x80000000 0x200000>;
33 compatible = "qcom,krait";
34 enable-method = "qcom,kpss-acc-v1";
37 next-level-cache = <&L2>;
40 cpu-idle-states = <&CPU_SPC>;
41 clocks = <&kraitcc 0>, <&kraitcc 4>;
42 clock-names = "cpu", "l2";
43 clock-latency = <100000>;
44 cooling-min-level = <0>;
45 cooling-max-level = <7>;
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
54 next-level-cache = <&L2>;
57 cpu-idle-states = <&CPU_SPC>;
58 clocks = <&kraitcc 1>, <&kraitcc 4>;
59 clock-names = "cpu", "l2";
60 clock-latency = <100000>;
61 cooling-min-level = <0>;
62 cooling-max-level = <7>;
67 compatible = "qcom,krait";
68 enable-method = "qcom,kpss-acc-v1";
71 next-level-cache = <&L2>;
74 cpu-idle-states = <&CPU_SPC>;
75 clocks = <&kraitcc 2>, <&kraitcc 4>;
76 clock-names = "cpu", "l2";
77 clock-latency = <100000>;
78 cooling-min-level = <0>;
79 cooling-max-level = <7>;
84 compatible = "qcom,krait";
85 enable-method = "qcom,kpss-acc-v1";
88 next-level-cache = <&L2>;
91 cpu-idle-states = <&CPU_SPC>;
92 clocks = <&kraitcc 3>, <&kraitcc 4>;
93 clock-names = "cpu", "l2";
94 clock-latency = <100000>;
95 cooling-min-level = <0>;
96 cooling-max-level = <7>;
101 compatible = "cache";
106 qcom,l2-rates = <384000000 972000000 1188000000>;
111 compatible = "qcom,idle-state-spc",
113 entry-latency-us = <400>;
114 exit-latency-us = <900>;
115 min-residency-us = <3000>;
122 polling-delay-passive = <250>;
123 polling-delay = <1000>;
125 thermal-sensors = <&tsens 7>;
129 temperature = <75000>;
134 temperature = <110000>;
142 trip = <&cpu_alert0>;
143 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149 polling-delay-passive = <250>;
150 polling-delay = <1000>;
152 thermal-sensors = <&tsens 8>;
156 temperature = <75000>;
161 temperature = <110000>;
169 trip = <&cpu_alert1>;
170 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
176 polling-delay-passive = <250>;
177 polling-delay = <1000>;
179 thermal-sensors = <&tsens 9>;
183 temperature = <75000>;
188 temperature = <110000>;
196 trip = <&cpu_alert2>;
197 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
203 polling-delay-passive = <250>;
204 polling-delay = <1000>;
206 thermal-sensors = <&tsens 10>;
210 temperature = <75000>;
215 temperature = <110000>;
223 trip = <&cpu_alert3>;
224 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
232 polling-delay-passive = <250>;
233 polling-delay = <1000>;
235 thermal-sensors = <&gcc 7>;
239 temperature = <75000>;
244 temperature = <95000>;
252 polling-delay-passive = <250>;
253 polling-delay = <1000>;
255 thermal-sensors = <&gcc 8>;
259 temperature = <75000>;
264 temperature = <95000>;
272 polling-delay-passive = <250>;
273 polling-delay = <1000>;
275 thermal-sensors = <&gcc 9>;
279 temperature = <75000>;
284 temperature = <95000>;
292 polling-delay-passive = <250>;
293 polling-delay = <1000>;
295 thermal-sensors = <&gcc 10>;
299 temperature = <75000>;
304 temperature = <95000>;
313 compatible = "qcom,krait-pmu";
314 interrupts = <1 10 0x304>;
319 compatible = "fixed-clock";
321 clock-frequency = <19200000>;
325 compatible = "fixed-clock";
327 clock-frequency = <27000000>;
331 compatible = "fixed-clock";
333 clock-frequency = <32768>;
337 sfpb_mutex: hwmutex {
338 compatible = "qcom,sfpb-mutex";
339 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
344 compatible = "qcom,smem";
345 memory-region = <&smem_region>;
347 hwlocks = <&sfpb_mutex 3>;
352 qcom,speed0-pvs0-bin-v0 =
353 < 384000000 950000 >,
354 < 486000000 975000 >,
355 < 594000000 1000000 >,
356 < 702000000 1025000 >,
357 < 810000000 1075000 >,
358 < 918000000 1100000 >,
359 < 1026000000 1125000 >,
360 < 1080000000 1175000 >,
361 < 1134000000 1175000 >,
362 < 1188000000 1200000 >,
363 < 1242000000 1200000 >,
364 < 1296000000 1225000 >,
365 < 1350000000 1225000 >,
366 < 1404000000 1237500 >,
367 < 1458000000 1237500 >,
368 < 1512000000 1250000 >;
370 qcom,speed0-pvs1-bin-v0 =
371 < 384000000 900000 >,
372 < 486000000 925000 >,
373 < 594000000 950000 >,
374 < 702000000 975000 >,
375 < 810000000 1025000 >,
376 < 918000000 1050000 >,
377 < 1026000000 1075000 >,
378 < 1080000000 1125000 >,
379 < 1134000000 1125000 >,
380 < 1188000000 1150000 >,
381 < 1242000000 1150000 >,
382 < 1296000000 1175000 >,
383 < 1350000000 1175000 >,
384 < 1404000000 1187500 >,
385 < 1458000000 1187500 >,
386 < 1512000000 1200000 >;
388 qcom,speed0-pvs3-bin-v0 =
389 < 384000000 850000 >,
390 < 486000000 875000 >,
391 < 594000000 900000 >,
392 < 702000000 925000 >,
393 < 810000000 975000 >,
394 < 918000000 1000000 >,
395 < 1026000000 1025000 >,
396 < 1080000000 1075000 >,
397 < 1134000000 1075000 >,
398 < 1188000000 1100000 >,
399 < 1242000000 1100000 >,
400 < 1296000000 1125000 >,
401 < 1350000000 1125000 >,
402 < 1404000000 1137500 >,
403 < 1458000000 1137500 >,
404 < 1512000000 1150000 >;
406 qcom,speed0-pvs4-bin-v0 =
407 < 384000000 850000 >,
408 < 486000000 875000 >,
409 < 594000000 900000 >,
410 < 702000000 925000 >,
411 < 810000000 962500 >,
412 < 918000000 975000 >,
413 < 1026000000 1000000 >,
414 < 1080000000 1050000 >,
415 < 1134000000 1050000 >,
416 < 1188000000 1075000 >,
417 < 1242000000 1075000 >,
418 < 1296000000 1100000 >,
419 < 1350000000 1100000 >,
420 < 1404000000 1112500 >,
421 < 1458000000 1112500 >,
422 < 1512000000 1125000 >;
424 qcom,speed1-pvs0-bin-v0 =
425 < 384000000 950000 >,
426 < 486000000 950000 >,
427 < 594000000 950000 >,
428 < 702000000 962500 >,
429 < 810000000 1000000 >,
430 < 918000000 1025000 >,
431 < 1026000000 1037500 >,
432 < 1134000000 1075000 >,
433 < 1242000000 1087500 >,
434 < 1350000000 1125000 >,
435 < 1458000000 1150000 >,
436 < 1566000000 1175000 >,
437 < 1674000000 1225000 >,
438 < 1728000000 1250000 >;
440 qcom,speed1-pvs1-bin-v0 =
441 < 384000000 950000 >,
442 < 486000000 950000 >,
443 < 594000000 950000 >,
444 < 702000000 962500 >,
445 < 810000000 975000 >,
446 < 918000000 1000000 >,
447 < 1026000000 1012500 >,
448 < 1134000000 1037500 >,
449 < 1242000000 1050000 >,
450 < 1350000000 1087500 >,
451 < 1458000000 1112500 >,
452 < 1566000000 1150000 >,
453 < 1674000000 1187500 >,
454 < 1728000000 1200000 >;
456 qcom,speed1-pvs2-bin-v0 =
457 < 384000000 925000 >,
458 < 486000000 925000 >,
459 < 594000000 925000 >,
460 < 702000000 925000 >,
461 < 810000000 937500 >,
462 < 918000000 950000 >,
463 < 1026000000 975000 >,
464 < 1134000000 1000000 >,
465 < 1242000000 1012500 >,
466 < 1350000000 1037500 >,
467 < 1458000000 1075000 >,
468 < 1566000000 1100000 >,
469 < 1674000000 1137500 >,
470 < 1728000000 1162500 >;
472 qcom,speed1-pvs3-bin-v0 =
473 < 384000000 900000 >,
474 < 486000000 900000 >,
475 < 594000000 900000 >,
476 < 702000000 900000 >,
477 < 810000000 900000 >,
478 < 918000000 925000 >,
479 < 1026000000 950000 >,
480 < 1134000000 975000 >,
481 < 1242000000 987500 >,
482 < 1350000000 1000000 >,
483 < 1458000000 1037500 >,
484 < 1566000000 1062500 >,
485 < 1674000000 1100000 >,
486 < 1728000000 1125000 >;
488 qcom,speed1-pvs4-bin-v0 =
489 < 384000000 875000 >,
490 < 486000000 875000 >,
491 < 594000000 875000 >,
492 < 702000000 875000 >,
493 < 810000000 887500 >,
494 < 918000000 900000 >,
495 < 1026000000 925000 >,
496 < 1134000000 950000 >,
497 < 1242000000 962500 >,
498 < 1350000000 975000 >,
499 < 1458000000 1000000 >,
500 < 1566000000 1037500 >,
501 < 1674000000 1075000 >,
502 < 1728000000 1100000 >;
504 qcom,speed1-pvs5-bin-v0 =
505 < 384000000 875000 >,
506 < 486000000 875000 >,
507 < 594000000 875000 >,
508 < 702000000 875000 >,
509 < 810000000 887500 >,
510 < 918000000 900000 >,
511 < 1026000000 925000 >,
512 < 1134000000 937500 >,
513 < 1242000000 950000 >,
514 < 1350000000 962500 >,
515 < 1458000000 987500 >,
516 < 1566000000 1012500 >,
517 < 1674000000 1050000 >,
518 < 1728000000 1075000 >;
520 qcom,speed1-pvs6-bin-v0 =
521 < 384000000 875000 >,
522 < 486000000 875000 >,
523 < 594000000 875000 >,
524 < 702000000 875000 >,
525 < 810000000 887500 >,
526 < 918000000 900000 >,
527 < 1026000000 925000 >,
528 < 1134000000 937500 >,
529 < 1242000000 950000 >,
530 < 1350000000 962500 >,
531 < 1458000000 975000 >,
532 < 1566000000 1000000 >,
533 < 1674000000 1025000 >,
534 < 1728000000 1050000 >;
536 qcom,speed2-pvs0-bin-v0 =
537 < 384000000 950000 >,
538 < 486000000 950000 >,
539 < 594000000 950000 >,
540 < 702000000 950000 >,
541 < 810000000 962500 >,
542 < 918000000 975000 >,
543 < 1026000000 1000000 >,
544 < 1134000000 1025000 >,
545 < 1242000000 1037500 >,
546 < 1350000000 1062500 >,
547 < 1458000000 1100000 >,
548 < 1566000000 1125000 >,
549 < 1674000000 1175000 >,
550 < 1782000000 1225000 >,
551 < 1890000000 1287500 >;
553 qcom,speed2-pvs1-bin-v0 =
554 < 384000000 925000 >,
555 < 486000000 925000 >,
556 < 594000000 925000 >,
557 < 702000000 925000 >,
558 < 810000000 937500 >,
559 < 918000000 950000 >,
560 < 1026000000 975000 >,
561 < 1134000000 1000000 >,
562 < 1242000000 1012500 >,
563 < 1350000000 1037500 >,
564 < 1458000000 1075000 >,
565 < 1566000000 1100000 >,
566 < 1674000000 1137500 >,
567 < 1782000000 1187500 >,
568 < 1890000000 1250000 >;
570 qcom,speed2-pvs2-bin-v0 =
571 < 384000000 900000 >,
572 < 486000000 900000 >,
573 < 594000000 900000 >,
574 < 702000000 900000 >,
575 < 810000000 912500 >,
576 < 918000000 925000 >,
577 < 1026000000 950000 >,
578 < 1134000000 975000 >,
579 < 1242000000 987500 >,
580 < 1350000000 1012500 >,
581 < 1458000000 1050000 >,
582 < 1566000000 1075000 >,
583 < 1674000000 1112500 >,
584 < 1782000000 1162500 >,
585 < 1890000000 1212500 >;
587 qcom,speed2-pvs3-bin-v0 =
588 < 384000000 900000 >,
589 < 486000000 900000 >,
590 < 594000000 900000 >,
591 < 702000000 900000 >,
592 < 810000000 900000 >,
593 < 918000000 912500 >,
594 < 1026000000 937500 >,
595 < 1134000000 962500 >,
596 < 1242000000 975000 >,
597 < 1350000000 1000000 >,
598 < 1458000000 1025000 >,
599 < 1566000000 1050000 >,
600 < 1674000000 1087500 >,
601 < 1782000000 1137500 >,
602 < 1890000000 1175000 >;
604 qcom,speed2-pvs4-bin-v0 =
605 < 384000000 875000 >,
606 < 486000000 875000 >,
607 < 594000000 875000 >,
608 < 702000000 875000 >,
609 < 810000000 887500 >,
610 < 918000000 900000 >,
611 < 1026000000 925000 >,
612 < 1134000000 950000 >,
613 < 1242000000 962500 >,
614 < 1350000000 975000 >,
615 < 1458000000 1000000 >,
616 < 1566000000 1037500 >,
617 < 1674000000 1075000 >,
618 < 1782000000 1112500 >,
619 < 1890000000 1150000 >;
621 qcom,speed2-pvs5-bin-v0 =
622 < 384000000 875000 >,
623 < 486000000 875000 >,
624 < 594000000 875000 >,
625 < 702000000 875000 >,
626 < 810000000 887500 >,
627 < 918000000 900000 >,
628 < 1026000000 925000 >,
629 < 1134000000 937500 >,
630 < 1242000000 950000 >,
631 < 1350000000 962500 >,
632 < 1458000000 987500 >,
633 < 1566000000 1012500 >,
634 < 1674000000 1050000 >,
635 < 1782000000 1087500 >,
636 < 1890000000 1125000 >;
638 qcom,speed2-pvs6-bin-v0 =
639 < 384000000 875000 >,
640 < 486000000 875000 >,
641 < 594000000 875000 >,
642 < 702000000 875000 >,
643 < 810000000 887500 >,
644 < 918000000 900000 >,
645 < 1026000000 925000 >,
646 < 1134000000 937500 >,
647 < 1242000000 950000 >,
648 < 1350000000 962500 >,
649 < 1458000000 975000 >,
650 < 1566000000 1000000 >,
651 < 1674000000 1025000 >,
652 < 1782000000 1062500 >,
653 < 1890000000 1100000 >;
655 qcom,speed14-pvs0-bin-v0 =
656 < 384000000 950000 >,
657 < 486000000 950000 >,
658 < 594000000 950000 >,
659 < 702000000 962500 >,
660 < 810000000 1000000 >,
661 < 918000000 1025000 >,
662 < 1026000000 1037500 >,
663 < 1134000000 1075000 >,
664 < 1242000000 1087500 >,
665 < 1350000000 1125000 >,
666 < 1458000000 1150000 >,
667 < 1512000000 1162500 >;
669 qcom,speed14-pvs1-bin-v0 =
670 < 384000000 950000 >,
671 < 486000000 950000 >,
672 < 594000000 950000 >,
673 < 702000000 962500 >,
674 < 810000000 975000 >,
675 < 918000000 1000000 >,
676 < 1026000000 1012500 >,
677 < 1134000000 1037500 >,
678 < 1242000000 1050000 >,
679 < 1350000000 1087500 >,
680 < 1458000000 1112500 >,
681 < 1512000000 1125000 >;
683 qcom,speed14-pvs2-bin-v0 =
684 < 384000000 925000 >,
685 < 486000000 925000 >,
686 < 594000000 925000 >,
687 < 702000000 925000 >,
688 < 810000000 937500 >,
689 < 918000000 950000 >,
690 < 1026000000 975000 >,
691 < 1134000000 1000000 >,
692 < 1242000000 1012500 >,
693 < 1350000000 1037500 >,
694 < 1458000000 1075000 >,
695 < 1512000000 1087500 >;
697 qcom,speed14-pvs3-bin-v0 =
698 < 384000000 900000 >,
699 < 486000000 900000 >,
700 < 594000000 900000 >,
701 < 702000000 900000 >,
702 < 810000000 900000 >,
703 < 918000000 925000 >,
704 < 1026000000 950000 >,
705 < 1134000000 975000 >,
706 < 1242000000 987500 >,
707 < 1350000000 1000000 >,
708 < 1458000000 1037500 >,
709 < 1512000000 1050000 >;
711 qcom,speed14-pvs4-bin-v0 =
712 < 384000000 875000 >,
713 < 486000000 875000 >,
714 < 594000000 875000 >,
715 < 702000000 875000 >,
716 < 810000000 887500 >,
717 < 918000000 900000 >,
718 < 1026000000 925000 >,
719 < 1134000000 950000 >,
720 < 1242000000 962500 >,
721 < 1350000000 975000 >,
722 < 1458000000 1000000 >,
723 < 1512000000 1012500 >;
725 qcom,speed14-pvs5-bin-v0 =
726 < 384000000 875000 >,
727 < 486000000 875000 >,
728 < 594000000 875000 >,
729 < 702000000 875000 >,
730 < 810000000 887500 >,
731 < 918000000 900000 >,
732 < 1026000000 925000 >,
733 < 1134000000 937500 >,
734 < 1242000000 950000 >,
735 < 1350000000 962500 >,
736 < 1458000000 987500 >,
737 < 1512000000 1000000 >;
739 qcom,speed14-pvs6-bin-v0 =
740 < 384000000 875000 >,
741 < 486000000 875000 >,
742 < 594000000 875000 >,
743 < 702000000 875000 >,
744 < 810000000 887500 >,
745 < 918000000 900000 >,
746 < 1026000000 925000 >,
747 < 1134000000 937500 >,
748 < 1242000000 950000 >,
749 < 1350000000 962500 >,
750 < 1458000000 975000 >,
751 < 1512000000 987500 >;
754 kraitcc: clock-controller {
755 compatible = "qcom,krait-cc-v1";
760 sleep_clk: sleep_clk {
761 compatible = "fixed-clock";
762 clock-frequency = <32768>;
769 compatible = "fixed-clock";
771 clock-frequency = <19200000>;
775 compatible = "fixed-clock";
777 clock-frequency = <27000000>;
781 compatible = "fixed-clock";
783 clock-frequency = <32768>;
788 compatible = "simple-bus";
791 compatible = "qcom,scm";
796 #address-cells = <1>;
799 compatible = "simple-bus";
801 tlmm_pinmux: pinctrl@800000 {
802 compatible = "qcom,apq8064-pinctrl";
803 reg = <0x800000 0x4000>;
807 interrupt-controller;
808 #interrupt-cells = <2>;
809 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&ps_hold>;
815 sfpb_wrapper_mutex: syscon@1200000 {
816 compatible = "syscon";
817 reg = <0x01200000 0x8000>;
820 intc: interrupt-controller@2000000 {
821 compatible = "qcom,msm-qgic2";
822 interrupt-controller;
823 #interrupt-cells = <3>;
824 reg = <0x02000000 0x1000>,
829 compatible = "qcom,kpss-timer", "qcom,msm-timer";
830 interrupts = <1 1 0x301>,
833 reg = <0x0200a000 0x100>;
834 clock-frequency = <27000000>,
836 cpu-offset = <0x80000>;
840 compatible = "qcom,kpss-wdt-apq8064";
841 reg = <0x0208a038 0x40>;
842 clocks = <&sleep_clk>;
846 acc0: clock-controller@2088000 {
847 compatible = "qcom,kpss-acc-v1";
848 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
849 clock-output-names = "acpu0_aux";
852 acc1: clock-controller@2098000 {
853 compatible = "qcom,kpss-acc-v1";
854 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
855 clock-output-names = "acpu1_aux";
858 acc2: clock-controller@20a8000 {
859 compatible = "qcom,kpss-acc-v1";
860 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
861 clock-output-names = "acpu2_aux";
864 acc3: clock-controller@20b8000 {
865 compatible = "qcom,kpss-acc-v1";
866 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
867 clock-output-names = "acpu3_aux";
870 saw0: power-controller@2089000 {
871 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
872 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
874 regulator-name = "krait0";
876 regulator-min-microvolt = <825000>;
877 regulator-max-microvolt = <1250000>;
880 saw1: power-controller@2099000 {
881 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
882 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
884 regulator-name = "krait1";
886 regulator-min-microvolt = <825000>;
887 regulator-max-microvolt = <1250000>;
890 saw2: power-controller@20a9000 {
891 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
892 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
894 regulator-name = "krait2";
896 regulator-min-microvolt = <825000>;
897 regulator-max-microvolt = <1250000>;
900 saw3: power-controller@20b9000 {
901 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
902 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
904 regulator-name = "krait3";
906 regulator-min-microvolt = <825000>;
907 regulator-max-microvolt = <1250000>;
910 gsbi1: gsbi@12440000 {
912 compatible = "qcom,gsbi-v1.0.0";
914 reg = <0x12440000 0x100>;
915 clocks = <&gcc GSBI1_H_CLK>;
916 clock-names = "iface";
917 #address-cells = <1>;
921 syscon-tcsr = <&tcsr>;
923 gsbi1_serial: serial@12450000 {
924 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
925 reg = <0x12450000 0x100>,
927 interrupts = <0 193 0x0>;
928 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
929 clock-names = "core", "iface";
933 gsbi1_i2c: i2c@12460000 {
934 compatible = "qcom,i2c-qup-v1.1.1";
935 pinctrl-0 = <&i2c1_pins>;
936 pinctrl-1 = <&i2c1_pins_sleep>;
937 pinctrl-names = "default", "sleep";
938 reg = <0x12460000 0x1000>;
939 interrupts = <0 194 IRQ_TYPE_NONE>;
940 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
941 clock-names = "core", "iface";
942 #address-cells = <1>;
948 gsbi2: gsbi@12480000 {
950 compatible = "qcom,gsbi-v1.0.0";
952 reg = <0x12480000 0x100>;
953 clocks = <&gcc GSBI2_H_CLK>;
954 clock-names = "iface";
955 #address-cells = <1>;
959 syscon-tcsr = <&tcsr>;
961 gsbi2_i2c: i2c@124a0000 {
962 compatible = "qcom,i2c-qup-v1.1.1";
963 reg = <0x124a0000 0x1000>;
964 pinctrl-0 = <&i2c2_pins>;
965 pinctrl-1 = <&i2c2_pins_sleep>;
966 pinctrl-names = "default", "sleep";
967 interrupts = <0 196 IRQ_TYPE_NONE>;
968 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
969 clock-names = "core", "iface";
970 #address-cells = <1>;
975 gsbi3: gsbi@16200000 {
977 compatible = "qcom,gsbi-v1.0.0";
979 reg = <0x16200000 0x100>;
980 clocks = <&gcc GSBI3_H_CLK>;
981 clock-names = "iface";
982 #address-cells = <1>;
985 gsbi3_i2c: i2c@16280000 {
986 compatible = "qcom,i2c-qup-v1.1.1";
987 pinctrl-0 = <&i2c3_pins>;
988 pinctrl-1 = <&i2c3_pins_sleep>;
989 pinctrl-names = "default", "sleep";
990 reg = <0x16280000 0x1000>;
991 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
992 clocks = <&gcc GSBI3_QUP_CLK>,
994 clock-names = "core", "iface";
995 #address-cells = <1>;
1000 gsbi4: gsbi@16300000 {
1001 status = "disabled";
1002 compatible = "qcom,gsbi-v1.0.0";
1004 reg = <0x16300000 0x03>;
1005 clocks = <&gcc GSBI4_H_CLK>;
1006 clock-names = "iface";
1007 #address-cells = <1>;
1011 gsbi4_i2c: i2c@16380000 {
1012 compatible = "qcom,i2c-qup-v1.1.1";
1013 pinctrl-0 = <&i2c4_pins>;
1014 pinctrl-1 = <&i2c4_pins_sleep>;
1015 pinctrl-names = "default", "sleep";
1016 reg = <0x16380000 0x1000>;
1017 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
1018 clocks = <&gcc GSBI4_QUP_CLK>,
1020 clock-names = "core", "iface";
1024 gsbi5: gsbi@1a200000 {
1025 status = "disabled";
1026 compatible = "qcom,gsbi-v1.0.0";
1028 reg = <0x1a200000 0x03>;
1029 clocks = <&gcc GSBI5_H_CLK>;
1030 clock-names = "iface";
1031 #address-cells = <1>;
1035 gsbi5_serial: serial@1a240000 {
1036 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1037 reg = <0x1a240000 0x100>,
1039 interrupts = <0 154 0x0>;
1040 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1041 clock-names = "core", "iface";
1042 status = "disabled";
1045 gsbi5_spi: spi@1a280000 {
1046 compatible = "qcom,spi-qup-v1.1.1";
1047 reg = <0x1a280000 0x1000>;
1048 interrupts = <0 155 0>;
1049 pinctrl-0 = <&spi5_default>;
1050 pinctrl-1 = <&spi5_sleep>;
1051 pinctrl-names = "default", "sleep";
1052 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1053 clock-names = "core", "iface";
1054 status = "disabled";
1055 #address-cells = <1>;
1060 gsbi6: gsbi@16500000 {
1061 status = "disabled";
1062 compatible = "qcom,gsbi-v1.0.0";
1064 reg = <0x16500000 0x03>;
1065 clocks = <&gcc GSBI6_H_CLK>;
1066 clock-names = "iface";
1067 #address-cells = <1>;
1070 syscon-tcsr = <&tcsr>;
1072 gsbi6_serial: serial@16540000 {
1073 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1074 reg = <0x16540000 0x100>,
1076 interrupts = <0 156 0x0>;
1077 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
1078 clock-names = "core", "iface";
1080 qcom,rx-crci = <11>;
1083 dmas = <&adm 6>, <&adm 7>;
1084 dma-names = "rx", "tx";
1086 status = "disabled";
1089 gsbi6_i2c: i2c@16580000 {
1090 compatible = "qcom,i2c-qup-v1.1.1";
1091 pinctrl-0 = <&i2c6_pins>;
1092 pinctrl-1 = <&i2c6_pins_sleep>;
1093 pinctrl-names = "default", "sleep";
1094 reg = <0x16580000 0x1000>;
1095 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
1096 clocks = <&gcc GSBI6_QUP_CLK>,
1098 clock-names = "core", "iface";
1102 gsbi7: gsbi@16600000 {
1103 status = "disabled";
1104 compatible = "qcom,gsbi-v1.0.0";
1106 reg = <0x16600000 0x100>;
1107 clocks = <&gcc GSBI7_H_CLK>;
1108 clock-names = "iface";
1109 #address-cells = <1>;
1112 syscon-tcsr = <&tcsr>;
1114 gsbi7_serial: serial@16640000 {
1115 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1116 reg = <0x16640000 0x1000>,
1117 <0x16600000 0x1000>;
1118 interrupts = <0 158 0x0>;
1119 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
1120 clock-names = "core", "iface";
1121 status = "disabled";
1124 gsbi7_i2c: i2c@16680000 {
1125 compatible = "qcom,i2c-qup-v1.1.1";
1126 pinctrl-0 = <&i2c7_pins>;
1127 pinctrl-1 = <&i2c7_pins_sleep>;
1128 pinctrl-names = "default", "sleep";
1129 reg = <0x16680000 0x1000>;
1130 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
1131 clocks = <&gcc GSBI7_QUP_CLK>,
1133 clock-names = "core", "iface";
1134 status = "disabled";
1139 compatible = "qcom,prng";
1140 reg = <0x1a500000 0x200>;
1141 clocks = <&gcc PRNG_CLK>;
1142 clock-names = "core";
1146 compatible = "qcom,ssbi";
1147 reg = <0x00500000 0x1000>;
1148 qcom,controller-type = "pmic-arbiter";
1151 compatible = "qcom,pm8921";
1152 interrupt-parent = <&tlmm_pinmux>;
1153 interrupts = <74 8>;
1154 #interrupt-cells = <2>;
1155 interrupt-controller;
1156 #address-cells = <1>;
1159 pm8921_gpio: gpio@150 {
1161 compatible = "qcom,pm8921-gpio",
1164 interrupts = <192 1>, <193 1>, <194 1>,
1165 <195 1>, <196 1>, <197 1>,
1166 <198 1>, <199 1>, <200 1>,
1167 <201 1>, <202 1>, <203 1>,
1168 <204 1>, <205 1>, <206 1>,
1169 <207 1>, <208 1>, <209 1>,
1170 <210 1>, <211 1>, <212 1>,
1171 <213 1>, <214 1>, <215 1>,
1172 <216 1>, <217 1>, <218 1>,
1173 <219 1>, <220 1>, <221 1>,
1174 <222 1>, <223 1>, <224 1>,
1175 <225 1>, <226 1>, <227 1>,
1176 <228 1>, <229 1>, <230 1>,
1177 <231 1>, <232 1>, <233 1>,
1185 pm8921_mpps: mpps@50 {
1186 compatible = "qcom,pm8921-mpp",
1192 <128 1>, <129 1>, <130 1>, <131 1>,
1193 <132 1>, <133 1>, <134 1>, <135 1>,
1194 <136 1>, <137 1>, <138 1>, <139 1>;
1198 compatible = "qcom,pm8921-rtc";
1199 interrupt-parent = <&pmicintc>;
1200 interrupts = <39 1>;
1206 compatible = "qcom,pm8921-pwrkey";
1208 interrupt-parent = <&pmicintc>;
1209 interrupts = <50 1>, <51 1>;
1216 qfprom: qfprom@00700000 {
1217 compatible = "qcom,qfprom";
1218 reg = <0x00700000 0x1000>;
1219 #address-cells = <1>;
1222 tsens_calib: calib {
1225 tsens_backup: backup_calib {
1230 gcc: clock-controller@900000 {
1231 compatible = "qcom,gcc-apq8064";
1232 reg = <0x00900000 0x4000>;
1233 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1234 nvmem-cell-names = "calib", "calib_backup";
1235 qcom,tsens-slopes = <1176 1176 1154 1176 1111
1236 1132 1132 1199 1132 1199 1132>;
1239 #thermal-sensor-cells = <1>;
1242 lcc: clock-controller@28000000 {
1243 compatible = "qcom,lcc-apq8064";
1244 reg = <0x28000000 0x1000>;
1249 mmcc: clock-controller@4000000 {
1250 compatible = "qcom,mmcc-apq8064";
1251 reg = <0x4000000 0x1000>;
1256 l2cc: clock-controller@2011000 {
1257 compatible = "syscon";
1258 reg = <0x2011000 0x1000>;
1262 compatible = "qcom,rpm-apq8064";
1263 reg = <0x108000 0x1000>;
1264 qcom,ipc = <&l2cc 0x8 2>;
1266 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
1267 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
1268 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
1269 interrupt-names = "ack", "err", "wakeup";
1271 rpmcc: clock-controller {
1272 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
1277 compatible = "qcom,rpm-pm8921-regulators";
1313 pm8921_lvs1: lvs1 {};
1314 pm8921_lvs2: lvs2 {};
1315 pm8921_lvs3: lvs3 {};
1316 pm8921_lvs4: lvs4 {};
1317 pm8921_lvs5: lvs5 {};
1318 pm8921_lvs6: lvs6 {};
1319 pm8921_lvs7: lvs7 {};
1321 pm8921_usb_switch: usb-switch {};
1323 pm8921_hdmi_switch: hdmi-switch {
1331 usb1_phy: phy@12500000 {
1332 compatible = "qcom,usb-otg-ci";
1333 reg = <0x12500000 0x400>;
1334 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1335 status = "disabled";
1338 clocks = <&gcc USB_HS1_XCVR_CLK>,
1339 <&gcc USB_HS1_H_CLK>;
1340 clock-names = "core", "iface";
1342 resets = <&gcc USB_HS1_RESET>;
1343 reset-names = "link";
1346 usb3_phy: phy@12520000 {
1347 compatible = "qcom,usb-otg-ci";
1348 reg = <0x12520000 0x400>;
1349 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
1350 status = "disabled";
1353 clocks = <&gcc USB_HS3_XCVR_CLK>,
1354 <&gcc USB_HS3_H_CLK>;
1355 clock-names = "core", "iface";
1357 resets = <&gcc USB_HS3_RESET>;
1358 reset-names = "link";
1361 usb4_phy: phy@12530000 {
1362 compatible = "qcom,usb-otg-ci";
1363 reg = <0x12530000 0x400>;
1364 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
1365 status = "disabled";
1368 clocks = <&gcc USB_HS4_XCVR_CLK>,
1369 <&gcc USB_HS4_H_CLK>;
1370 clock-names = "core", "iface";
1372 resets = <&gcc USB_HS4_RESET>;
1373 reset-names = "link";
1376 gadget1: gadget@12500000 {
1377 compatible = "qcom,ci-hdrc";
1378 reg = <0x12500000 0x400>;
1379 status = "disabled";
1380 dr_mode = "peripheral";
1381 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1382 usb-phy = <&usb1_phy>;
1385 usb1: usb@12500000 {
1386 compatible = "qcom,ehci-host";
1387 reg = <0x12500000 0x400>;
1388 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
1389 status = "disabled";
1390 usb-phy = <&usb1_phy>;
1393 usb3: usb@12520000 {
1394 compatible = "qcom,ehci-host";
1395 reg = <0x12520000 0x400>;
1396 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
1397 status = "disabled";
1398 usb-phy = <&usb3_phy>;
1401 usb4: usb@12530000 {
1402 compatible = "qcom,ehci-host";
1403 reg = <0x12530000 0x400>;
1404 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
1405 status = "disabled";
1406 usb-phy = <&usb4_phy>;
1409 sata_phy0: phy@1b400000 {
1410 compatible = "qcom,apq8064-sata-phy";
1411 status = "disabled";
1412 reg = <0x1b400000 0x200>;
1413 reg-names = "phy_mem";
1414 clocks = <&gcc SATA_PHY_CFG_CLK>;
1415 clock-names = "cfg";
1419 sata0: sata@29000000 {
1420 compatible = "qcom,apq8064-ahci", "generic-ahci";
1421 status = "disabled";
1422 reg = <0x29000000 0x180>;
1423 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
1425 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1428 <&gcc SATA_RXOOB_CLK>,
1429 <&gcc SATA_PMALIVE_CLK>;
1430 clock-names = "slave_iface",
1436 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1437 <&gcc SATA_PMALIVE_CLK>;
1438 assigned-clock-rates = <100000000>, <100000000>;
1440 phys = <&sata_phy0>;
1441 phy-names = "sata-phy";
1442 ports-implemented = <0x1>;
1445 /* Temporary fixed regulator */
1446 sdcc1bam:dma@12402000{
1447 compatible = "qcom,bam-v1.3.0";
1448 reg = <0x12402000 0x8000>;
1449 interrupts = <0 98 0>;
1450 clocks = <&gcc SDC1_H_CLK>;
1451 clock-names = "bam_clk";
1456 sdcc3bam:dma@12182000{
1457 compatible = "qcom,bam-v1.3.0";
1458 reg = <0x12182000 0x8000>;
1459 interrupts = <0 96 0>;
1460 clocks = <&gcc SDC3_H_CLK>;
1461 clock-names = "bam_clk";
1466 sdcc4bam:dma@121c2000{
1467 compatible = "qcom,bam-v1.3.0";
1468 reg = <0x121c2000 0x8000>;
1469 interrupts = <0 95 0>;
1470 clocks = <&gcc SDC4_H_CLK>;
1471 clock-names = "bam_clk";
1477 compatible = "arm,amba-bus";
1478 #address-cells = <1>;
1481 sdcc1: sdcc@12400000 {
1482 status = "disabled";
1483 compatible = "arm,pl18x", "arm,primecell";
1484 arm,primecell-periphid = <0x00051180>;
1485 reg = <0x12400000 0x2000>;
1486 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1487 interrupt-names = "cmd_irq";
1488 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1489 clock-names = "mclk", "apb_pclk";
1491 max-frequency = <96000000>;
1495 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1496 dma-names = "tx", "rx";
1499 sdcc3: sdcc@12180000 {
1500 compatible = "arm,pl18x", "arm,primecell";
1501 arm,primecell-periphid = <0x00051180>;
1502 status = "disabled";
1503 reg = <0x12180000 0x2000>;
1504 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1505 interrupt-names = "cmd_irq";
1506 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1507 clock-names = "mclk", "apb_pclk";
1511 max-frequency = <192000000>;
1513 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1514 dma-names = "tx", "rx";
1517 sdcc4: sdcc@121c0000 {
1518 compatible = "arm,pl18x", "arm,primecell";
1519 arm,primecell-periphid = <0x00051180>;
1520 status = "disabled";
1521 reg = <0x121c0000 0x2000>;
1522 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1523 interrupt-names = "cmd_irq";
1524 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1525 clock-names = "mclk", "apb_pclk";
1529 max-frequency = <48000000>;
1530 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1531 dma-names = "tx", "rx";
1532 pinctrl-names = "default";
1533 pinctrl-0 = <&sdc4_gpios>;
1538 compatible = "qcom,adm";
1539 reg = <0x18320000 0xE0000>;
1540 interrupts = <GIC_SPI 171 IRQ_TYPE_NONE>;
1543 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1544 clock-names = "core", "iface";
1546 resets = <&gcc ADM0_RESET>,
1547 <&gcc ADM0_PBUS_RESET>,
1548 <&gcc ADM0_C0_RESET>,
1549 <&gcc ADM0_C1_RESET>,
1550 <&gcc ADM0_C2_RESET>;
1551 reset-names = "clk", "pbus", "c0", "c1", "c2";
1554 status = "disabled";
1557 tcsr: syscon@1a400000 {
1558 compatible = "qcom,tcsr-apq8064", "syscon";
1559 reg = <0x1a400000 0x100>;
1562 pcie: pci@1b500000 {
1563 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1564 reg = <0x1b500000 0x1000
1567 0x0ff00000 0x100000>;
1568 reg-names = "dbi", "elbi", "parf", "config";
1569 device_type = "pci";
1570 linux,pci-domain = <0>;
1571 bus-range = <0x00 0xff>;
1573 #address-cells = <3>;
1575 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1576 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1577 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1578 interrupt-names = "msi";
1579 #interrupt-cells = <1>;
1580 interrupt-map-mask = <0 0 0 0x7>;
1581 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1582 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1583 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1584 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1585 clocks = <&gcc PCIE_A_CLK>,
1587 <&gcc PCIE_PHY_REF_CLK>;
1588 clock-names = "core", "iface", "phy";
1589 resets = <&gcc PCIE_ACLK_RESET>,
1590 <&gcc PCIE_HCLK_RESET>,
1591 <&gcc PCIE_POR_RESET>,
1592 <&gcc PCIE_PCI_RESET>,
1593 <&gcc PCIE_PHY_RESET>;
1594 reset-names = "axi", "ahb", "por", "pci", "phy";
1595 status = "disabled";
1598 pil_q6v4: pil@28800000 {
1599 compatible = "qcom,tz-pil", "qcom,apq8064-tz-pil";
1600 qcom,firmware-name = "q6";
1601 reg = <0x28800000 0x100>;
1602 reg-names = "qdsp6_base";
1603 qcom,pas-id = <1>; /* PAS_Q6 */
1607 compatible = "qcom,smd";
1609 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
1610 qcom,ipc = <&l2cc 8 15>;
1611 qcom,smd-edge = <1>;
1612 qcom,remote-pid = <0x2>;
1614 compatible = "qcom,apr";
1615 qcom,smd-channels = "apr_audio_svc";
1616 rproc = <&pil_q6v4>;
1622 compatible = "qcom,msm-dai-fe";
1623 #sound-dai-cells = <0>;
1626 hdmi_dai: dai_hdmi {
1627 compatible = "qcom,msm-dai-q6-hdmi";
1628 #sound-dai-cells = <0>;
1631 hdmi_codec: codec_hdmi {
1632 compatible = "linux,hdmi-audio";
1633 #sound-dai-cells = <0>;
1637 compatible = "qcom,msm-pcm-dsp";
1638 #sound-dai-cells = <0>;
1641 q6_route: msm_pcm_routing {
1642 compatible = "qcom,msm-pcm-routing";
1643 #sound-dai-cells = <0>;
1647 compatible = "qcom,snd-apq8064";
1651 hdmi: qcom,hdmi-tx@4a00000 {
1652 compatible = "qcom,hdmi-tx-8960";
1653 reg-names = "core_physical";
1654 reg = <0x04a00000 0x1000>;
1655 interrupts = <GIC_SPI 79 0>;
1661 <&mmcc HDMI_APP_CLK>,
1662 <&mmcc HDMI_M_AHB_CLK>,
1663 <&mmcc HDMI_S_AHB_CLK>;
1664 qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
1665 qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
1666 qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
1667 pinctrl-names = "default";
1668 pinctrl-0 = <&hdmi_pinctrl>;
1671 gpu: qcom,adreno-3xx@4300000 {
1672 compatible = "qcom,adreno-3xx";
1673 reg = <0x04300000 0x20000>;
1674 reg-names = "kgsl_3d0_reg_memory";
1675 interrupts = <GIC_SPI 80 0>;
1676 interrupt-names = "kgsl_3d0_irq";
1684 <&mmcc GFX3D_AHB_CLK>,
1685 <&mmcc GFX3D_AXI_CLK>,
1686 <&mmcc MMSS_IMEM_AHB_CLK>;
1687 qcom,chipid = <0x03020002>;
1689 iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1690 &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1691 &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1692 &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
1694 qcom,gpu-pwrlevels {
1695 compatible = "qcom,gpu-pwrlevels";
1696 qcom,gpu-pwrlevel@0 {
1697 qcom,gpu-freq = <450000000>;
1699 qcom,gpu-pwrlevel@1 {
1700 qcom,gpu-freq = <27000000>;
1705 mdp: qcom,mdp@5100000 {
1706 compatible = "qcom,mdp";
1707 reg = <0x05100000 0xf0000>;
1708 interrupts = <GIC_SPI 75 0>;
1709 connectors = <&hdmi>;
1721 <&mmcc MDP_AHB_CLK>,
1722 <&mmcc MDP_LUT_CLK>,
1724 <&mmcc HDMI_TV_CLK>,
1726 <&mmcc MDP_AXI_CLK>;
1728 iommus = <&mdp_port0 0 2
1732 mdp_port0: qcom,iommu@7500000 {
1733 compatible = "qcom,iommu-v0";
1739 <&mmcc SMMU_AHB_CLK>,
1740 <&mmcc MDP_AXI_CLK>;
1741 reg = <0x07500000 0x100000>;
1748 mdp_port1: qcom,iommu@7600000 {
1749 compatible = "qcom,iommu";
1755 <&mmcc SMMU_AHB_CLK>,
1756 <&mmcc MDP_AXI_CLK>;
1757 reg = <0x07600000 0x100000>;
1764 gfx3d: qcom,iommu@7c00000 {
1765 compatible = "qcom,iommu-v0";
1766 #iommu-cells = <16>;
1771 <&mmcc SMMU_AHB_CLK>,
1772 <&mmcc GFX3D_AXI_CLK>;
1773 reg = <0x07c00000 0x100000>;
1780 gfx3d1: qcom,iommu@7d00000 {
1781 compatible = "qcom,iommu-v0";
1782 #iommu-cells = <16>;
1787 <&mmcc SMMU_AHB_CLK>,
1788 <&mmcc GFX3D_AXI_CLK>;
1789 reg = <0x07d00000 0x100000>;
1798 #include "qcom-apq8064-coresight.dtsi"
1799 #include "qcom-apq8064-pins.dtsi"