arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   8 #include <dt-bindings/soc/qcom,gsbi.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         model = "Qualcomm APQ8064";
  14         compatible = "qcom,apq8064";
  15         interrupt-parent = <&intc>;
  16
  17         reserved-memory {
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 ranges;
  21
  22                 smem_region: smem@80000000 {
  23                         reg = <0x80000000 0x200000>;
  24                         no-map;
  25                 };
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 CPU0: cpu@0 {
  33                         compatible = "qcom,krait";
  34                         enable-method = "qcom,kpss-acc-v1";
  35                         device_type = "cpu";
  36                         reg = <0>;
  37                         next-level-cache = <&L2>;
  38                         qcom,acc = <&acc0>;
  39                         qcom,saw = <&saw0>;
  40                         cpu-idle-states = <&CPU_SPC>;
  41                         clocks = <&kraitcc 0>, <&kraitcc 4>;
  42                         clock-names = "cpu", "l2";
  43                         clock-latency = <100000>;
  44                         cooling-min-level = <0>;
  45                         cooling-max-level = <7>;
  46                         #cooling-cells = <2>;
  47                 };
  48
  49                 CPU1: cpu@1 {
  50                         compatible = "qcom,krait";
  51                         enable-method = "qcom,kpss-acc-v1";
  52                         device_type = "cpu";
  53                         reg = <1>;
  54                         next-level-cache = <&L2>;
  55                         qcom,acc = <&acc1>;
  56                         qcom,saw = <&saw1>;
  57                         cpu-idle-states = <&CPU_SPC>;
  58                         clocks = <&kraitcc 1>, <&kraitcc 4>;
  59                         clock-names = "cpu", "l2";
  60                         clock-latency = <100000>;
  61                         cooling-min-level = <0>;
  62                         cooling-max-level = <7>;
  63                         #cooling-cells = <2>;
  64                 };
  65
  66                 CPU2: cpu@2 {
  67                         compatible = "qcom,krait";
  68                         enable-method = "qcom,kpss-acc-v1";
  69                         device_type = "cpu";
  70                         reg = <2>;
  71                         next-level-cache = <&L2>;
  72                         qcom,acc = <&acc2>;
  73                         qcom,saw = <&saw2>;
  74                         cpu-idle-states = <&CPU_SPC>;
  75                         clocks = <&kraitcc 2>, <&kraitcc 4>;
  76                         clock-names = "cpu", "l2";
  77                         clock-latency = <100000>;
  78                         cooling-min-level = <0>;
  79                         cooling-max-level = <7>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 CPU3: cpu@3 {
  84                         compatible = "qcom,krait";
  85                         enable-method = "qcom,kpss-acc-v1";
  86                         device_type = "cpu";
  87                         reg = <3>;
  88                         next-level-cache = <&L2>;
  89                         qcom,acc = <&acc3>;
  90                         qcom,saw = <&saw3>;
  91                         cpu-idle-states = <&CPU_SPC>;
  92                         clocks = <&kraitcc 3>, <&kraitcc 4>;
  93                         clock-names = "cpu", "l2";
  94                         clock-latency = <100000>;
  95                         cooling-min-level = <0>;
  96                         cooling-max-level = <7>;
  97                         #cooling-cells = <2>;
  98                 };
  99
 100                 L2: l2-cache {
 101                         compatible = "cache";
 102                         cache-level = <2>;
 103                 };
 104
 105                 qcom,l2 {
 106                         qcom,l2-rates = <384000000 972000000 1188000000>;
 107                 };
 108
 109                 idle-states {
 110                         CPU_SPC: spc {
 111                                 compatible = "qcom,idle-state-spc",
 112                                                 "arm,idle-state";
 113                                 entry-latency-us = <400>;
 114                                 exit-latency-us = <900>;
 115                                 min-residency-us = <3000>;
 116                         };
 117                 };
 118         };
 119
 120         thermal-zones {
 121                 cpu-thermal0 {
 122                         polling-delay-passive = <250>;
 123                         polling-delay = <1000>;
 124
 125                         thermal-sensors = <&tsens 7>;
 126
 127                         trips {
 128                                 cpu_alert0: trip@0 {
 129                                         temperature = <75000>;
 130                                         hysteresis = <2000>;
 131                                         type = "passive";
 132                                 };
 133                                 cpu_crit0: trip@1 {
 134                                         temperature = <110000>;
 135                                         hysteresis = <2000>;
 136                                         type = "critical";
 137                                 };
 138                         };
 139
 140                         cooling-maps {
 141                                 map0 {
 142                                         trip = <&cpu_alert0>;
 143                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 144                                 };
 145                         };
 146                 };
 147
 148                 cpu-thermal1 {
 149                         polling-delay-passive = <250>;
 150                         polling-delay = <1000>;
 151
 152                         thermal-sensors = <&tsens 8>;
 153
 154                         trips {
 155                                 cpu_alert1: trip@0 {
 156                                         temperature = <75000>;
 157                                         hysteresis = <2000>;
 158                                         type = "passive";
 159                                 };
 160                                 cpu_crit1: trip@1 {
 161                                         temperature = <110000>;
 162                                         hysteresis = <2000>;
 163                                         type = "critical";
 164                                 };
 165                         };
 166
 167                         cooling-maps {
 168                                 map0 {
 169                                         trip = <&cpu_alert1>;
 170                                         cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 171                                 };
 172                         };
 173                 };
 174
 175                 cpu-thermal2 {
 176                         polling-delay-passive = <250>;
 177                         polling-delay = <1000>;
 178
 179                         thermal-sensors = <&tsens 9>;
 180
 181                         trips {
 182                                 cpu_alert2: trip@0 {
 183                                         temperature = <75000>;
 184                                         hysteresis = <2000>;
 185                                         type = "passive";
 186                                 };
 187                                 cpu_crit2: trip@1 {
 188                                         temperature = <110000>;
 189                                         hysteresis = <2000>;
 190                                         type = "critical";
 191                                 };
 192                         };
 193
 194                         cooling-maps {
 195                                 map0 {
 196                                         trip = <&cpu_alert2>;
 197                                         cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 198                                 };
 199                         };
 200                 };
 201
 202                 cpu-thermal3 {
 203                         polling-delay-passive = <250>;
 204                         polling-delay = <1000>;
 205
 206                         thermal-sensors = <&tsens 10>;
 207
 208                         trips {
 209                                 cpu_alert3: trip@0 {
 210                                         temperature = <75000>;
 211                                         hysteresis = <2000>;
 212                                         type = "passive";
 213                                 };
 214                                 cpu_crit3: trip@1 {
 215                                         temperature = <110000>;
 216                                         hysteresis = <2000>;
 217                                         type = "critical";
 218                                 };
 219                         };
 220
 221                         cooling-maps {
 222                                 map0 {
 223                                         trip = <&cpu_alert3>;
 224                                         cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 225                                 };
 226                         };
 227                 };
 228         };
 229
 230         thermal-zones {
 231                 cpu-thermal0 {
 232                         polling-delay-passive = <250>;
 233                         polling-delay = <1000>;
 234
 235                         thermal-sensors = <&gcc 7>;
 236
 237                         trips {
 238                                 cpu_alert0: trip@0 {
 239                                         temperature = <75000>;
 240                                         hysteresis = <2000>;
 241                                         type = "passive";
 242                                 };
 243                                 cpu_crit0: trip@1 {
 244                                         temperature = <95000>;
 245                                         hysteresis = <2000>;
 246                                         type = "critical";
 247                                 };
 248                         };
 249                 };
 250
 251                 cpu-thermal1 {
 252                         polling-delay-passive = <250>;
 253                         polling-delay = <1000>;
 254
 255                         thermal-sensors = <&gcc 8>;
 256
 257                         trips {
 258                                 cpu_alert1: trip@0 {
 259                                         temperature = <75000>;
 260                                         hysteresis = <2000>;
 261                                         type = "passive";
 262                                 };
 263                                 cpu_crit1: trip@1 {
 264                                         temperature = <95000>;
 265                                         hysteresis = <2000>;
 266                                         type = "critical";
 267                                 };
 268                         };
 269                 };
 270
 271                 cpu-thermal2 {
 272                         polling-delay-passive = <250>;
 273                         polling-delay = <1000>;
 274
 275                         thermal-sensors = <&gcc 9>;
 276
 277                         trips {
 278                                 cpu_alert2: trip@0 {
 279                                         temperature = <75000>;
 280                                         hysteresis = <2000>;
 281                                         type = "passive";
 282                                 };
 283                                 cpu_crit2: trip@1 {
 284                                         temperature = <95000>;
 285                                         hysteresis = <2000>;
 286                                         type = "critical";
 287                                 };
 288                         };
 289                 };
 290
 291                 cpu-thermal3 {
 292                         polling-delay-passive = <250>;
 293                         polling-delay = <1000>;
 294
 295                         thermal-sensors = <&gcc 10>;
 296
 297                         trips {
 298                                 cpu_alert3: trip@0 {
 299                                         temperature = <75000>;
 300                                         hysteresis = <2000>;
 301                                         type = "passive";
 302                                 };
 303                                 cpu_crit3: trip@1 {
 304                                         temperature = <95000>;
 305                                         hysteresis = <2000>;
 306                                         type = "critical";
 307                                 };
 308                         };
 309                 };
 310         };
 311
 312         cpu-pmu {
 313                 compatible = "qcom,krait-pmu";
 314                 interrupts = <1 10 0x304>;
 315         };
 316
 317         clocks {
 318                 cxo_board {
 319                         compatible = "fixed-clock";
 320                         #clock-cells = <0>;
 321                         clock-frequency = <19200000>;
 322                 };
 323
 324                 pxo_board {
 325                         compatible = "fixed-clock";
 326                         #clock-cells = <0>;
 327                         clock-frequency = <27000000>;
 328                 };
 329
 330                 sleep_clk {
 331                         compatible = "fixed-clock";
 332                         #clock-cells = <0>;
 333                         clock-frequency = <32768>;
 334                 };
 335         };
 336
 337         sfpb_mutex: hwmutex {
 338                 compatible = "qcom,sfpb-mutex";
 339                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
 340                 #hwlock-cells = <1>;
 341         };
 342
 343         smem {
 344                 compatible = "qcom,smem";
 345                 memory-region = <&smem_region>;
 346
 347                 hwlocks = <&sfpb_mutex 3>;
 348         };
 349
 350         qcom,pvs {
 351                 qcom,pvs-format-a;
 352                 qcom,speed0-pvs0-bin-v0 =
 353                         < 384000000 950000  >,
 354                         < 486000000 975000  >,
 355                         < 594000000 1000000  >,
 356                         < 702000000 1025000  >,
 357                         < 810000000 1075000  >,
 358                         < 918000000 1100000  >,
 359                         < 1026000000 1125000 >,
 360                         < 1080000000 1175000 >,
 361                         < 1134000000 1175000 >,
 362                         < 1188000000 1200000 >,
 363                         < 1242000000 1200000 >,
 364                         < 1296000000 1225000 >,
 365                         < 1350000000 1225000 >,
 366                         < 1404000000 1237500 >,
 367                         < 1458000000 1237500 >,
 368                         < 1512000000 1250000 >;
 369
 370                 qcom,speed0-pvs1-bin-v0 =
 371                         < 384000000 900000  >,
 372                         < 486000000 925000  >,
 373                         < 594000000 950000  >,
 374                         < 702000000 975000  >,
 375                         < 810000000 1025000  >,
 376                         < 918000000 1050000  >,
 377                         < 1026000000 1075000 >,
 378                         < 1080000000 1125000 >,
 379                         < 1134000000 1125000 >,
 380                         < 1188000000 1150000 >,
 381                         < 1242000000 1150000 >,
 382                         < 1296000000 1175000 >,
 383                         < 1350000000 1175000 >,
 384                         < 1404000000 1187500 >,
 385                         < 1458000000 1187500 >,
 386                         < 1512000000 1200000 >;
 387
 388                 qcom,speed0-pvs3-bin-v0 =
 389                         < 384000000 850000  >,
 390                         < 486000000 875000  >,
 391                         < 594000000 900000  >,
 392                         < 702000000 925000  >,
 393                         < 810000000 975000  >,
 394                         < 918000000 1000000  >,
 395                         < 1026000000 1025000 >,
 396                         < 1080000000 1075000 >,
 397                         < 1134000000 1075000 >,
 398                         < 1188000000 1100000 >,
 399                         < 1242000000 1100000 >,
 400                         < 1296000000 1125000 >,
 401                         < 1350000000 1125000 >,
 402                         < 1404000000 1137500 >,
 403                         < 1458000000 1137500 >,
 404                         < 1512000000 1150000 >;
 405
 406                 qcom,speed0-pvs4-bin-v0 =
 407                         < 384000000 850000  >,
 408                         < 486000000 875000  >,
 409                         < 594000000 900000  >,
 410                         < 702000000 925000  >,
 411                         < 810000000 962500  >,
 412                         < 918000000 975000  >,
 413                         < 1026000000 1000000 >,
 414                         < 1080000000 1050000 >,
 415                         < 1134000000 1050000 >,
 416                         < 1188000000 1075000 >,
 417                         < 1242000000 1075000 >,
 418                         < 1296000000 1100000 >,
 419                         < 1350000000 1100000 >,
 420                         < 1404000000 1112500 >,
 421                         < 1458000000 1112500 >,
 422                         < 1512000000 1125000 >;
 423
 424                 qcom,speed1-pvs0-bin-v0 =
 425                         < 384000000 950000  >,
 426                         < 486000000 950000  >,
 427                         < 594000000 950000  >,
 428                         < 702000000 962500  >,
 429                         < 810000000 1000000  >,
 430                         < 918000000 1025000  >,
 431                         < 1026000000 1037500 >,
 432                         < 1134000000 1075000 >,
 433                         < 1242000000 1087500 >,
 434                         < 1350000000 1125000 >,
 435                         < 1458000000 1150000 >,
 436                         < 1566000000 1175000 >,
 437                         < 1674000000 1225000 >,
 438                         < 1728000000 1250000 >;
 439
 440                 qcom,speed1-pvs1-bin-v0 =
 441                         < 384000000 950000  >,
 442                         < 486000000 950000  >,
 443                         < 594000000 950000  >,
 444                         < 702000000 962500  >,
 445                         < 810000000 975000  >,
 446                         < 918000000 1000000 >,
 447                         < 1026000000 1012500 >,
 448                         < 1134000000 1037500 >,
 449                         < 1242000000 1050000 >,
 450                         < 1350000000 1087500 >,
 451                         < 1458000000 1112500 >,
 452                         < 1566000000 1150000 >,
 453                         < 1674000000 1187500 >,
 454                         < 1728000000 1200000 >;
 455
 456                 qcom,speed1-pvs2-bin-v0 =
 457                         < 384000000 925000  >,
 458                         < 486000000 925000  >,
 459                         < 594000000 925000  >,
 460                         < 702000000 925000  >,
 461                         < 810000000 937500  >,
 462                         < 918000000 950000  >,
 463                         < 1026000000 975000 >,
 464                         < 1134000000 1000000 >,
 465                         < 1242000000 1012500 >,
 466                         < 1350000000 1037500 >,
 467                         < 1458000000 1075000 >,
 468                         < 1566000000 1100000 >,
 469                         < 1674000000 1137500 >,
 470                         < 1728000000 1162500 >;
 471
 472                 qcom,speed1-pvs3-bin-v0 =
 473                         < 384000000 900000  >,
 474                         < 486000000 900000  >,
 475                         < 594000000 900000  >,
 476                         < 702000000 900000  >,
 477                         < 810000000 900000  >,
 478                         < 918000000 925000  >,
 479                         < 1026000000 950000 >,
 480                         < 1134000000 975000 >,
 481                         < 1242000000 987500 >,
 482                         < 1350000000 1000000 >,
 483                         < 1458000000 1037500 >,
 484                         < 1566000000 1062500 >,
 485                         < 1674000000 1100000 >,
 486                         < 1728000000 1125000 >;
 487
 488                 qcom,speed1-pvs4-bin-v0 =
 489                         < 384000000 875000  >,
 490                         < 486000000 875000  >,
 491                         < 594000000 875000  >,
 492                         < 702000000 875000  >,
 493                         < 810000000 887500  >,
 494                         < 918000000 900000  >,
 495                         < 1026000000 925000 >,
 496                         < 1134000000 950000 >,
 497                         < 1242000000 962500 >,
 498                         < 1350000000 975000 >,
 499                         < 1458000000 1000000 >,
 500                         < 1566000000 1037500 >,
 501                         < 1674000000 1075000 >,
 502                         < 1728000000 1100000 >;
 503
 504                 qcom,speed1-pvs5-bin-v0 =
 505                         < 384000000 875000  >,
 506                         < 486000000 875000  >,
 507                         < 594000000 875000  >,
 508                         < 702000000 875000  >,
 509                         < 810000000 887500  >,
 510                         < 918000000 900000  >,
 511                         < 1026000000 925000 >,
 512                         < 1134000000 937500 >,
 513                         < 1242000000 950000 >,
 514                         < 1350000000 962500 >,
 515                         < 1458000000 987500 >,
 516                         < 1566000000 1012500 >,
 517                         < 1674000000 1050000 >,
 518                         < 1728000000 1075000 >;
 519
 520                 qcom,speed1-pvs6-bin-v0 =
 521                         < 384000000 875000  >,
 522                         < 486000000 875000  >,
 523                         < 594000000 875000  >,
 524                         < 702000000 875000  >,
 525                         < 810000000 887500  >,
 526                         < 918000000 900000  >,
 527                         < 1026000000 925000 >,
 528                         < 1134000000 937500 >,
 529                         < 1242000000 950000 >,
 530                         < 1350000000 962500 >,
 531                         < 1458000000 975000 >,
 532                         < 1566000000 1000000 >,
 533                         < 1674000000 1025000 >,
 534                         < 1728000000 1050000 >;
 535
 536                 qcom,speed2-pvs0-bin-v0 =
 537                         < 384000000 950000  >,
 538                         < 486000000 950000  >,
 539                         < 594000000 950000  >,
 540                         < 702000000 950000  >,
 541                         < 810000000 962500  >,
 542                         < 918000000 975000  >,
 543                         < 1026000000 1000000 >,
 544                         < 1134000000 1025000 >,
 545                         < 1242000000 1037500 >,
 546                         < 1350000000 1062500 >,
 547                         < 1458000000 1100000 >,
 548                         < 1566000000 1125000 >,
 549                         < 1674000000 1175000 >,
 550                         < 1782000000 1225000 >,
 551                         < 1890000000 1287500 >;
 552
 553                 qcom,speed2-pvs1-bin-v0 =
 554                         < 384000000 925000  >,
 555                         < 486000000 925000  >,
 556                         < 594000000 925000  >,
 557                         < 702000000 925000  >,
 558                         < 810000000 937500  >,
 559                         < 918000000 950000  >,
 560                         < 1026000000 975000 >,
 561                         < 1134000000 1000000 >,
 562                         < 1242000000 1012500 >,
 563                         < 1350000000 1037500 >,
 564                         < 1458000000 1075000 >,
 565                         < 1566000000 1100000 >,
 566                         < 1674000000 1137500 >,
 567                         < 1782000000 1187500 >,
 568                         < 1890000000 1250000 >;
 569
 570                 qcom,speed2-pvs2-bin-v0 =
 571                         < 384000000 900000  >,
 572                         < 486000000 900000  >,
 573                         < 594000000 900000  >,
 574                         < 702000000 900000  >,
 575                         < 810000000 912500  >,
 576                         < 918000000 925000  >,
 577                         < 1026000000 950000 >,
 578                         < 1134000000 975000 >,
 579                         < 1242000000 987500 >,
 580                         < 1350000000 1012500 >,
 581                         < 1458000000 1050000 >,
 582                         < 1566000000 1075000 >,
 583                         < 1674000000 1112500 >,
 584                         < 1782000000 1162500 >,
 585                         < 1890000000 1212500 >;
 586
 587                 qcom,speed2-pvs3-bin-v0 =
 588                         < 384000000 900000  >,
 589                         < 486000000 900000  >,
 590                         < 594000000 900000  >,
 591                         < 702000000 900000  >,
 592                         < 810000000 900000  >,
 593                         < 918000000 912500  >,
 594                         < 1026000000 937500 >,
 595                         < 1134000000 962500 >,
 596                         < 1242000000 975000 >,
 597                         < 1350000000 1000000 >,
 598                         < 1458000000 1025000 >,
 599                         < 1566000000 1050000 >,
 600                         < 1674000000 1087500 >,
 601                         < 1782000000 1137500 >,
 602                         < 1890000000 1175000 >;
 603
 604                 qcom,speed2-pvs4-bin-v0 =
 605                         < 384000000 875000  >,
 606                         < 486000000 875000  >,
 607                         < 594000000 875000  >,
 608                         < 702000000 875000  >,
 609                         < 810000000 887500  >,
 610                         < 918000000 900000  >,
 611                         < 1026000000 925000 >,
 612                         < 1134000000 950000 >,
 613                         < 1242000000 962500 >,
 614                         < 1350000000 975000 >,
 615                         < 1458000000 1000000 >,
 616                         < 1566000000 1037500 >,
 617                         < 1674000000 1075000 >,
 618                         < 1782000000 1112500 >,
 619                         < 1890000000 1150000 >;
 620
 621                 qcom,speed2-pvs5-bin-v0 =
 622                         < 384000000 875000  >,
 623                         < 486000000 875000  >,
 624                         < 594000000 875000  >,
 625                         < 702000000 875000  >,
 626                         < 810000000 887500  >,
 627                         < 918000000 900000  >,
 628                         < 1026000000 925000 >,
 629                         < 1134000000 937500 >,
 630                         < 1242000000 950000 >,
 631                         < 1350000000 962500 >,
 632                         < 1458000000 987500 >,
 633                         < 1566000000 1012500 >,
 634                         < 1674000000 1050000 >,
 635                         < 1782000000 1087500 >,
 636                         < 1890000000 1125000 >;
 637
 638                 qcom,speed2-pvs6-bin-v0 =
 639                         < 384000000 875000  >,
 640                         < 486000000 875000  >,
 641                         < 594000000 875000  >,
 642                         < 702000000 875000  >,
 643                         < 810000000 887500  >,
 644                         < 918000000 900000  >,
 645                         < 1026000000 925000 >,
 646                         < 1134000000 937500 >,
 647                         < 1242000000 950000 >,
 648                         < 1350000000 962500 >,
 649                         < 1458000000 975000 >,
 650                         < 1566000000 1000000 >,
 651                         < 1674000000 1025000 >,
 652                         < 1782000000 1062500 >,
 653                         < 1890000000 1100000 >;
 654
 655                 qcom,speed14-pvs0-bin-v0 =
 656                         < 384000000 950000 >,
 657                         < 486000000 950000 >,
 658                         < 594000000 950000 >,
 659                         < 702000000 962500 >,
 660                         < 810000000 1000000 >,
 661                         < 918000000 1025000 >,
 662                         < 1026000000 1037500 >,
 663                         < 1134000000 1075000 >,
 664                         < 1242000000 1087500 >,
 665                         < 1350000000 1125000 >,
 666                         < 1458000000 1150000 >,
 667                         < 1512000000 1162500 >;
 668
 669                 qcom,speed14-pvs1-bin-v0 =
 670                         < 384000000 950000 >,
 671                         < 486000000 950000 >,
 672                         < 594000000 950000 >,
 673                         < 702000000 962500 >,
 674                         < 810000000 975000 >,
 675                         < 918000000 1000000 >,
 676                         < 1026000000 1012500 >,
 677                         < 1134000000 1037500 >,
 678                         < 1242000000 1050000 >,
 679                         < 1350000000 1087500 >,
 680                         < 1458000000 1112500 >,
 681                         < 1512000000 1125000 >;
 682
 683                 qcom,speed14-pvs2-bin-v0 =
 684                         < 384000000 925000 >,
 685                         < 486000000 925000 >,
 686                         < 594000000 925000 >,
 687                         < 702000000 925000 >,
 688                         < 810000000 937500 >,
 689                         < 918000000 950000 >,
 690                         < 1026000000 975000 >,
 691                         < 1134000000 1000000 >,
 692                         < 1242000000 1012500 >,
 693                         < 1350000000 1037500 >,
 694                         < 1458000000 1075000 >,
 695                         < 1512000000 1087500 >;
 696
 697                 qcom,speed14-pvs3-bin-v0 =
 698                         < 384000000 900000 >,
 699                         < 486000000 900000 >,
 700                         < 594000000 900000 >,
 701                         < 702000000 900000 >,
 702                         < 810000000 900000 >,
 703                         < 918000000 925000 >,
 704                         < 1026000000 950000 >,
 705                         < 1134000000 975000 >,
 706                         < 1242000000 987500 >,
 707                         < 1350000000 1000000 >,
 708                         < 1458000000 1037500 >,
 709                         < 1512000000 1050000 >;
 710
 711                 qcom,speed14-pvs4-bin-v0 =
 712                         < 384000000 875000 >,
 713                         < 486000000 875000 >,
 714                         < 594000000 875000 >,
 715                         < 702000000 875000 >,
 716                         < 810000000 887500 >,
 717                         < 918000000 900000 >,
 718                         < 1026000000 925000 >,
 719                         < 1134000000 950000 >,
 720                         < 1242000000 962500 >,
 721                         < 1350000000 975000 >,
 722                         < 1458000000 1000000 >,
 723                         < 1512000000 1012500 >;
 724
 725                 qcom,speed14-pvs5-bin-v0 =
 726                         < 384000000 875000 >,
 727                         < 486000000 875000 >,
 728                         < 594000000 875000 >,
 729                         < 702000000 875000 >,
 730                         < 810000000 887500 >,
 731                         < 918000000 900000 >,
 732                         < 1026000000 925000 >,
 733                         < 1134000000 937500 >,
 734                         < 1242000000 950000 >,
 735                         < 1350000000 962500 >,
 736                         < 1458000000 987500 >,
 737                         < 1512000000 1000000 >;
 738
 739                 qcom,speed14-pvs6-bin-v0 =
 740                         < 384000000 875000 >,
 741                         < 486000000 875000 >,
 742                         < 594000000 875000 >,
 743                         < 702000000 875000 >,
 744                         < 810000000 887500 >,
 745                         < 918000000 900000 >,
 746                         < 1026000000 925000 >,
 747                         < 1134000000 937500 >,
 748                         < 1242000000 950000 >,
 749                         < 1350000000 962500 >,
 750                         < 1458000000 975000 >,
 751                         < 1512000000 987500 >;
 752         };
 753
 754         kraitcc: clock-controller {
 755                 compatible = "qcom,krait-cc-v1";
 756                 #clock-cells = <1>;
 757         };
 758
 759         clocks {
 760                 sleep_clk: sleep_clk {
 761                         compatible = "fixed-clock";
 762                         clock-frequency = <32768>;
 763                         #clock-cells = <0>;
 764                 };
 765         };
 766
 767         clocks {
 768                 cxo_board {
 769                         compatible = "fixed-clock";
 770                         #clock-cells = <0>;
 771                         clock-frequency = <19200000>;
 772                 };
 773
 774                 pxo_board {
 775                         compatible = "fixed-clock";
 776                         #clock-cells = <0>;
 777                         clock-frequency = <27000000>;
 778                 };
 779
 780                 sleep_clk {
 781                         compatible = "fixed-clock";
 782                         #clock-cells = <0>;
 783                         clock-frequency = <32768>;
 784                 };
 785         };
 786
 787         soc: soc {
 788                 #address-cells = <1>;
 789                 #size-cells = <1>;
 790                 ranges;
 791                 compatible = "simple-bus";
 792
 793                 tlmm_pinmux: pinctrl@800000 {
 794                         compatible = "qcom,apq8064-pinctrl";
 795                         reg = <0x800000 0x4000>;
 796
 797                         gpio-controller;
 798                         #gpio-cells = <2>;
 799                         interrupt-controller;
 800                         #interrupt-cells = <2>;
 801                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 802
 803                         pinctrl-names = "default";
 804                         pinctrl-0 = <&ps_hold>;
 805
 806                         sdc4_gpios: sdc4-gpios {
 807                                 pios {
 808                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 809                                         function = "sdc4";
 810                                 };
 811                         };
 812
 813                         hdmi_pinctrl: hdmi-pinctrl {
 814                                 mux1 {
 815                                         pins = "gpio69", "gpio70", "gpio71";
 816                                         function = "hdmi";
 817                                         bias-pull-up;
 818                                         drive-strength = <2>;
 819                                 };
 820                                 mux2 {
 821                                         pins = "gpio72";
 822                                         function = "hdmi";
 823                                         bias-pull-down;
 824                                         drive-strength = <16>;
 825                                 };
 826                         };
 827                         ps_hold: ps_hold {
 828                                 mux {
 829                                         pins = "gpio78";
 830                                         function = "ps_hold";
 831                                 };
 832                         };
 833
 834                         i2c1_pins: i2c1 {
 835                                 mux {
 836                                         pins = "gpio20", "gpio21";
 837                                         function = "gsbi1";
 838                                 };
 839                         };
 840
 841                         i2c3_pins: i2c3 {
 842                                 mux {
 843                                         pins = "gpio8", "gpio9";
 844                                         function = "gsbi3";
 845                                 };
 846                         };
 847
 848                         gsbi6_uart_2pins: gsbi6_uart_2pins {
 849                                 mux {
 850                                         pins = "gpio14", "gpio15";
 851                                         function = "gsbi6";
 852                                 };
 853                         };
 854
 855                         gsbi6_uart_4pins: gsbi6_uart_4pins {
 856                                 mux {
 857                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 858                                         function = "gsbi6";
 859                                 };
 860                         };
 861
 862                         gsbi7_uart_2pins: gsbi7_uart_2pins {
 863                                 mux {
 864                                         pins = "gpio82", "gpio83";
 865                                         function = "gsbi7";
 866                                 };
 867                         };
 868
 869                         gsbi7_uart_4pins: gsbi7_uart_4pins {
 870                                 mux {
 871                                         pins = "gpio82", "gpio83", "gpio84", "gpio85";
 872                                         function = "gsbi7";
 873                                 };
 874                         };
 875                 };
 876
 877                 sfpb_wrapper_mutex: syscon@1200000 {
 878                         compatible = "syscon";
 879                         reg = <0x01200000 0x8000>;
 880                 };
 881
 882                 intc: interrupt-controller@2000000 {
 883                         compatible = "qcom,msm-qgic2";
 884                         interrupt-controller;
 885                         #interrupt-cells = <3>;
 886                         reg = <0x02000000 0x1000>,
 887                               <0x02002000 0x1000>;
 888                 };
 889
 890                 timer@200a000 {
 891                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 892                         interrupts = <1 1 0x301>,
 893                                      <1 2 0x301>,
 894                                      <1 3 0x301>;
 895                         reg = <0x0200a000 0x100>;
 896                         clock-frequency = <27000000>,
 897                                           <32768>;
 898                         cpu-offset = <0x80000>;
 899                 };
 900
 901                 watchdog@208a038 {
 902                         compatible = "qcom,kpss-wdt-apq8064";
 903                         reg = <0x0208a038 0x40>;
 904                         clocks = <&sleep_clk>;
 905                         timeout-sec = <10>;
 906                 };
 907
 908                 acc0: clock-controller@2088000 {
 909                         compatible = "qcom,kpss-acc-v1";
 910                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 911                         clock-output-names = "acpu0_aux";
 912                 };
 913
 914                 acc1: clock-controller@2098000 {
 915                         compatible = "qcom,kpss-acc-v1";
 916                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 917                         clock-output-names = "acpu1_aux";
 918                 };
 919
 920                 acc2: clock-controller@20a8000 {
 921                         compatible = "qcom,kpss-acc-v1";
 922                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 923                         clock-output-names = "acpu2_aux";
 924                 };
 925
 926                 acc3: clock-controller@20b8000 {
 927                         compatible = "qcom,kpss-acc-v1";
 928                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 929                         clock-output-names = "acpu3_aux";
 930                 };
 931
 932                 saw0: power-controller@2089000 {
 933                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 934                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 935                         regulator;
 936                         regulator-name = "krait0";
 937                         regulator-always-on;
 938                         regulator-min-microvolt = <825000>;
 939                         regulator-max-microvolt = <1250000>;
 940                 };
 941
 942                 saw1: power-controller@2099000 {
 943                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 944                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 945                         regulator;
 946                         regulator-name = "krait1";
 947                         regulator-always-on;
 948                         regulator-min-microvolt = <825000>;
 949                         regulator-max-microvolt = <1250000>;
 950                 };
 951
 952                 saw2: power-controller@20a9000 {
 953                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 954                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 955                         regulator;
 956                         regulator-name = "krait2";
 957                         regulator-always-on;
 958                         regulator-min-microvolt = <825000>;
 959                         regulator-max-microvolt = <1250000>;
 960                 };
 961
 962                 saw3: power-controller@20b9000 {
 963                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 964                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 965                         regulator;
 966                         regulator-name = "krait3";
 967                         regulator-always-on;
 968                         regulator-min-microvolt = <825000>;
 969                         regulator-max-microvolt = <1250000>;
 970                 };
 971
 972                 gsbi1: gsbi@12440000 {
 973                         status = "disabled";
 974                         compatible = "qcom,gsbi-v1.0.0";
 975                         cell-index = <1>;
 976                         reg = <0x12440000 0x100>;
 977                         clocks = <&gcc GSBI1_H_CLK>;
 978                         clock-names = "iface";
 979                         #address-cells = <1>;
 980                         #size-cells = <1>;
 981                         ranges;
 982
 983                         syscon-tcsr = <&tcsr>;
 984
 985                         i2c1: i2c@12460000 {
 986                                 compatible = "qcom,i2c-qup-v1.1.1";
 987                                 pinctrl-0 = <&i2c1_pins>;
 988                                 pinctrl-names = "default";
 989                                 reg = <0x12460000 0x1000>;
 990                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 991                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 992                                 clock-names = "core", "iface";
 993                                 #address-cells = <1>;
 994                                 #size-cells = <0>;
 995                         };
 996                 };
 997
 998                 gsbi2: gsbi@12480000 {
 999                         status = "disabled";
1000                         compatible = "qcom,gsbi-v1.0.0";
1001                         cell-index = <2>;
1002                         reg = <0x12480000 0x100>;
1003                         clocks = <&gcc GSBI2_H_CLK>;
1004                         clock-names = "iface";
1005                         #address-cells = <1>;
1006                         #size-cells = <1>;
1007                         ranges;
1008
1009                         syscon-tcsr = <&tcsr>;
1010
1011                         i2c2: i2c@124a0000 {
1012                                 compatible = "qcom,i2c-qup-v1.1.1";
1013                                 reg = <0x124a0000 0x1000>;
1014                                 interrupts = <0 196 IRQ_TYPE_NONE>;
1015                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
1016                                 clock-names = "core", "iface";
1017                                 #address-cells = <1>;
1018                                 #size-cells = <0>;
1019                         };
1020                 };
1021
1022                 gsbi3: gsbi@16200000 {
1023                         status = "disabled";
1024                         compatible = "qcom,gsbi-v1.0.0";
1025                         cell-index = <3>;
1026                         reg = <0x16200000 0x100>;
1027                         clocks = <&gcc GSBI3_H_CLK>;
1028                         clock-names = "iface";
1029                         #address-cells = <1>;
1030                         #size-cells = <1>;
1031                         ranges;
1032                         i2c3: i2c@16280000 {
1033                                 compatible = "qcom,i2c-qup-v1.1.1";
1034                                 pinctrl-0 = <&i2c3_pins>;
1035                                 pinctrl-names = "default";
1036                                 reg = <0x16280000 0x1000>;
1037                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
1038                                 clocks = <&gcc GSBI3_QUP_CLK>,
1039                                          <&gcc GSBI3_H_CLK>;
1040                                 clock-names = "core", "iface";
1041                         };
1042                 };
1043
1044                 gsbi5: gsbi@1a200000 {
1045                         status = "disabled";
1046                         compatible = "qcom,gsbi-v1.0.0";
1047                         cell-index = <5>;
1048                         reg = <0x1a200000 0x03>;
1049                         clocks = <&gcc GSBI5_H_CLK>;
1050                         clock-names = "iface";
1051                         #address-cells = <1>;
1052                         #size-cells = <1>;
1053                         ranges;
1054
1055                         gsbi5_serial: serial@1a240000 {
1056                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1057                                 reg = <0x1a240000 0x100>,
1058                                       <0x1a200000 0x03>;
1059                                 interrupts = <0 154 0x0>;
1060                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1061                                 clock-names = "core", "iface";
1062                                 status = "disabled";
1063                         };
1064                 };
1065
1066                 gsbi6: gsbi@16500000 {
1067                         status = "disabled";
1068                         compatible = "qcom,gsbi-v1.0.0";
1069                         cell-index = <6>;
1070                         reg = <0x16500000 0x03>;
1071                         clocks = <&gcc GSBI6_H_CLK>;
1072                         clock-names = "iface";
1073                         #address-cells = <1>;
1074                         #size-cells = <1>;
1075                         ranges;
1076                         syscon-tcsr = <&tcsr>;
1077
1078                         gsbi6_serial: serial@16540000 {
1079                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1080                                 reg = <0x16540000 0x100>,
1081                                       <0x16500000 0x03>;
1082                                 interrupts = <0 156 0x0>;
1083                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
1084                                 clock-names = "core", "iface";
1085
1086                                 qcom,rx-crci = <11>;
1087                                 qcom,tx-crci = <6>;
1088
1089                                 dmas = <&adm 6>, <&adm 7>;
1090                                 dma-names = "rx", "tx";
1091
1092                                 status = "disabled";
1093                         };
1094                 };
1095
1096                 gsbi7: gsbi@16600000 {
1097                         status = "disabled";
1098                         compatible = "qcom,gsbi-v1.0.0";
1099                         cell-index = <7>;
1100                         reg = <0x16600000 0x100>;
1101                         clocks = <&gcc GSBI7_H_CLK>;
1102                         clock-names = "iface";
1103                         #address-cells = <1>;
1104                         #size-cells = <1>;
1105                         ranges;
1106                         syscon-tcsr = <&tcsr>;
1107
1108                         gsbi7_serial: serial@16640000 {
1109                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
1110                                 reg = <0x16640000 0x1000>,
1111                                       <0x16600000 0x1000>;
1112                                 interrupts = <0 158 0x0>;
1113                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
1114                                 clock-names = "core", "iface";
1115                                 status = "disabled";
1116                         };
1117                 };
1118
1119                 rng@1a500000 {
1120                         compatible = "qcom,prng";
1121                         reg = <0x1a500000 0x200>;
1122                         clocks = <&gcc PRNG_CLK>;
1123                         clock-names = "core";
1124                 };
1125
1126                 qcom,ssbi@500000 {
1127                         compatible = "qcom,ssbi";
1128                         reg = <0x00500000 0x1000>;
1129                         qcom,controller-type = "pmic-arbiter";
1130
1131                         pmicintc: pmic@0 {
1132                                 compatible = "qcom,pm8921";
1133                                 interrupt-parent = <&tlmm_pinmux>;
1134                                 interrupts = <74 8>;
1135                                 #interrupt-cells = <2>;
1136                                 interrupt-controller;
1137                                 #address-cells = <1>;
1138                                 #size-cells = <0>;
1139
1140                                 pm8921_gpio: gpio@150 {
1141
1142                                         compatible = "qcom,pm8921-gpio",
1143                                                      "qcom,ssbi-gpio";
1144                                         reg = <0x150>;
1145                                         interrupts = <192 1>, <193 1>, <194 1>,
1146                                                      <195 1>, <196 1>, <197 1>,
1147                                                      <198 1>, <199 1>, <200 1>,
1148                                                      <201 1>, <202 1>, <203 1>,
1149                                                      <204 1>, <205 1>, <206 1>,
1150                                                      <207 1>, <208 1>, <209 1>,
1151                                                      <210 1>, <211 1>, <212 1>,
1152                                                      <213 1>, <214 1>, <215 1>,
1153                                                      <216 1>, <217 1>, <218 1>,
1154                                                      <219 1>, <220 1>, <221 1>,
1155                                                      <222 1>, <223 1>, <224 1>,
1156                                                      <225 1>, <226 1>, <227 1>,
1157                                                      <228 1>, <229 1>, <230 1>,
1158                                                      <231 1>, <232 1>, <233 1>,
1159                                                      <234 1>, <235 1>;
1160
1161                                         gpio-controller;
1162                                         #gpio-cells = <2>;
1163
1164                                 };
1165
1166                                 pm8921_mpps: mpps@50 {
1167                                         compatible = "qcom,pm8921-mpp",
1168                                                      "qcom,ssbi-mpp";
1169                                         reg = <0x50>;
1170                                         gpio-controller;
1171                                         #gpio-cells = <2>;
1172                                         interrupts =
1173                                         <128 1>, <129 1>, <130 1>, <131 1>,
1174                                         <132 1>, <133 1>, <134 1>, <135 1>,
1175                                         <136 1>, <137 1>, <138 1>, <139 1>;
1176                                 };
1177
1178                                 rtc@11d {
1179                                         compatible = "qcom,pm8921-rtc";
1180                                         interrupt-parent = <&pmicintc>;
1181                                         interrupts = <39 1>;
1182                                         reg = <0x11d>;
1183                                         allow-set-time;
1184                                 };
1185
1186                                 pwrkey@1c {
1187                                         compatible = "qcom,pm8921-pwrkey";
1188                                         reg = <0x1c>;
1189                                         interrupt-parent = <&pmicintc>;
1190                                         interrupts = <50 1>, <51 1>;
1191                                         debounce = <15625>;
1192                                         pull-up;
1193                                 };
1194                         };
1195                 };
1196
1197                 qfprom: qfprom@00700000 {
1198                         compatible      = "qcom,qfprom";
1199                         reg             = <0x00700000 0x1000>;
1200                         #address-cells  = <1>;
1201                         #size-cells     = <1>;
1202                         ranges;
1203                         tsens_calib: calib {
1204                                 reg = <0x404 0x10>;
1205                         };
1206                         tsens_backup: backup_calib {
1207                                 reg = <0x414 0x10>;
1208                         };
1209                 };
1210
1211                 gcc: clock-controller@900000 {
1212                         compatible = "qcom,gcc-apq8064";
1213                         reg = <0x00900000 0x4000>;
1214                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
1215                         nvmem-cell-names = "calib", "calib_backup";
1216                         qcom,tsens-slopes = <1176 1176 1154 1176 1111
1217                                 1132 1132 1199 1132 1199 1132>;
1218                         #clock-cells = <1>;
1219                         #reset-cells = <1>;
1220                         #thermal-sensor-cells = <1>;
1221                 };
1222
1223                 lcc: clock-controller@28000000 {
1224                         compatible = "qcom,lcc-apq8064";
1225                         reg = <0x28000000 0x1000>;
1226                         #clock-cells = <1>;
1227                         #reset-cells = <1>;
1228                 };
1229
1230                 mmcc: clock-controller@4000000 {
1231                         compatible = "qcom,mmcc-apq8064";
1232                         reg = <0x4000000 0x1000>;
1233                         #clock-cells = <1>;
1234                         #reset-cells = <1>;
1235                 };
1236
1237                 l2cc: clock-controller@2011000 {
1238                         compatible      = "syscon";
1239                         reg             = <0x2011000 0x1000>;
1240                 };
1241
1242                 rpm@108000 {
1243                         compatible      = "qcom,rpm-apq8064";
1244                         reg             = <0x108000 0x1000>;
1245                         qcom,ipc        = <&l2cc 0x8 2>;
1246
1247                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
1248                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
1249                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
1250                         interrupt-names = "ack", "err", "wakeup";
1251
1252                         rpmcc: clock-controller {
1253                                 compatible      = "qcom,rpmcc-apq8064", "qcom,rpmcc";
1254                                 #clock-cells = <1>;
1255                         };
1256
1257                         regulators {
1258                                 compatible = "qcom,rpm-pm8921-regulators";
1259
1260                                 pm8921_s1: s1 {};
1261                                 pm8921_s2: s2 {};
1262                                 pm8921_s3: s3 {};
1263                                 pm8921_s4: s4 {};
1264                                 pm8921_s7: s7 {};
1265                                 pm8921_s8: s8 {};
1266
1267                                 pm8921_l1: l1 {};
1268                                 pm8921_l2: l2 {};
1269                                 pm8921_l3: l3 {};
1270                                 pm8921_l4: l4 {};
1271                                 pm8921_l5: l5 {};
1272                                 pm8921_l6: l6 {};
1273                                 pm8921_l7: l7 {};
1274                                 pm8921_l8: l8 {};
1275                                 pm8921_l9: l9 {};
1276                                 pm8921_l10: l10 {};
1277                                 pm8921_l11: l11 {};
1278                                 pm8921_l12: l12 {};
1279                                 pm8921_l14: l14 {};
1280                                 pm8921_l15: l15 {};
1281                                 pm8921_l16: l16 {};
1282                                 pm8921_l17: l17 {};
1283                                 pm8921_l18: l18 {};
1284                                 pm8921_l21: l21 {};
1285                                 pm8921_l22: l22 {};
1286                                 pm8921_l23: l23 {};
1287                                 pm8921_l24: l24 {};
1288                                 pm8921_l25: l25 {};
1289                                 pm8921_l26: l26 {};
1290                                 pm8921_l27: l27 {};
1291                                 pm8921_l28: l28 {};
1292                                 pm8921_l29: l29 {};
1293
1294                                 pm8921_lvs1: lvs1 {};
1295                                 pm8921_lvs2: lvs2 {};
1296                                 pm8921_lvs3: lvs3 {};
1297                                 pm8921_lvs4: lvs4 {};
1298                                 pm8921_lvs5: lvs5 {};
1299                                 pm8921_lvs6: lvs6 {};
1300                                 pm8921_lvs7: lvs7 {};
1301
1302                                 pm8921_usb_switch: usb-switch {};
1303
1304                                 pm8921_hdmi_switch: hdmi-switch {
1305                                         bias-pull-down;
1306                                 };
1307
1308                                 pm8921_ncp: ncp {};
1309                         };
1310                 };
1311
1312                 usb1_phy: phy@12500000 {
1313                         compatible      = "qcom,usb-otg-ci";
1314                         reg             = <0x12500000 0x400>;
1315                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1316                         status          = "disabled";
1317                         dr_mode         = "host";
1318
1319                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
1320                                           <&gcc USB_HS1_H_CLK>;
1321                         clock-names     = "core", "iface";
1322
1323                         resets          = <&gcc USB_HS1_RESET>;
1324                         reset-names     = "link";
1325                 };
1326
1327                 usb3_phy: phy@12520000 {
1328                         compatible      = "qcom,usb-otg-ci";
1329                         reg             = <0x12520000 0x400>;
1330                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
1331                         status          = "disabled";
1332                         dr_mode         = "host";
1333
1334                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
1335                                           <&gcc USB_HS3_H_CLK>;
1336                         clock-names     = "core", "iface";
1337
1338                         resets          = <&gcc USB_HS3_RESET>;
1339                         reset-names     = "link";
1340                 };
1341
1342                 usb4_phy: phy@12530000 {
1343                         compatible      = "qcom,usb-otg-ci";
1344                         reg             = <0x12530000 0x400>;
1345                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
1346                         status          = "disabled";
1347                         dr_mode         = "host";
1348
1349                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
1350                                           <&gcc USB_HS4_H_CLK>;
1351                         clock-names     = "core", "iface";
1352
1353                         resets          = <&gcc USB_HS4_RESET>;
1354                         reset-names     = "link";
1355                 };
1356
1357                 gadget1: gadget@12500000 {
1358                         compatible      = "qcom,ci-hdrc";
1359                         reg             = <0x12500000 0x400>;
1360                         status          = "disabled";
1361                         dr_mode         = "peripheral";
1362                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1363                         usb-phy         = <&usb1_phy>;
1364                 };
1365
1366                 usb1: usb@12500000 {
1367                         compatible      = "qcom,ehci-host";
1368                         reg             = <0x12500000 0x400>;
1369                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
1370                         status          = "disabled";
1371                         usb-phy         = <&usb1_phy>;
1372                 };
1373
1374                 usb3: usb@12520000 {
1375                         compatible      = "qcom,ehci-host";
1376                         reg             = <0x12520000 0x400>;
1377                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
1378                         status          = "disabled";
1379                         usb-phy         = <&usb3_phy>;
1380                 };
1381
1382                 usb4: usb@12530000 {
1383                         compatible      = "qcom,ehci-host";
1384                         reg             = <0x12530000 0x400>;
1385                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
1386                         status          = "disabled";
1387                         usb-phy         = <&usb4_phy>;
1388                 };
1389
1390                 sata_phy0: phy@1b400000 {
1391                         compatible      = "qcom,apq8064-sata-phy";
1392                         status          = "disabled";
1393                         reg             = <0x1b400000 0x200>;
1394                         reg-names       = "phy_mem";
1395                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
1396                         clock-names     = "cfg";
1397                         #phy-cells      = <0>;
1398                 };
1399
1400                 sata0: sata@29000000 {
1401                         compatible              = "generic-ahci";
1402                         status                  = "disabled";
1403                         reg                     = <0x29000000 0x180>;
1404                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
1405
1406                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
1407                                                 <&gcc SATA_H_CLK>,
1408                                                 <&gcc SATA_A_CLK>,
1409                                                 <&gcc SATA_RXOOB_CLK>,
1410                                                 <&gcc SATA_PMALIVE_CLK>;
1411                         clock-names             = "slave_iface",
1412                                                 "iface",
1413                                                 "bus",
1414                                                 "rxoob",
1415                                                 "core_pmalive";
1416
1417                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
1418                                                 <&gcc SATA_PMALIVE_CLK>;
1419                         assigned-clock-rates    = <100000000>, <100000000>;
1420
1421                         phys                    = <&sata_phy0>;
1422                         phy-names               = "sata-phy";
1423                 };
1424
1425                 /* Temporary fixed regulator */
1426                 sdcc1bam:dma@12402000{
1427                         compatible = "qcom,bam-v1.3.0";
1428                         reg = <0x12402000 0x8000>;
1429                         interrupts = <0 98 0>;
1430                         clocks = <&gcc SDC1_H_CLK>;
1431                         clock-names = "bam_clk";
1432                         #dma-cells = <1>;
1433                         qcom,ee = <0>;
1434                 };
1435
1436                 sdcc3bam:dma@12182000{
1437                         compatible = "qcom,bam-v1.3.0";
1438                         reg = <0x12182000 0x8000>;
1439                         interrupts = <0 96 0>;
1440                         clocks = <&gcc SDC3_H_CLK>;
1441                         clock-names = "bam_clk";
1442                         #dma-cells = <1>;
1443                         qcom,ee = <0>;
1444                 };
1445
1446                 sdcc4bam:dma@121c2000{
1447                         compatible = "qcom,bam-v1.3.0";
1448                         reg = <0x121c2000 0x8000>;
1449                         interrupts = <0 95 0>;
1450                         clocks = <&gcc SDC4_H_CLK>;
1451                         clock-names = "bam_clk";
1452                         #dma-cells = <1>;
1453                         qcom,ee = <0>;
1454                 };
1455
1456                 amba {
1457                         compatible = "arm,amba-bus";
1458                         #address-cells = <1>;
1459                         #size-cells = <1>;
1460                         ranges;
1461                         sdcc1: sdcc@12400000 {
1462                                 status          = "disabled";
1463                                 compatible      = "arm,pl18x", "arm,primecell";
1464                                 arm,primecell-periphid = <0x00051180>;
1465                                 reg             = <0x12400000 0x2000>;
1466                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1467                                 interrupt-names = "cmd_irq";
1468                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1469                                 clock-names     = "mclk", "apb_pclk";
1470                                 bus-width       = <8>;
1471                                 max-frequency   = <96000000>;
1472                                 non-removable;
1473                                 cap-sd-highspeed;
1474                                 cap-mmc-highspeed;
1475                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1476                                 dma-names = "tx", "rx";
1477                         };
1478
1479                         sdcc3: sdcc@12180000 {
1480                                 compatible      = "arm,pl18x", "arm,primecell";
1481                                 arm,primecell-periphid = <0x00051180>;
1482                                 status          = "disabled";
1483                                 reg             = <0x12180000 0x2000>;
1484                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1485                                 interrupt-names = "cmd_irq";
1486                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1487                                 clock-names     = "mclk", "apb_pclk";
1488                                 bus-width       = <4>;
1489                                 cap-sd-highspeed;
1490                                 cap-mmc-highspeed;
1491                                 max-frequency   = <192000000>;
1492                                 no-1-8-v;
1493                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1494                                 dma-names = "tx", "rx";
1495                         };
1496
1497                         sdcc4: sdcc@121c0000 {
1498                                 compatible      = "arm,pl18x", "arm,primecell";
1499                                 arm,primecell-periphid = <0x00051180>;
1500                                 status          = "disabled";
1501                                 reg             = <0x121c0000 0x2000>;
1502                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1503                                 interrupt-names = "cmd_irq";
1504                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1505                                 clock-names     = "mclk", "apb_pclk";
1506                                 bus-width       = <4>;
1507                                 cap-sd-highspeed;
1508                                 cap-mmc-highspeed;
1509                                 max-frequency   = <48000000>;
1510                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1511                                 dma-names = "tx", "rx";
1512                                 pinctrl-names = "default";
1513                                 pinctrl-0 = <&sdc4_gpios>;
1514                         };
1515                 };
1516
1517                 adm: dma@18320000 {
1518                         compatible = "qcom,adm";
1519                         reg = <0x18320000 0xE0000>;
1520                         interrupts = <GIC_SPI 171 IRQ_TYPE_NONE>;
1521                         #dma-cells = <1>;
1522
1523                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1524                         clock-names = "core", "iface";
1525
1526                         resets = <&gcc ADM0_RESET>,
1527                                  <&gcc ADM0_PBUS_RESET>,
1528                                  <&gcc ADM0_C0_RESET>,
1529                                  <&gcc ADM0_C1_RESET>,
1530                                  <&gcc ADM0_C2_RESET>;
1531                         reset-names = "clk", "pbus", "c0", "c1", "c2";
1532                         qcom,ee = <1>;
1533
1534                         status = "disabled";
1535                 };
1536
1537                 tcsr: syscon@1a400000 {
1538                         compatible = "qcom,tcsr-apq8064", "syscon";
1539                         reg = <0x1a400000 0x100>;
1540                 };
1541
1542                 pcie: pci@1b500000 {
1543                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1544                         reg = <0x1b500000 0x1000
1545                                0x1b502000 0x80
1546                                0x1b600000 0x100
1547                                0x0ff00000 0x100000>;
1548                         reg-names = "dbi", "elbi", "parf", "config";
1549                         device_type = "pci";
1550                         linux,pci-domain = <0>;
1551                         bus-range = <0x00 0xff>;
1552                         num-lanes = <1>;
1553                         #address-cells = <3>;
1554                         #size-cells = <2>;
1555                         ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
1556                                   0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1557                         interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1558                         interrupt-names = "msi";
1559                         #interrupt-cells = <1>;
1560                         interrupt-map-mask = <0 0 0 0x7>;
1561                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1562                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1563                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1564                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1565                         clocks = <&gcc PCIE_A_CLK>,
1566                                  <&gcc PCIE_H_CLK>,
1567                                  <&gcc PCIE_PHY_REF_CLK>;
1568                         clock-names = "core", "iface", "phy";
1569                         resets = <&gcc PCIE_ACLK_RESET>,
1570                                  <&gcc PCIE_HCLK_RESET>,
1571                                  <&gcc PCIE_POR_RESET>,
1572                                  <&gcc PCIE_PCI_RESET>,
1573                                  <&gcc PCIE_PHY_RESET>;
1574                         reset-names = "axi", "ahb", "por", "pci", "phy";
1575                         status = "disabled";
1576                 };
1577
1578                 pil_q6v4: pil@28800000 {
1579                         compatible      = "qcom,tz-pil", "qcom,apq8064-tz-pil";
1580                         qcom,firmware-name = "q6";
1581                         reg             = <0x28800000 0x100>;
1582                         reg-names       = "qdsp6_base";
1583                         qcom,pas-id             = <1>; /* PAS_Q6 */
1584                 };
1585
1586                 smd {
1587                         compatible = "qcom,smd";
1588                         adsp_a11 {
1589                                 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
1590                                 qcom,ipc = <&l2cc 8 15>;
1591                                 qcom,smd-edge = <1>;
1592                                 qcom,remote-pid = <0x2>;
1593                                 q6_requests {
1594                                         compatible      = "qcom,apr";
1595                                         qcom,smd-channels = "apr_audio_svc";
1596                                         rproc = <&pil_q6v4>;
1597                                 };
1598                         };
1599                 };
1600
1601                 dai_fe: dai_fe {
1602                         compatible      = "qcom,msm-dai-fe";
1603                         #sound-dai-cells = <0>;
1604                 };
1605
1606                 hdmi_dai: dai_hdmi {
1607                         compatible = "qcom,msm-dai-q6-hdmi";
1608                         #sound-dai-cells = <0>;
1609                 };
1610
1611                 hdmi_codec: codec_hdmi {
1612                         compatible = "linux,hdmi-audio";
1613                         #sound-dai-cells = <0>;
1614                 };
1615
1616                 q6_pcm: msm_pcm {
1617                         compatible = "qcom,msm-pcm-dsp";
1618                         #sound-dai-cells = <0>;
1619                 };
1620
1621                 q6_route: msm_pcm_routing {
1622                         compatible = "qcom,msm-pcm-routing";
1623                         #sound-dai-cells = <0>;
1624                 };
1625
1626                 snd {
1627                         compatible      = "qcom,snd-apq8064";
1628                 };
1629
1630
1631                 hdmi: qcom,hdmi-tx@4a00000 {
1632                         compatible = "qcom,hdmi-tx-8960";
1633                         reg-names = "core_physical";
1634                         reg = <0x04a00000 0x1000>;
1635                         interrupts = <GIC_SPI 79 0>;
1636                         clock-names =
1637                             "core_clk",
1638                             "master_iface_clk",
1639                             "slave_iface_clk";
1640                         clocks =
1641                             <&mmcc HDMI_APP_CLK>,
1642                             <&mmcc HDMI_M_AHB_CLK>,
1643                             <&mmcc HDMI_S_AHB_CLK>;
1644                         qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>;
1645                         qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>;
1646                         qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
1647                         pinctrl-names = "default";
1648                         pinctrl-0 = <&hdmi_pinctrl>;
1649                 };
1650
1651                 gpu: qcom,adreno-3xx@4300000 {
1652                         compatible = "qcom,adreno-3xx";
1653                         reg = <0x04300000 0x20000>;
1654                         reg-names = "kgsl_3d0_reg_memory";
1655                         interrupts = <GIC_SPI 80 0>;
1656                         interrupt-names = "kgsl_3d0_irq";
1657                         clock-names =
1658                             "core_clk",
1659                             "iface_clk",
1660                             "mem_clk",
1661                             "mem_iface_clk";
1662                         clocks =
1663                             <&mmcc GFX3D_CLK>,
1664                             <&mmcc GFX3D_AHB_CLK>,
1665                             <&mmcc GFX3D_AXI_CLK>,
1666                             <&mmcc MMSS_IMEM_AHB_CLK>;
1667                         qcom,chipid = <0x03020002>;
1668
1669                          iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1670                                    &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1671                                    &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1672                                    &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
1673
1674                         qcom,gpu-pwrlevels {
1675                                 compatible = "qcom,gpu-pwrlevels";
1676                                 qcom,gpu-pwrlevel@0 {
1677                                         qcom,gpu-freq = <450000000>;
1678                                 };
1679                                 qcom,gpu-pwrlevel@1 {
1680                                         qcom,gpu-freq = <27000000>;
1681                                 };
1682                         };
1683                 };
1684
1685                 mdp: qcom,mdp@5100000 {
1686                         compatible = "qcom,mdp";
1687                         reg = <0x05100000 0xf0000>;
1688                         interrupts = <GIC_SPI 75 0>;
1689                         connectors = <&hdmi>;
1690                         gpus = <&gpu>;
1691                         clock-names =
1692                             "core_clk",
1693                             "iface_clk",
1694                             "lut_clk",
1695                             "src_clk",
1696                             "hdmi_clk",
1697                             "mdp_clk",
1698                             "mdp_axi_clk";
1699                         clocks =
1700                             <&mmcc MDP_CLK>,
1701                             <&mmcc MDP_AHB_CLK>,
1702                             <&mmcc MDP_LUT_CLK>,
1703                             <&mmcc TV_SRC>,
1704                             <&mmcc HDMI_TV_CLK>,
1705                             <&mmcc MDP_TV_CLK>,
1706                             <&mmcc MDP_AXI_CLK>;
1707
1708                         iommus = <&mdp_port0 0 2
1709                                   &mdp_port1 0 2>;
1710                 };
1711
1712                 mdp_port0: qcom,iommu@7500000 {
1713                         compatible = "qcom,iommu-v0";
1714                         #iommu-cells = <2>;
1715                         clock-names =
1716                             "smmu_pclk",
1717                             "iommu_clk";
1718                         clocks =
1719                             <&mmcc SMMU_AHB_CLK>,
1720                             <&mmcc MDP_AXI_CLK>;
1721                         reg = <0x07500000 0x100000>;
1722                         interrupts =
1723                             <GIC_SPI 63 0>,
1724                             <GIC_SPI 64 0>;
1725                         ncb = <2>;
1726                 };
1727
1728                 mdp_port1: qcom,iommu@7600000 {
1729                         compatible = "qcom,iommu";
1730                         #iommu-cells = <2>;
1731                         clock-names =
1732                             "smmu_pclk",
1733                             "iommu_clk";
1734                         clocks =
1735                             <&mmcc SMMU_AHB_CLK>,
1736                             <&mmcc MDP_AXI_CLK>;
1737                         reg = <0x07600000 0x100000>;
1738                         interrupts =
1739                             <GIC_SPI 61 0>,
1740                             <GIC_SPI 62 0>;
1741                         ncb = <2>;
1742                 };
1743
1744                 gfx3d: qcom,iommu@7c00000 {
1745                         compatible = "qcom,iommu-v0";
1746                         #iommu-cells = <16>;
1747                         clock-names =
1748                             "smmu_pclk",
1749                             "iommu_clk";
1750                         clocks =
1751                             <&mmcc SMMU_AHB_CLK>,
1752                             <&mmcc GFX3D_AXI_CLK>;
1753                         reg = <0x07c00000 0x100000>;
1754                         interrupts =
1755                             <GIC_SPI 69 0>,
1756                             <GIC_SPI 70 0>;
1757                         ncb = <3>;
1758                 };
1759
1760                 gfx3d1: qcom,iommu@7d00000 {
1761                         compatible = "qcom,iommu-v0";
1762                         #iommu-cells = <16>;
1763                         clock-names =
1764                             "smmu_pclk",
1765                             "iommu_clk";
1766                         clocks =
1767                             <&mmcc SMMU_AHB_CLK>,
1768                             <&mmcc GFX3D_AXI_CLK>;
1769                         reg = <0x07d00000 0x100000>;
1770                         interrupts =
1771                             <GIC_SPI 210 0>,
1772                             <GIC_SPI 211 0>;
1773                         ncb = <3>;
1774                 };
1775         };
1776 };
1777
1778 #include "qcom-apq8064-coresight.dtsi"