arch/arm/boot/dts/qcom-apq8064.dtsi

   1 /dts-v1/;
   2
   3 #include "skeleton.dtsi"
   4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
   5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
   6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
   7 #include <dt-bindings/soc/qcom,gsbi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 / {
  10         model = "Qualcomm APQ8064";
  11         compatible = "qcom,apq8064";
  12         interrupt-parent = <&intc>;
  13
  14         reserved-memory {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18
  19                 smem_region: smem@80000000 {
  20                         reg = <0x80000000 0x200000>;
  21                         no-map;
  22                 };
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         compatible = "qcom,krait";
  31                         enable-method = "qcom,kpss-acc-v1";
  32                         device_type = "cpu";
  33                         reg = <0>;
  34                         next-level-cache = <&L2>;
  35                         qcom,acc = <&acc0>;
  36                         qcom,saw = <&saw0>;
  37                         cpu-idle-states = <&CPU_SPC>;
  38                 };
  39
  40                 cpu@1 {
  41                         compatible = "qcom,krait";
  42                         enable-method = "qcom,kpss-acc-v1";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                         next-level-cache = <&L2>;
  46                         qcom,acc = <&acc1>;
  47                         qcom,saw = <&saw1>;
  48                         cpu-idle-states = <&CPU_SPC>;
  49                 };
  50
  51                 cpu@2 {
  52                         compatible = "qcom,krait";
  53                         enable-method = "qcom,kpss-acc-v1";
  54                         device_type = "cpu";
  55                         reg = <2>;
  56                         next-level-cache = <&L2>;
  57                         qcom,acc = <&acc2>;
  58                         qcom,saw = <&saw2>;
  59                         cpu-idle-states = <&CPU_SPC>;
  60                 };
  61
  62                 cpu@3 {
  63                         compatible = "qcom,krait";
  64                         enable-method = "qcom,kpss-acc-v1";
  65                         device_type = "cpu";
  66                         reg = <3>;
  67                         next-level-cache = <&L2>;
  68                         qcom,acc = <&acc3>;
  69                         qcom,saw = <&saw3>;
  70                         cpu-idle-states = <&CPU_SPC>;
  71                 };
  72
  73                 L2: l2-cache {
  74                         compatible = "cache";
  75                         cache-level = <2>;
  76                 };
  77
  78                 idle-states {
  79                         CPU_SPC: spc {
  80                                 compatible = "qcom,idle-state-spc",
  81                                                 "arm,idle-state";
  82                                 entry-latency-us = <400>;
  83                                 exit-latency-us = <900>;
  84                                 min-residency-us = <3000>;
  85                         };
  86                 };
  87         };
  88
  89         cpu-pmu {
  90                 compatible = "qcom,krait-pmu";
  91                 interrupts = <1 10 0x304>;
  92         };
  93
  94         sfpb_mutex: hwmutex {
  95                 compatible = "qcom,sfpb-mutex";
  96                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
  97                 #hwlock-cells = <1>;
  98         };
  99
 100         smem {
 101                 compatible = "qcom,smem";
 102                 memory-region = <&smem_region>;
 103
 104                 hwlocks = <&sfpb_mutex 3>;
 105         };
 106
 107         soc: soc {
 108                 #address-cells = <1>;
 109                 #size-cells = <1>;
 110                 ranges;
 111                 compatible = "simple-bus";
 112
 113                 tlmm_pinmux: pinctrl@800000 {
 114                         compatible = "qcom,apq8064-pinctrl";
 115                         reg = <0x800000 0x4000>;
 116
 117                         gpio-controller;
 118                         #gpio-cells = <2>;
 119                         interrupt-controller;
 120                         #interrupt-cells = <2>;
 121                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
 122
 123                         pinctrl-names = "default";
 124                         pinctrl-0 = <&ps_hold>;
 125
 126                         sdc4_gpios: sdc4-gpios {
 127                                 pios {
 128                                         pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
 129                                         function = "sdc4";
 130                                 };
 131                         };
 132
 133                         ps_hold: ps_hold {
 134                                 mux {
 135                                         pins = "gpio78";
 136                                         function = "ps_hold";
 137                                 };
 138                         };
 139
 140                         i2c1_pins: i2c1 {
 141                                 mux {
 142                                         pins = "gpio20", "gpio21";
 143                                         function = "gsbi1";
 144                                 };
 145                         };
 146
 147                         i2c3_pins: i2c3 {
 148                                 mux {
 149                                         pins = "gpio8", "gpio9";
 150                                         function = "gsbi3";
 151                                 };
 152                         };
 153
 154                         gsbi6_uart_2pins: gsbi6_uart_2pins {
 155                                 mux {
 156                                         pins = "gpio14", "gpio15";
 157                                         function = "gsbi6";
 158                                 };
 159                         };
 160
 161                         gsbi6_uart_4pins: gsbi6_uart_4pins {
 162                                 mux {
 163                                         pins = "gpio14", "gpio15", "gpio16", "gpio17";
 164                                         function = "gsbi6";
 165                                 };
 166                         };
 167
 168                         gsbi7_uart_2pins: gsbi7_uart_2pins {
 169                                 mux {
 170                                         pins = "gpio82", "gpio83";
 171                                         function = "gsbi7";
 172                                 };
 173                         };
 174
 175                         gsbi7_uart_4pins: gsbi7_uart_4pins {
 176                                 mux {
 177                                         pins = "gpio82", "gpio83", "gpio84", "gpio85";
 178                                         function = "gsbi7";
 179                                 };
 180                         };
 181                 };
 182
 183                 sfpb_wrapper_mutex: syscon@1200000 {
 184                         compatible = "syscon";
 185                         reg = <0x01200000 0x8000>;
 186                 };
 187
 188                 intc: interrupt-controller@2000000 {
 189                         compatible = "qcom,msm-qgic2";
 190                         interrupt-controller;
 191                         #interrupt-cells = <3>;
 192                         reg = <0x02000000 0x1000>,
 193                               <0x02002000 0x1000>;
 194                 };
 195
 196                 timer@200a000 {
 197                         compatible = "qcom,kpss-timer", "qcom,msm-timer";
 198                         interrupts = <1 1 0x301>,
 199                                      <1 2 0x301>,
 200                                      <1 3 0x301>;
 201                         reg = <0x0200a000 0x100>;
 202                         clock-frequency = <27000000>,
 203                                           <32768>;
 204                         cpu-offset = <0x80000>;
 205                 };
 206
 207                 acc0: clock-controller@2088000 {
 208                         compatible = "qcom,kpss-acc-v1";
 209                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 210                 };
 211
 212                 acc1: clock-controller@2098000 {
 213                         compatible = "qcom,kpss-acc-v1";
 214                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 215                 };
 216
 217                 acc2: clock-controller@20a8000 {
 218                         compatible = "qcom,kpss-acc-v1";
 219                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
 220                 };
 221
 222                 acc3: clock-controller@20b8000 {
 223                         compatible = "qcom,kpss-acc-v1";
 224                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
 225                 };
 226
 227                 saw0: power-controller@2089000 {
 228                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 229                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 230                         regulator;
 231                 };
 232
 233                 saw1: power-controller@2099000 {
 234                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 235                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 236                         regulator;
 237                 };
 238
 239                 saw2: power-controller@20a9000 {
 240                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 241                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
 242                         regulator;
 243                 };
 244
 245                 saw3: power-controller@20b9000 {
 246                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
 247                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
 248                         regulator;
 249                 };
 250
 251                 gsbi1: gsbi@12440000 {
 252                         status = "disabled";
 253                         compatible = "qcom,gsbi-v1.0.0";
 254                         cell-index = <1>;
 255                         reg = <0x12440000 0x100>;
 256                         clocks = <&gcc GSBI1_H_CLK>;
 257                         clock-names = "iface";
 258                         #address-cells = <1>;
 259                         #size-cells = <1>;
 260                         ranges;
 261
 262                         syscon-tcsr = <&tcsr>;
 263
 264                         i2c1: i2c@12460000 {
 265                                 compatible = "qcom,i2c-qup-v1.1.1";
 266                                 pinctrl-0 = <&i2c1_pins>;
 267                                 pinctrl-names = "default";
 268                                 reg = <0x12460000 0x1000>;
 269                                 interrupts = <0 194 IRQ_TYPE_NONE>;
 270                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
 271                                 clock-names = "core", "iface";
 272                                 #address-cells = <1>;
 273                                 #size-cells = <0>;
 274                         };
 275                 };
 276
 277                 gsbi2: gsbi@12480000 {
 278                         status = "disabled";
 279                         compatible = "qcom,gsbi-v1.0.0";
 280                         cell-index = <2>;
 281                         reg = <0x12480000 0x100>;
 282                         clocks = <&gcc GSBI2_H_CLK>;
 283                         clock-names = "iface";
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286                         ranges;
 287
 288                         syscon-tcsr = <&tcsr>;
 289
 290                         i2c2: i2c@124a0000 {
 291                                 compatible = "qcom,i2c-qup-v1.1.1";
 292                                 reg = <0x124a0000 0x1000>;
 293                                 interrupts = <0 196 IRQ_TYPE_NONE>;
 294                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
 295                                 clock-names = "core", "iface";
 296                                 #address-cells = <1>;
 297                                 #size-cells = <0>;
 298                         };
 299                 };
 300
 301                 gsbi3: gsbi@16200000 {
 302                         status = "disabled";
 303                         compatible = "qcom,gsbi-v1.0.0";
 304                         cell-index = <3>;
 305                         reg = <0x16200000 0x100>;
 306                         clocks = <&gcc GSBI3_H_CLK>;
 307                         clock-names = "iface";
 308                         #address-cells = <1>;
 309                         #size-cells = <1>;
 310                         ranges;
 311                         i2c3: i2c@16280000 {
 312                                 compatible = "qcom,i2c-qup-v1.1.1";
 313                                 pinctrl-0 = <&i2c3_pins>;
 314                                 pinctrl-names = "default";
 315                                 reg = <0x16280000 0x1000>;
 316                                 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
 317                                 clocks = <&gcc GSBI3_QUP_CLK>,
 318                                          <&gcc GSBI3_H_CLK>;
 319                                 clock-names = "core", "iface";
 320                         };
 321                 };
 322
 323                 gsbi6: gsbi@16500000 {
 324                         status = "disabled";
 325                         compatible = "qcom,gsbi-v1.0.0";
 326                         cell-index = <6>;
 327                         reg = <0x16500000 0x03>;
 328                         clocks = <&gcc GSBI6_H_CLK>;
 329                         clock-names = "iface";
 330                         #address-cells = <1>;
 331                         #size-cells = <1>;
 332                         ranges;
 333
 334                         gsbi6_serial: serial@16540000 {
 335                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 336                                 reg = <0x16540000 0x100>,
 337                                       <0x16500000 0x03>;
 338                                 interrupts = <0 156 0x0>;
 339                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
 340                                 clock-names = "core", "iface";
 341                                 status = "disabled";
 342                         };
 343                 };
 344
 345                 gsbi7: gsbi@16600000 {
 346                         status = "disabled";
 347                         compatible = "qcom,gsbi-v1.0.0";
 348                         cell-index = <7>;
 349                         reg = <0x16600000 0x100>;
 350                         clocks = <&gcc GSBI7_H_CLK>;
 351                         clock-names = "iface";
 352                         #address-cells = <1>;
 353                         #size-cells = <1>;
 354                         ranges;
 355                         syscon-tcsr = <&tcsr>;
 356
 357                         gsbi7_serial: serial@16640000 {
 358                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 359                                 reg = <0x16640000 0x1000>,
 360                                       <0x16600000 0x1000>;
 361                                 interrupts = <0 158 0x0>;
 362                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
 363                                 clock-names = "core", "iface";
 364                                 status = "disabled";
 365                         };
 366                 };
 367
 368                 rng@1a500000 {
 369                         compatible = "qcom,prng";
 370                         reg = <0x1a500000 0x200>;
 371                         clocks = <&gcc PRNG_CLK>;
 372                         clock-names = "core";
 373                 };
 374
 375                 qcom,ssbi@500000 {
 376                         compatible = "qcom,ssbi";
 377                         reg = <0x00500000 0x1000>;
 378                         qcom,controller-type = "pmic-arbiter";
 379
 380                         pmicintc: pmic@0 {
 381                                 compatible = "qcom,pm8921";
 382                                 interrupt-parent = <&tlmm_pinmux>;
 383                                 interrupts = <74 8>;
 384                                 #interrupt-cells = <2>;
 385                                 interrupt-controller;
 386                                 #address-cells = <1>;
 387                                 #size-cells = <0>;
 388
 389                                 pm8921_gpio: gpio@150 {
 390
 391                                         compatible = "qcom,pm8921-gpio";
 392                                         reg = <0x150>;
 393                                         interrupts = <192 1>, <193 1>, <194 1>,
 394                                                      <195 1>, <196 1>, <197 1>,
 395                                                      <198 1>, <199 1>, <200 1>,
 396                                                      <201 1>, <202 1>, <203 1>,
 397                                                      <204 1>, <205 1>, <206 1>,
 398                                                      <207 1>, <208 1>, <209 1>,
 399                                                      <210 1>, <211 1>, <212 1>,
 400                                                      <213 1>, <214 1>, <215 1>,
 401                                                      <216 1>, <217 1>, <218 1>,
 402                                                      <219 1>, <220 1>, <221 1>,
 403                                                      <222 1>, <223 1>, <224 1>,
 404                                                      <225 1>, <226 1>, <227 1>,
 405                                                      <228 1>, <229 1>, <230 1>,
 406                                                      <231 1>, <232 1>, <233 1>,
 407                                                      <234 1>, <235 1>;
 408
 409                                         gpio-controller;
 410                                         #gpio-cells = <2>;
 411
 412                                 };
 413
 414                                 pm8921_mpps: mpps@50 {
 415                                         compatible = "qcom,pm8921-mpp";
 416                                         reg = <0x50>;
 417                                         gpio-controller;
 418                                         #gpio-cells = <2>;
 419                                         interrupts =
 420                                         <128 1>, <129 1>, <130 1>, <131 1>,
 421                                         <132 1>, <133 1>, <134 1>, <135 1>,
 422                                         <136 1>, <137 1>, <138 1>, <139 1>;
 423                                 };
 424
 425                                 rtc@11d {
 426                                         compatible = "qcom,pm8921-rtc";
 427                                         interrupt-parent = <&pmicintc>;
 428                                         interrupts = <39 1>;
 429                                         reg = <0x11d>;
 430                                         allow-set-time;
 431                                 };
 432
 433                                 pwrkey@1c {
 434                                         compatible = "qcom,pm8921-pwrkey";
 435                                         reg = <0x1c>;
 436                                         interrupt-parent = <&pmicintc>;
 437                                         interrupts = <50 1>, <51 1>;
 438                                         debounce = <15625>;
 439                                         pull-up;
 440                                 };
 441                         };
 442                 };
 443
 444                 gcc: clock-controller@900000 {
 445                         compatible = "qcom,gcc-apq8064";
 446                         reg = <0x00900000 0x4000>;
 447                         #clock-cells = <1>;
 448                         #reset-cells = <1>;
 449                 };
 450
 451                 lcc: clock-controller@28000000 {
 452                         compatible = "qcom,lcc-apq8064";
 453                         reg = <0x28000000 0x1000>;
 454                         #clock-cells = <1>;
 455                         #reset-cells = <1>;
 456                 };
 457
 458                 mmcc: clock-controller@4000000 {
 459                         compatible = "qcom,mmcc-apq8064";
 460                         reg = <0x4000000 0x1000>;
 461                         #clock-cells = <1>;
 462                         #reset-cells = <1>;
 463                 };
 464
 465                 l2cc: clock-controller@2011000 {
 466                         compatible      = "syscon";
 467                         reg             = <0x2011000 0x1000>;
 468                 };
 469
 470                 rpm@108000 {
 471                         compatible      = "qcom,rpm-apq8064";
 472                         reg             = <0x108000 0x1000>;
 473                         qcom,ipc        = <&l2cc 0x8 2>;
 474
 475                         interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
 476                                           <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
 477                                           <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
 478                         interrupt-names = "ack", "err", "wakeup";
 479
 480                         regulators {
 481                                 compatible = "qcom,rpm-pm8921-regulators";
 482
 483                                 pm8921_s1: s1 {};
 484                                 pm8921_s2: s2 {};
 485                                 pm8921_s3: s3 {};
 486                                 pm8921_s4: s4 {};
 487                                 pm8921_s7: s7 {};
 488                                 pm8921_s8: s8 {};
 489
 490                                 pm8921_l1: l1 {};
 491                                 pm8921_l2: l2 {};
 492                                 pm8921_l3: l3 {};
 493                                 pm8921_l4: l4 {};
 494                                 pm8921_l5: l5 {};
 495                                 pm8921_l6: l6 {};
 496                                 pm8921_l7: l7 {};
 497                                 pm8921_l8: l8 {};
 498                                 pm8921_l9: l9 {};
 499                                 pm8921_l10: l10 {};
 500                                 pm8921_l11: l11 {};
 501                                 pm8921_l12: l12 {};
 502                                 pm8921_l14: l14 {};
 503                                 pm8921_l15: l15 {};
 504                                 pm8921_l16: l16 {};
 505                                 pm8921_l17: l17 {};
 506                                 pm8921_l18: l18 {};
 507                                 pm8921_l21: l21 {};
 508                                 pm8921_l22: l22 {};
 509                                 pm8921_l23: l23 {};
 510                                 pm8921_l24: l24 {};
 511                                 pm8921_l25: l25 {};
 512                                 pm8921_l26: l26 {};
 513                                 pm8921_l27: l27 {};
 514                                 pm8921_l28: l28 {};
 515                                 pm8921_l29: l29 {};
 516
 517                                 pm8921_lvs1: lvs1 {};
 518                                 pm8921_lvs2: lvs2 {};
 519                                 pm8921_lvs3: lvs3 {};
 520                                 pm8921_lvs4: lvs4 {};
 521                                 pm8921_lvs5: lvs5 {};
 522                                 pm8921_lvs6: lvs6 {};
 523                                 pm8921_lvs7: lvs7 {};
 524
 525                                 pm8921_usb_switch: usb-switch {};
 526
 527                                 pm8921_hdmi_switch: hdmi-switch {
 528                                         bias-pull-down;
 529                                 };
 530
 531                                 pm8921_ncp: ncp {};
 532                         };
 533                 };
 534
 535                 usb1_phy: phy@12500000 {
 536                         compatible      = "qcom,usb-otg-ci";
 537                         reg             = <0x12500000 0x400>;
 538                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 539                         status          = "disabled";
 540                         dr_mode         = "host";
 541
 542                         clocks          = <&gcc USB_HS1_XCVR_CLK>,
 543                                           <&gcc USB_HS1_H_CLK>;
 544                         clock-names     = "core", "iface";
 545
 546                         resets          = <&gcc USB_HS1_RESET>;
 547                         reset-names     = "link";
 548                 };
 549
 550                 usb3_phy: phy@12520000 {
 551                         compatible      = "qcom,usb-otg-ci";
 552                         reg             = <0x12520000 0x400>;
 553                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 554                         status          = "disabled";
 555                         dr_mode         = "host";
 556
 557                         clocks          = <&gcc USB_HS3_XCVR_CLK>,
 558                                           <&gcc USB_HS3_H_CLK>;
 559                         clock-names     = "core", "iface";
 560
 561                         resets          = <&gcc USB_HS3_RESET>;
 562                         reset-names     = "link";
 563                 };
 564
 565                 usb4_phy: phy@12530000 {
 566                         compatible      = "qcom,usb-otg-ci";
 567                         reg             = <0x12530000 0x400>;
 568                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 569                         status          = "disabled";
 570                         dr_mode         = "host";
 571
 572                         clocks          = <&gcc USB_HS4_XCVR_CLK>,
 573                                           <&gcc USB_HS4_H_CLK>;
 574                         clock-names     = "core", "iface";
 575
 576                         resets          = <&gcc USB_HS4_RESET>;
 577                         reset-names     = "link";
 578                 };
 579
 580                 gadget1: gadget@12500000 {
 581                         compatible      = "qcom,ci-hdrc";
 582                         reg             = <0x12500000 0x400>;
 583                         status          = "disabled";
 584                         dr_mode         = "peripheral";
 585                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 586                         usb-phy         = <&usb1_phy>;
 587                 };
 588
 589                 usb1: usb@12500000 {
 590                         compatible      = "qcom,ehci-host";
 591                         reg             = <0x12500000 0x400>;
 592                         interrupts      = <GIC_SPI 100 IRQ_TYPE_NONE>;
 593                         status          = "disabled";
 594                         usb-phy         = <&usb1_phy>;
 595                 };
 596
 597                 usb3: usb@12520000 {
 598                         compatible      = "qcom,ehci-host";
 599                         reg             = <0x12520000 0x400>;
 600                         interrupts      = <GIC_SPI 188 IRQ_TYPE_NONE>;
 601                         status          = "disabled";
 602                         usb-phy         = <&usb3_phy>;
 603                 };
 604
 605                 usb4: usb@12530000 {
 606                         compatible      = "qcom,ehci-host";
 607                         reg             = <0x12530000 0x400>;
 608                         interrupts      = <GIC_SPI 215 IRQ_TYPE_NONE>;
 609                         status          = "disabled";
 610                         usb-phy         = <&usb4_phy>;
 611                 };
 612
 613                 sata_phy0: phy@1b400000 {
 614                         compatible      = "qcom,apq8064-sata-phy";
 615                         status          = "disabled";
 616                         reg             = <0x1b400000 0x200>;
 617                         reg-names       = "phy_mem";
 618                         clocks          = <&gcc SATA_PHY_CFG_CLK>;
 619                         clock-names     = "cfg";
 620                         #phy-cells      = <0>;
 621                 };
 622
 623                 sata0: sata@29000000 {
 624                         compatible              = "generic-ahci";
 625                         status                  = "disabled";
 626                         reg                     = <0x29000000 0x180>;
 627                         interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
 628
 629                         clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
 630                                                 <&gcc SATA_H_CLK>,
 631                                                 <&gcc SATA_A_CLK>,
 632                                                 <&gcc SATA_RXOOB_CLK>,
 633                                                 <&gcc SATA_PMALIVE_CLK>;
 634                         clock-names             = "slave_iface",
 635                                                 "iface",
 636                                                 "bus",
 637                                                 "rxoob",
 638                                                 "core_pmalive";
 639
 640                         assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
 641                                                 <&gcc SATA_PMALIVE_CLK>;
 642                         assigned-clock-rates    = <100000000>, <100000000>;
 643
 644                         phys                    = <&sata_phy0>;
 645                         phy-names               = "sata-phy";
 646                 };
 647
 648                 /* Temporary fixed regulator */
 649                 sdcc1bam:dma@12402000{
 650                         compatible = "qcom,bam-v1.3.0";
 651                         reg = <0x12402000 0x8000>;
 652                         interrupts = <0 98 0>;
 653                         clocks = <&gcc SDC1_H_CLK>;
 654                         clock-names = "bam_clk";
 655                         #dma-cells = <1>;
 656                         qcom,ee = <0>;
 657                 };
 658
 659                 sdcc3bam:dma@12182000{
 660                         compatible = "qcom,bam-v1.3.0";
 661                         reg = <0x12182000 0x8000>;
 662                         interrupts = <0 96 0>;
 663                         clocks = <&gcc SDC3_H_CLK>;
 664                         clock-names = "bam_clk";
 665                         #dma-cells = <1>;
 666                         qcom,ee = <0>;
 667                 };
 668
 669                 sdcc4bam:dma@121c2000{
 670                         compatible = "qcom,bam-v1.3.0";
 671                         reg = <0x121c2000 0x8000>;
 672                         interrupts = <0 95 0>;
 673                         clocks = <&gcc SDC4_H_CLK>;
 674                         clock-names = "bam_clk";
 675                         #dma-cells = <1>;
 676                         qcom,ee = <0>;
 677                 };
 678
 679                 amba {
 680                         compatible = "arm,amba-bus";
 681                         #address-cells = <1>;
 682                         #size-cells = <1>;
 683                         ranges;
 684                         sdcc1: sdcc@12400000 {
 685                                 status          = "disabled";
 686                                 compatible      = "arm,pl18x", "arm,primecell";
 687                                 arm,primecell-periphid = <0x00051180>;
 688                                 reg             = <0x12400000 0x2000>;
 689                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 690                                 interrupt-names = "cmd_irq";
 691                                 clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 692                                 clock-names     = "mclk", "apb_pclk";
 693                                 bus-width       = <8>;
 694                                 max-frequency   = <96000000>;
 695                                 non-removable;
 696                                 cap-sd-highspeed;
 697                                 cap-mmc-highspeed;
 698                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 699                                 dma-names = "tx", "rx";
 700                         };
 701
 702                         sdcc3: sdcc@12180000 {
 703                                 compatible      = "arm,pl18x", "arm,primecell";
 704                                 arm,primecell-periphid = <0x00051180>;
 705                                 status          = "disabled";
 706                                 reg             = <0x12180000 0x2000>;
 707                                 interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 708                                 interrupt-names = "cmd_irq";
 709                                 clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 710                                 clock-names     = "mclk", "apb_pclk";
 711                                 bus-width       = <4>;
 712                                 cap-sd-highspeed;
 713                                 cap-mmc-highspeed;
 714                                 max-frequency   = <192000000>;
 715                                 no-1-8-v;
 716                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 717                                 dma-names = "tx", "rx";
 718                         };
 719
 720                         sdcc4: sdcc@121c0000 {
 721                                 compatible      = "arm,pl18x", "arm,primecell";
 722                                 arm,primecell-periphid = <0x00051180>;
 723                                 status          = "disabled";
 724                                 reg             = <0x121c0000 0x2000>;
 725                                 interrupts      = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 726                                 interrupt-names = "cmd_irq";
 727                                 clocks          = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 728                                 clock-names     = "mclk", "apb_pclk";
 729                                 bus-width       = <4>;
 730                                 cap-sd-highspeed;
 731                                 cap-mmc-highspeed;
 732                                 max-frequency   = <48000000>;
 733                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 734                                 dma-names = "tx", "rx";
 735                                 pinctrl-names = "default";
 736                                 pinctrl-0 = <&sdc4_gpios>;
 737                         };
 738                 };
 739
 740                 tcsr: syscon@1a400000 {
 741                         compatible = "qcom,tcsr-apq8064", "syscon";
 742                         reg = <0x1a400000 0x100>;
 743                 };
 744         };
 745 };