arch/arm/boot/dts/tegra30.dtsi

   1 #include <dt-bindings/clock/tegra30-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra30";
  10         interrupt-parent = <&intc>;
  11
  12         aliases {
  13                 serial0 = &uarta;
  14                 serial1 = &uartb;
  15                 serial2 = &uartc;
  16                 serial3 = &uartd;
  17                 serial4 = &uarte;
  18         };
  19
  20         pcie-controller@00003000 {
  21                 compatible = "nvidia,tegra30-pcie";
  22                 device_type = "pci";
  23                 reg = <0x00003000 0x00000800   /* PADS registers */
  24                        0x00003800 0x00000200   /* AFI registers */
  25                        0x10000000 0x10000000>; /* configuration space */
  26                 reg-names = "pads", "afi", "cs";
  27                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  28                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  29                 interrupt-names = "intr", "msi";
  30
  31                 bus-range = <0x00 0xff>;
  32                 #address-cells = <3>;
  33                 #size-cells = <2>;
  34
  35                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  36                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  37                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  38                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  39                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  40                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  41
  42                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  43                          <&tegra_car TEGRA30_CLK_AFI>,
  44                          <&tegra_car TEGRA30_CLK_PLL_E>,
  45                          <&tegra_car TEGRA30_CLK_CML0>;
  46                 clock-names = "pex", "afi", "pll_e", "cml";
  47                 resets = <&tegra_car 70>,
  48                          <&tegra_car 72>,
  49                          <&tegra_car 74>;
  50                 reset-names = "pex", "afi", "pcie_x";
  51                 status = "disabled";
  52
  53                 pci@1,0 {
  54                         device_type = "pci";
  55                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  56                         reg = <0x000800 0 0 0 0>;
  57                         status = "disabled";
  58
  59                         #address-cells = <3>;
  60                         #size-cells = <2>;
  61                         ranges;
  62
  63                         nvidia,num-lanes = <2>;
  64                 };
  65
  66                 pci@2,0 {
  67                         device_type = "pci";
  68                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  69                         reg = <0x001000 0 0 0 0>;
  70                         status = "disabled";
  71
  72                         #address-cells = <3>;
  73                         #size-cells = <2>;
  74                         ranges;
  75
  76                         nvidia,num-lanes = <2>;
  77                 };
  78
  79                 pci@3,0 {
  80                         device_type = "pci";
  81                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  82                         reg = <0x001800 0 0 0 0>;
  83                         status = "disabled";
  84
  85                         #address-cells = <3>;
  86                         #size-cells = <2>;
  87                         ranges;
  88
  89                         nvidia,num-lanes = <2>;
  90                 };
  91         };
  92
  93         host1x@50000000 {
  94                 compatible = "nvidia,tegra30-host1x", "simple-bus";
  95                 reg = <0x50000000 0x00024000>;
  96                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  97                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  98                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
  99                 resets = <&tegra_car 28>;
 100                 reset-names = "host1x";
 101
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104
 105                 ranges = <0x54000000 0x54000000 0x04000000>;
 106
 107                 mpe@54040000 {
 108                         compatible = "nvidia,tegra30-mpe";
 109                         reg = <0x54040000 0x00040000>;
 110                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 111                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 112                         resets = <&tegra_car 60>;
 113                         reset-names = "mpe";
 114                 };
 115
 116                 vi@54080000 {
 117                         compatible = "nvidia,tegra30-vi";
 118                         reg = <0x54080000 0x00040000>;
 119                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 120                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 121                         resets = <&tegra_car 20>;
 122                         reset-names = "vi";
 123                 };
 124
 125                 epp@540c0000 {
 126                         compatible = "nvidia,tegra30-epp";
 127                         reg = <0x540c0000 0x00040000>;
 128                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 129                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 130                         resets = <&tegra_car 19>;
 131                         reset-names = "epp";
 132                 };
 133
 134                 isp@54100000 {
 135                         compatible = "nvidia,tegra30-isp";
 136                         reg = <0x54100000 0x00040000>;
 137                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 138                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 139                         resets = <&tegra_car 23>;
 140                         reset-names = "isp";
 141                 };
 142
 143                 gr2d@54140000 {
 144                         compatible = "nvidia,tegra30-gr2d";
 145                         reg = <0x54140000 0x00040000>;
 146                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 147                         resets = <&tegra_car 21>;
 148                         reset-names = "2d";
 149                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 150                 };
 151
 152                 gr3d@54180000 {
 153                         compatible = "nvidia,tegra30-gr3d";
 154                         reg = <0x54180000 0x00040000>;
 155                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 156                                   &tegra_car TEGRA30_CLK_GR3D2>;
 157                         clock-names = "3d", "3d2";
 158                         resets = <&tegra_car 24>,
 159                                  <&tegra_car 98>;
 160                         reset-names = "3d", "3d2";
 161                 };
 162
 163                 dc@54200000 {
 164                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 165                         reg = <0x54200000 0x00040000>;
 166                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 167                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 168                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 169                         clock-names = "dc", "parent";
 170                         resets = <&tegra_car 27>;
 171                         reset-names = "dc";
 172
 173                         nvidia,head = <0>;
 174
 175                         rgb {
 176                                 status = "disabled";
 177                         };
 178                 };
 179
 180                 dc@54240000 {
 181                         compatible = "nvidia,tegra30-dc";
 182                         reg = <0x54240000 0x00040000>;
 183                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 184                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 185                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 186                         clock-names = "dc", "parent";
 187                         resets = <&tegra_car 26>;
 188                         reset-names = "dc";
 189
 190                         nvidia,head = <1>;
 191
 192                         rgb {
 193                                 status = "disabled";
 194                         };
 195                 };
 196
 197                 hdmi@54280000 {
 198                         compatible = "nvidia,tegra30-hdmi";
 199                         reg = <0x54280000 0x00040000>;
 200                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 202                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 203                         clock-names = "hdmi", "parent";
 204                         resets = <&tegra_car 51>;
 205                         reset-names = "hdmi";
 206                         status = "disabled";
 207                 };
 208
 209                 tvo@542c0000 {
 210                         compatible = "nvidia,tegra30-tvo";
 211                         reg = <0x542c0000 0x00040000>;
 212                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 213                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 214                         status = "disabled";
 215                 };
 216
 217                 dsi@54300000 {
 218                         compatible = "nvidia,tegra30-dsi";
 219                         reg = <0x54300000 0x00040000>;
 220                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 221                         resets = <&tegra_car 48>;
 222                         reset-names = "dsi";
 223                         status = "disabled";
 224                 };
 225         };
 226
 227         timer@50004600 {
 228                 compatible = "arm,cortex-a9-twd-timer";
 229                 reg = <0x50040600 0x20>;
 230                 interrupts = <GIC_PPI 13
 231                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 232                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 233         };
 234
 235         intc: interrupt-controller@50041000 {
 236                 compatible = "arm,cortex-a9-gic";
 237                 reg = <0x50041000 0x1000
 238                        0x50040100 0x0100>;
 239                 interrupt-controller;
 240                 #interrupt-cells = <3>;
 241         };
 242
 243         cache-controller@50043000 {
 244                 compatible = "arm,pl310-cache";
 245                 reg = <0x50043000 0x1000>;
 246                 arm,data-latency = <6 6 2>;
 247                 arm,tag-latency = <5 5 2>;
 248                 cache-unified;
 249                 cache-level = <2>;
 250         };
 251
 252         timer@60005000 {
 253                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 254                 reg = <0x60005000 0x400>;
 255                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 262         };
 263
 264         tegra_car: clock@60006000 {
 265                 compatible = "nvidia,tegra30-car";
 266                 reg = <0x60006000 0x1000>;
 267                 #clock-cells = <1>;
 268                 #reset-cells = <1>;
 269         };
 270
 271         apbdma: dma@6000a000 {
 272                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 273                 reg = <0x6000a000 0x1400>;
 274                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 275                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 276                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 280                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 281                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 282                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 283                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 284                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 285                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 296                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 298                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 302                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 305                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 307                 resets = <&tegra_car 34>;
 308                 reset-names = "dma";
 309                 #dma-cells = <1>;
 310         };
 311
 312         ahb: ahb@6000c004 {
 313                 compatible = "nvidia,tegra30-ahb";
 314                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 315         };
 316
 317         gpio: gpio@6000d000 {
 318                 compatible = "nvidia,tegra30-gpio";
 319                 reg = <0x6000d000 0x1000>;
 320                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 321                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 322                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 323                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 324                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 325                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 326                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 328                 #gpio-cells = <2>;
 329                 gpio-controller;
 330                 #interrupt-cells = <2>;
 331                 interrupt-controller;
 332         };
 333
 334         pinmux: pinmux@70000868 {
 335                 compatible = "nvidia,tegra30-pinmux";
 336                 reg = <0x70000868 0xd4    /* Pad control registers */
 337                        0x70003000 0x3e4>; /* Mux registers */
 338         };
 339
 340         /*
 341          * There are two serial driver i.e. 8250 based simple serial
 342          * driver and APB DMA based serial driver for higher baudrate
 343          * and performace. To enable the 8250 based driver, the compatible
 344          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 345          * the APB DMA based serial driver, the comptible is
 346          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 347          */
 348         uarta: serial@70006000 {
 349                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 350                 reg = <0x70006000 0x40>;
 351                 reg-shift = <2>;
 352                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 354                 resets = <&tegra_car 6>;
 355                 reset-names = "serial";
 356                 dmas = <&apbdma 8>, <&apbdma 8>;
 357                 dma-names = "rx", "tx";
 358                 status = "disabled";
 359         };
 360
 361         uartb: serial@70006040 {
 362                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 363                 reg = <0x70006040 0x40>;
 364                 reg-shift = <2>;
 365                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 366                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 367                 resets = <&tegra_car 7>;
 368                 reset-names = "serial";
 369                 dmas = <&apbdma 9>, <&apbdma 9>;
 370                 dma-names = "rx", "tx";
 371                 status = "disabled";
 372         };
 373
 374         uartc: serial@70006200 {
 375                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 376                 reg = <0x70006200 0x100>;
 377                 reg-shift = <2>;
 378                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 379                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 380                 resets = <&tegra_car 55>;
 381                 reset-names = "serial";
 382                 dmas = <&apbdma 10>, <&apbdma 10>;
 383                 dma-names = "rx", "tx";
 384                 status = "disabled";
 385         };
 386
 387         uartd: serial@70006300 {
 388                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 389                 reg = <0x70006300 0x100>;
 390                 reg-shift = <2>;
 391                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 393                 resets = <&tegra_car 65>;
 394                 reset-names = "serial";
 395                 dmas = <&apbdma 19>, <&apbdma 19>;
 396                 dma-names = "rx", "tx";
 397                 status = "disabled";
 398         };
 399
 400         uarte: serial@70006400 {
 401                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 402                 reg = <0x70006400 0x100>;
 403                 reg-shift = <2>;
 404                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 405                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 406                 resets = <&tegra_car 66>;
 407                 reset-names = "serial";
 408                 dmas = <&apbdma 20>, <&apbdma 20>;
 409                 dma-names = "rx", "tx";
 410                 status = "disabled";
 411         };
 412
 413         pwm: pwm@7000a000 {
 414                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 415                 reg = <0x7000a000 0x100>;
 416                 #pwm-cells = <2>;
 417                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 418                 resets = <&tegra_car 17>;
 419                 reset-names = "pwm";
 420                 status = "disabled";
 421         };
 422
 423         rtc@7000e000 {
 424                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 425                 reg = <0x7000e000 0x100>;
 426                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 427                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 428         };
 429
 430         i2c@7000c000 {
 431                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 432                 reg = <0x7000c000 0x100>;
 433                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 437                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 438                 clock-names = "div-clk", "fast-clk";
 439                 resets = <&tegra_car 12>;
 440                 reset-names = "i2c";
 441                 dmas = <&apbdma 21>, <&apbdma 21>;
 442                 dma-names = "rx", "tx";
 443                 status = "disabled";
 444         };
 445
 446         i2c@7000c400 {
 447                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 448                 reg = <0x7000c400 0x100>;
 449                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 453                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 454                 clock-names = "div-clk", "fast-clk";
 455                 resets = <&tegra_car 54>;
 456                 reset-names = "i2c";
 457                 dmas = <&apbdma 22>, <&apbdma 22>;
 458                 dma-names = "rx", "tx";
 459                 status = "disabled";
 460         };
 461
 462         i2c@7000c500 {
 463                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 464                 reg = <0x7000c500 0x100>;
 465                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 469                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 470                 clock-names = "div-clk", "fast-clk";
 471                 resets = <&tegra_car 67>;
 472                 reset-names = "i2c";
 473                 dmas = <&apbdma 23>, <&apbdma 23>;
 474                 dma-names = "rx", "tx";
 475                 status = "disabled";
 476         };
 477
 478         i2c@7000c700 {
 479                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 480                 reg = <0x7000c700 0x100>;
 481                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 482                 #address-cells = <1>;
 483                 #size-cells = <0>;
 484                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 485                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 486                 resets = <&tegra_car 103>;
 487                 reset-names = "i2c";
 488                 clock-names = "div-clk", "fast-clk";
 489                 dmas = <&apbdma 26>, <&apbdma 26>;
 490                 dma-names = "rx", "tx";
 491                 status = "disabled";
 492         };
 493
 494         i2c@7000d000 {
 495                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 496                 reg = <0x7000d000 0x100>;
 497                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 498                 #address-cells = <1>;
 499                 #size-cells = <0>;
 500                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 501                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 502                 clock-names = "div-clk", "fast-clk";
 503                 resets = <&tegra_car 47>;
 504                 reset-names = "i2c";
 505                 dmas = <&apbdma 24>, <&apbdma 24>;
 506                 dma-names = "rx", "tx";
 507                 status = "disabled";
 508         };
 509
 510         spi@7000d400 {
 511                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 512                 reg = <0x7000d400 0x200>;
 513                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 514                 #address-cells = <1>;
 515                 #size-cells = <0>;
 516                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 517                 resets = <&tegra_car 41>;
 518                 reset-names = "spi";
 519                 dmas = <&apbdma 15>, <&apbdma 15>;
 520                 dma-names = "rx", "tx";
 521                 status = "disabled";
 522         };
 523
 524         spi@7000d600 {
 525                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 526                 reg = <0x7000d600 0x200>;
 527                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 528                 #address-cells = <1>;
 529                 #size-cells = <0>;
 530                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 531                 resets = <&tegra_car 44>;
 532                 reset-names = "spi";
 533                 dmas = <&apbdma 16>, <&apbdma 16>;
 534                 dma-names = "rx", "tx";
 535                 status = "disabled";
 536         };
 537
 538         spi@7000d800 {
 539                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 540                 reg = <0x7000d800 0x200>;
 541                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 545                 resets = <&tegra_car 46>;
 546                 reset-names = "spi";
 547                 dmas = <&apbdma 17>, <&apbdma 17>;
 548                 dma-names = "rx", "tx";
 549                 status = "disabled";
 550         };
 551
 552         spi@7000da00 {
 553                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 554                 reg = <0x7000da00 0x200>;
 555                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 559                 resets = <&tegra_car 68>;
 560                 reset-names = "spi";
 561                 dmas = <&apbdma 18>, <&apbdma 18>;
 562                 dma-names = "rx", "tx";
 563                 status = "disabled";
 564         };
 565
 566         spi@7000dc00 {
 567                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 568                 reg = <0x7000dc00 0x200>;
 569                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 573                 resets = <&tegra_car 104>;
 574                 reset-names = "spi";
 575                 dmas = <&apbdma 27>, <&apbdma 27>;
 576                 dma-names = "rx", "tx";
 577                 status = "disabled";
 578         };
 579
 580         spi@7000de00 {
 581                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 582                 reg = <0x7000de00 0x200>;
 583                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 584                 #address-cells = <1>;
 585                 #size-cells = <0>;
 586                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 587                 resets = <&tegra_car 106>;
 588                 reset-names = "spi";
 589                 dmas = <&apbdma 28>, <&apbdma 28>;
 590                 dma-names = "rx", "tx";
 591                 status = "disabled";
 592         };
 593
 594         kbc@7000e200 {
 595                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 596                 reg = <0x7000e200 0x100>;
 597                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 598                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 599                 resets = <&tegra_car 36>;
 600                 reset-names = "kbc";
 601                 status = "disabled";
 602         };
 603
 604         pmc@7000e400 {
 605                 compatible = "nvidia,tegra30-pmc";
 606                 reg = <0x7000e400 0x400>;
 607                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 608                 clock-names = "pclk", "clk32k_in";
 609         };
 610
 611         memory-controller@7000f000 {
 612                 compatible = "nvidia,tegra30-mc";
 613                 reg = <0x7000f000 0x010
 614                        0x7000f03c 0x1b4
 615                        0x7000f200 0x028
 616                        0x7000f284 0x17c>;
 617                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 618         };
 619
 620         iommu@7000f010 {
 621                 compatible = "nvidia,tegra30-smmu";
 622                 reg = <0x7000f010 0x02c
 623                        0x7000f1f0 0x010
 624                        0x7000f228 0x05c>;
 625                 nvidia,#asids = <4>;            /* # of ASIDs */
 626                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 627                 nvidia,ahb = <&ahb>;
 628         };
 629
 630         ahub@70080000 {
 631                 compatible = "nvidia,tegra30-ahub";
 632                 reg = <0x70080000 0x200
 633                        0x70080200 0x100>;
 634                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 636                          <&tegra_car TEGRA30_CLK_APBIF>;
 637                 clock-names = "d_audio", "apbif";
 638                 resets = <&tegra_car 106>, /* d_audio */
 639                          <&tegra_car 107>, /* apbif */
 640                          <&tegra_car 30>,  /* i2s0 */
 641                          <&tegra_car 11>,  /* i2s1 */
 642                          <&tegra_car 18>,  /* i2s2 */
 643                          <&tegra_car 101>, /* i2s3 */
 644                          <&tegra_car 102>, /* i2s4 */
 645                          <&tegra_car 108>, /* dam0 */
 646                          <&tegra_car 109>, /* dam1 */
 647                          <&tegra_car 110>, /* dam2 */
 648                          <&tegra_car 10>;  /* spdif */
 649                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 650                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 651                               "spdif";
 652                 dmas = <&apbdma 1>, <&apbdma 1>,
 653                        <&apbdma 2>, <&apbdma 2>,
 654                        <&apbdma 3>, <&apbdma 3>,
 655                        <&apbdma 4>, <&apbdma 4>;
 656                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 657                             "rx3", "tx3";
 658                 ranges;
 659                 #address-cells = <1>;
 660                 #size-cells = <1>;
 661
 662                 tegra_i2s0: i2s@70080300 {
 663                         compatible = "nvidia,tegra30-i2s";
 664                         reg = <0x70080300 0x100>;
 665                         nvidia,ahub-cif-ids = <4 4>;
 666                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 667                         resets = <&tegra_car 30>;
 668                         reset-names = "i2s";
 669                         status = "disabled";
 670                 };
 671
 672                 tegra_i2s1: i2s@70080400 {
 673                         compatible = "nvidia,tegra30-i2s";
 674                         reg = <0x70080400 0x100>;
 675                         nvidia,ahub-cif-ids = <5 5>;
 676                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 677                         resets = <&tegra_car 11>;
 678                         reset-names = "i2s";
 679                         status = "disabled";
 680                 };
 681
 682                 tegra_i2s2: i2s@70080500 {
 683                         compatible = "nvidia,tegra30-i2s";
 684                         reg = <0x70080500 0x100>;
 685                         nvidia,ahub-cif-ids = <6 6>;
 686                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 687                         resets = <&tegra_car 18>;
 688                         reset-names = "i2s";
 689                         status = "disabled";
 690                 };
 691
 692                 tegra_i2s3: i2s@70080600 {
 693                         compatible = "nvidia,tegra30-i2s";
 694                         reg = <0x70080600 0x100>;
 695                         nvidia,ahub-cif-ids = <7 7>;
 696                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 697                         resets = <&tegra_car 101>;
 698                         reset-names = "i2s";
 699                         status = "disabled";
 700                 };
 701
 702                 tegra_i2s4: i2s@70080700 {
 703                         compatible = "nvidia,tegra30-i2s";
 704                         reg = <0x70080700 0x100>;
 705                         nvidia,ahub-cif-ids = <8 8>;
 706                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 707                         resets = <&tegra_car 102>;
 708                         reset-names = "i2s";
 709                         status = "disabled";
 710                 };
 711         };
 712
 713         sdhci@78000000 {
 714                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 715                 reg = <0x78000000 0x200>;
 716                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 717                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 718                 resets = <&tegra_car 14>;
 719                 reset-names = "sdhci";
 720                 status = "disabled";
 721         };
 722
 723         sdhci@78000200 {
 724                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 725                 reg = <0x78000200 0x200>;
 726                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 727                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 728                 resets = <&tegra_car 9>;
 729                 reset-names = "sdhci";
 730                 status = "disabled";
 731         };
 732
 733         sdhci@78000400 {
 734                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 735                 reg = <0x78000400 0x200>;
 736                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 737                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 738                 resets = <&tegra_car 69>;
 739                 reset-names = "sdhci";
 740                 status = "disabled";
 741         };
 742
 743         sdhci@78000600 {
 744                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 745                 reg = <0x78000600 0x200>;
 746                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 747                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 748                 resets = <&tegra_car 15>;
 749                 reset-names = "sdhci";
 750                 status = "disabled";
 751         };
 752
 753         usb@7d000000 {
 754                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 755                 reg = <0x7d000000 0x4000>;
 756                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 757                 phy_type = "utmi";
 758                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 759                 resets = <&tegra_car 22>;
 760                 reset-names = "usb";
 761                 nvidia,needs-double-reset;
 762                 nvidia,phy = <&phy1>;
 763                 status = "disabled";
 764         };
 765
 766         phy1: usb-phy@7d000000 {
 767                 compatible = "nvidia,tegra30-usb-phy";
 768                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 769                 phy_type = "utmi";
 770                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 771                          <&tegra_car TEGRA30_CLK_PLL_U>,
 772                          <&tegra_car TEGRA30_CLK_USBD>;
 773                 clock-names = "reg", "pll_u", "utmi-pads";
 774                 nvidia,hssync-start-delay = <9>;
 775                 nvidia,idle-wait-delay = <17>;
 776                 nvidia,elastic-limit = <16>;
 777                 nvidia,term-range-adj = <6>;
 778                 nvidia,xcvr-setup = <51>;
 779                 nvidia.xcvr-setup-use-fuses;
 780                 nvidia,xcvr-lsfslew = <1>;
 781                 nvidia,xcvr-lsrslew = <1>;
 782                 nvidia,xcvr-hsslew = <32>;
 783                 nvidia,hssquelch-level = <2>;
 784                 nvidia,hsdiscon-level = <5>;
 785                 status = "disabled";
 786         };
 787
 788         usb@7d004000 {
 789                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 790                 reg = <0x7d004000 0x4000>;
 791                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 792                 phy_type = "utmi";
 793                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 794                 resets = <&tegra_car 58>;
 795                 reset-names = "usb";
 796                 nvidia,phy = <&phy2>;
 797                 status = "disabled";
 798         };
 799
 800         phy2: usb-phy@7d004000 {
 801                 compatible = "nvidia,tegra30-usb-phy";
 802                 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
 803                 phy_type = "utmi";
 804                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 805                          <&tegra_car TEGRA30_CLK_PLL_U>,
 806                          <&tegra_car TEGRA30_CLK_USBD>;
 807                 clock-names = "reg", "pll_u", "utmi-pads";
 808                 nvidia,hssync-start-delay = <9>;
 809                 nvidia,idle-wait-delay = <17>;
 810                 nvidia,elastic-limit = <16>;
 811                 nvidia,term-range-adj = <6>;
 812                 nvidia,xcvr-setup = <51>;
 813                 nvidia.xcvr-setup-use-fuses;
 814                 nvidia,xcvr-lsfslew = <2>;
 815                 nvidia,xcvr-lsrslew = <2>;
 816                 nvidia,xcvr-hsslew = <32>;
 817                 nvidia,hssquelch-level = <2>;
 818                 nvidia,hsdiscon-level = <5>;
 819                 status = "disabled";
 820         };
 821
 822         usb@7d008000 {
 823                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 824                 reg = <0x7d008000 0x4000>;
 825                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 826                 phy_type = "utmi";
 827                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 828                 resets = <&tegra_car 59>;
 829                 reset-names = "usb";
 830                 nvidia,phy = <&phy3>;
 831                 status = "disabled";
 832         };
 833
 834         phy3: usb-phy@7d008000 {
 835                 compatible = "nvidia,tegra30-usb-phy";
 836                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 837                 phy_type = "utmi";
 838                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 839                          <&tegra_car TEGRA30_CLK_PLL_U>,
 840                          <&tegra_car TEGRA30_CLK_USBD>;
 841                 clock-names = "reg", "pll_u", "utmi-pads";
 842                 nvidia,hssync-start-delay = <0>;
 843                 nvidia,idle-wait-delay = <17>;
 844                 nvidia,elastic-limit = <16>;
 845                 nvidia,term-range-adj = <6>;
 846                 nvidia,xcvr-setup = <51>;
 847                 nvidia.xcvr-setup-use-fuses;
 848                 nvidia,xcvr-lsfslew = <2>;
 849                 nvidia,xcvr-lsrslew = <2>;
 850                 nvidia,xcvr-hsslew = <32>;
 851                 nvidia,hssquelch-level = <2>;
 852                 nvidia,hsdiscon-level = <5>;
 853                 status = "disabled";
 854         };
 855
 856         cpus {
 857                 #address-cells = <1>;
 858                 #size-cells = <0>;
 859
 860                 cpu@0 {
 861                         device_type = "cpu";
 862                         compatible = "arm,cortex-a9";
 863                         reg = <0>;
 864                 };
 865
 866                 cpu@1 {
 867                         device_type = "cpu";
 868                         compatible = "arm,cortex-a9";
 869                         reg = <1>;
 870                 };
 871
 872                 cpu@2 {
 873                         device_type = "cpu";
 874                         compatible = "arm,cortex-a9";
 875                         reg = <2>;
 876                 };
 877
 878                 cpu@3 {
 879                         device_type = "cpu";
 880                         compatible = "arm,cortex-a9";
 881                         reg = <3>;
 882                 };
 883         };
 884
 885         pmu {
 886                 compatible = "arm,cortex-a9-pmu";
 887                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 888                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 889                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 890                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 891         };
 892 };