2 * PCI-E support for CNS3xxx
4 * Copyright 2008 Cavium Networks
5 * Richard Liu <richard.liu@caviumnetworks.com>
6 * Copyright 2010 MontaVista Software, LLC.
7 * Anton Vorontsov <avorontsov@mvista.com>
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/bug.h>
17 #include <linux/pci.h>
19 #include <linux/ioport.h>
20 #include <linux/interrupt.h>
21 #include <linux/ptrace.h>
22 #include <asm/mach/map.h>
26 enum cns3xxx_access_type {
27 CNS3XXX_HOST_TYPE = 0,
30 CNS3XXX_NUM_ACCESS_TYPES,
34 struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
36 struct resource res_io;
37 struct resource res_mem;
43 static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
45 static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
47 struct pci_sys_data *root = sysdata;
49 return &cns3xxx_pcie[root->domain];
52 static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
54 return sysdata_to_cnspci(dev->sysdata);
57 static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
59 return sysdata_to_cnspci(bus->sysdata);
62 static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
63 unsigned int devfn, int where)
65 struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
66 int busno = bus->number;
67 int slot = PCI_SLOT(devfn);
69 enum cns3xxx_access_type type;
72 /* If there is no link, just show the CNS PCI bridge. */
73 if (!cnspci->linked && (busno > 0 || slot > 0))
77 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
78 * we still want to access it. For this to work, we must place
79 * the first device on the same bus as the CNS PCI bridge.
86 type = CNS3XXX_CFG1_TYPE;
89 base = (void __iomem *)cnspci->cfg_bases[type].virtual;
90 offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
95 static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
96 int where, int size, u32 *val)
100 u32 mask = (0x1ull << (size * 8)) - 1;
101 int shift = (where % 4) * 8;
103 base = cns3xxx_pci_cfg_base(bus, devfn, where);
106 return PCIBIOS_SUCCESSFUL;
109 v = __raw_readl(base);
111 if (bus->number == 0 && devfn == 0 &&
112 (where & 0xffc) == PCI_CLASS_REVISION) {
114 * RC's class is 0xb, but Linux PCI driver needs 0x604
115 * for a PCIe bridge. So we must fixup the class code
122 *val = (v >> shift) & mask;
124 return PCIBIOS_SUCCESSFUL;
127 static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
128 int where, int size, u32 val)
132 u32 mask = (0x1ull << (size * 8)) - 1;
133 int shift = (where % 4) * 8;
135 base = cns3xxx_pci_cfg_base(bus, devfn, where);
137 return PCIBIOS_SUCCESSFUL;
139 v = __raw_readl(base);
141 v &= ~(mask << shift);
142 v |= (val & mask) << shift;
144 __raw_writel(v, base);
146 return PCIBIOS_SUCCESSFUL;
149 static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
151 struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
152 struct resource *res_io = &cnspci->res_io;
153 struct resource *res_mem = &cnspci->res_mem;
155 BUG_ON(request_resource(&iomem_resource, res_io) ||
156 request_resource(&iomem_resource, res_mem));
158 pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
159 pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
164 static struct pci_ops cns3xxx_pcie_ops = {
165 .read = cns3xxx_pci_read_config,
166 .write = cns3xxx_pci_write_config,
169 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
171 struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
172 int irq = cnspci->irqs[slot];
174 pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
175 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
176 PCI_FUNC(dev->devfn), slot, pin, irq);
181 static struct cns3xxx_pcie cns3xxx_pcie[] = {
184 [CNS3XXX_HOST_TYPE] = {
185 .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
186 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
190 [CNS3XXX_CFG0_TYPE] = {
191 .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
192 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
196 [CNS3XXX_CFG1_TYPE] = {
197 .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
198 .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
204 .name = "PCIe0 I/O space",
205 .start = CNS3XXX_PCIE0_IO_BASE,
206 .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
207 .flags = IORESOURCE_IO,
210 .name = "PCIe0 non-prefetchable",
211 .start = CNS3XXX_PCIE0_MEM_BASE,
212 .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
213 .flags = IORESOURCE_MEM,
215 .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
219 .ops = &cns3xxx_pcie_ops,
220 .setup = cns3xxx_pci_setup,
221 .map_irq = cns3xxx_pcie_map_irq,
226 [CNS3XXX_HOST_TYPE] = {
227 .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
228 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
232 [CNS3XXX_CFG0_TYPE] = {
233 .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
234 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
238 [CNS3XXX_CFG1_TYPE] = {
239 .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
240 .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
246 .name = "PCIe1 I/O space",
247 .start = CNS3XXX_PCIE1_IO_BASE,
248 .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
249 .flags = IORESOURCE_IO,
252 .name = "PCIe1 non-prefetchable",
253 .start = CNS3XXX_PCIE1_MEM_BASE,
254 .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
255 .flags = IORESOURCE_MEM,
257 .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
261 .ops = &cns3xxx_pcie_ops,
262 .setup = cns3xxx_pci_setup,
263 .map_irq = cns3xxx_pcie_map_irq,
268 static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
270 int port = cnspci->hw_pci.domain;
274 reg = __raw_readl(MISC_PCIE_CTRL(port));
276 * Enable Application Request to 1, it will exit L1 automatically,
277 * but when chip back, it will use another clock, still can use 0x1.
280 __raw_writel(reg, MISC_PCIE_CTRL(port));
282 pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
283 pr_info("PCIe: Port[%d] Check data link layer...", port);
287 reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
289 pr_info("Link up.\n");
292 } else if (time_after(jiffies, time + 50)) {
293 pr_info("Device not found.\n");
299 static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
301 int port = cnspci->hw_pci.domain;
302 struct pci_sys_data sd = {
305 struct pci_bus bus = {
307 .ops = &cns3xxx_pcie_ops,
310 u32 io_base = cnspci->res_io.start >> 16;
311 u32 mem_base = cnspci->res_mem.start >> 16;
312 u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
313 u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
319 host_base = (__pfn_to_phys(host_base) - 1) >> 16;
320 cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
322 pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
323 pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
324 pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
326 pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
327 pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
328 pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
330 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
331 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
332 pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
333 pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
338 /* Set Device Max_Read_Request_Size to 128 byte */
339 devfn = PCI_DEVFN(1, 0);
340 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
341 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
342 dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
343 pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
344 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
345 if (!(dc & (0x3 << 12)))
346 pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
348 /* Disable PCIe0 Interrupt Mask INTA to INTD */
349 __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
352 static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
353 struct pt_regs *regs)
360 static int __init cns3xxx_pcie_init(void)
367 hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
368 "imprecise external abort");
370 for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
371 iotable_init(cns3xxx_pcie[i].cfg_bases,
372 ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
373 cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
374 cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
375 cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
376 cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
377 pci_common_init(&cns3xxx_pcie[i].hw_pci);
380 pci_assign_unassigned_resources();
384 device_initcall(cns3xxx_pcie_init);