2 * TI DaVinci DM365 chip specific setup
4 * Copyright (C) 2009 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/serial_8250.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/gpio.h>
23 #include <asm/mach/map.h>
25 #include <mach/dm365.h>
26 #include <mach/clock.h>
27 #include <mach/cputype.h>
28 #include <mach/edma.h>
31 #include <mach/irqs.h>
32 #include <mach/time.h>
33 #include <mach/serial.h>
34 #include <mach/common.h>
39 #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
41 static struct pll_data pll1_data = {
43 .phys_base = DAVINCI_PLL1_BASE,
44 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
47 static struct pll_data pll2_data = {
49 .phys_base = DAVINCI_PLL2_BASE,
50 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
53 static struct clk ref_clk = {
55 .rate = DM365_REF_FREQ,
58 static struct clk pll1_clk = {
62 .pll_data = &pll1_data,
65 static struct clk pll1_aux_clk = {
66 .name = "pll1_aux_clk",
68 .flags = CLK_PLL | PRE_PLL,
71 static struct clk pll1_sysclkbp = {
72 .name = "pll1_sysclkbp",
74 .flags = CLK_PLL | PRE_PLL,
78 static struct clk clkout0_clk = {
81 .flags = CLK_PLL | PRE_PLL,
84 static struct clk pll1_sysclk1 = {
85 .name = "pll1_sysclk1",
91 static struct clk pll1_sysclk2 = {
92 .name = "pll1_sysclk2",
98 static struct clk pll1_sysclk3 = {
99 .name = "pll1_sysclk3",
105 static struct clk pll1_sysclk4 = {
106 .name = "pll1_sysclk4",
112 static struct clk pll1_sysclk5 = {
113 .name = "pll1_sysclk5",
119 static struct clk pll1_sysclk6 = {
120 .name = "pll1_sysclk6",
126 static struct clk pll1_sysclk7 = {
127 .name = "pll1_sysclk7",
133 static struct clk pll1_sysclk8 = {
134 .name = "pll1_sysclk8",
140 static struct clk pll1_sysclk9 = {
141 .name = "pll1_sysclk9",
147 static struct clk pll2_clk = {
151 .pll_data = &pll2_data,
154 static struct clk pll2_aux_clk = {
155 .name = "pll2_aux_clk",
157 .flags = CLK_PLL | PRE_PLL,
160 static struct clk clkout1_clk = {
163 .flags = CLK_PLL | PRE_PLL,
166 static struct clk pll2_sysclk1 = {
167 .name = "pll2_sysclk1",
173 static struct clk pll2_sysclk2 = {
174 .name = "pll2_sysclk2",
180 static struct clk pll2_sysclk3 = {
181 .name = "pll2_sysclk3",
187 static struct clk pll2_sysclk4 = {
188 .name = "pll2_sysclk4",
194 static struct clk pll2_sysclk5 = {
195 .name = "pll2_sysclk5",
201 static struct clk pll2_sysclk6 = {
202 .name = "pll2_sysclk6",
208 static struct clk pll2_sysclk7 = {
209 .name = "pll2_sysclk7",
215 static struct clk pll2_sysclk8 = {
216 .name = "pll2_sysclk8",
222 static struct clk pll2_sysclk9 = {
223 .name = "pll2_sysclk9",
229 static struct clk vpss_dac_clk = {
231 .parent = &pll1_sysclk3,
232 .lpsc = DM365_LPSC_DAC_CLK,
235 static struct clk vpss_master_clk = {
236 .name = "vpss_master",
237 .parent = &pll1_sysclk5,
238 .lpsc = DM365_LPSC_VPSSMSTR,
242 static struct clk arm_clk = {
244 .parent = &pll2_sysclk2,
245 .lpsc = DAVINCI_LPSC_ARM,
246 .flags = ALWAYS_ENABLED,
249 static struct clk uart0_clk = {
251 .parent = &pll1_aux_clk,
252 .lpsc = DAVINCI_LPSC_UART0,
255 static struct clk uart1_clk = {
257 .parent = &pll1_sysclk4,
258 .lpsc = DAVINCI_LPSC_UART1,
261 static struct clk i2c_clk = {
263 .parent = &pll1_aux_clk,
264 .lpsc = DAVINCI_LPSC_I2C,
267 static struct clk mmcsd0_clk = {
269 .parent = &pll1_sysclk8,
270 .lpsc = DAVINCI_LPSC_MMC_SD,
273 static struct clk mmcsd1_clk = {
275 .parent = &pll1_sysclk4,
276 .lpsc = DM365_LPSC_MMC_SD1,
279 static struct clk spi0_clk = {
281 .parent = &pll1_sysclk4,
282 .lpsc = DAVINCI_LPSC_SPI,
285 static struct clk spi1_clk = {
287 .parent = &pll1_sysclk4,
288 .lpsc = DM365_LPSC_SPI1,
291 static struct clk spi2_clk = {
293 .parent = &pll1_sysclk4,
294 .lpsc = DM365_LPSC_SPI2,
297 static struct clk spi3_clk = {
299 .parent = &pll1_sysclk4,
300 .lpsc = DM365_LPSC_SPI3,
303 static struct clk spi4_clk = {
305 .parent = &pll1_aux_clk,
306 .lpsc = DM365_LPSC_SPI4,
309 static struct clk gpio_clk = {
311 .parent = &pll1_sysclk4,
312 .lpsc = DAVINCI_LPSC_GPIO,
315 static struct clk aemif_clk = {
317 .parent = &pll1_sysclk4,
318 .lpsc = DAVINCI_LPSC_AEMIF,
321 static struct clk pwm0_clk = {
323 .parent = &pll1_aux_clk,
324 .lpsc = DAVINCI_LPSC_PWM0,
327 static struct clk pwm1_clk = {
329 .parent = &pll1_aux_clk,
330 .lpsc = DAVINCI_LPSC_PWM1,
333 static struct clk pwm2_clk = {
335 .parent = &pll1_aux_clk,
336 .lpsc = DAVINCI_LPSC_PWM2,
339 static struct clk pwm3_clk = {
342 .lpsc = DM365_LPSC_PWM3,
345 static struct clk timer0_clk = {
347 .parent = &pll1_aux_clk,
348 .lpsc = DAVINCI_LPSC_TIMER0,
351 static struct clk timer1_clk = {
353 .parent = &pll1_aux_clk,
354 .lpsc = DAVINCI_LPSC_TIMER1,
357 static struct clk timer2_clk = {
359 .parent = &pll1_aux_clk,
360 .lpsc = DAVINCI_LPSC_TIMER2,
364 static struct clk timer3_clk = {
366 .parent = &pll1_aux_clk,
367 .lpsc = DM365_LPSC_TIMER3,
370 static struct clk usb_clk = {
372 .parent = &pll2_sysclk1,
373 .lpsc = DAVINCI_LPSC_USB,
376 static struct clk emac_clk = {
378 .parent = &pll1_sysclk4,
379 .lpsc = DM365_LPSC_EMAC,
382 static struct clk voicecodec_clk = {
383 .name = "voice_codec",
384 .parent = &pll2_sysclk4,
385 .lpsc = DM365_LPSC_VOICE_CODEC,
388 static struct clk asp0_clk = {
390 .parent = &pll1_sysclk4,
391 .lpsc = DM365_LPSC_McBSP1,
394 static struct clk rto_clk = {
396 .parent = &pll1_sysclk4,
397 .lpsc = DM365_LPSC_RTO,
400 static struct clk mjcp_clk = {
402 .parent = &pll1_sysclk3,
403 .lpsc = DM365_LPSC_MJCP,
406 static struct davinci_clk dm365_clks[] = {
407 CLK(NULL, "ref", &ref_clk),
408 CLK(NULL, "pll1", &pll1_clk),
409 CLK(NULL, "pll1_aux", &pll1_aux_clk),
410 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
411 CLK(NULL, "clkout0", &clkout0_clk),
412 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
413 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
414 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
415 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
416 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
417 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
418 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
419 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
420 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
421 CLK(NULL, "pll2", &pll2_clk),
422 CLK(NULL, "pll2_aux", &pll2_aux_clk),
423 CLK(NULL, "clkout1", &clkout1_clk),
424 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
425 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
426 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
427 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
428 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
429 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
430 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
431 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
432 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
433 CLK(NULL, "vpss_dac", &vpss_dac_clk),
434 CLK(NULL, "vpss_master", &vpss_master_clk),
435 CLK(NULL, "arm", &arm_clk),
436 CLK(NULL, "uart0", &uart0_clk),
437 CLK(NULL, "uart1", &uart1_clk),
438 CLK("i2c_davinci.1", NULL, &i2c_clk),
439 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
440 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
441 CLK("spi_davinci.0", NULL, &spi0_clk),
442 CLK("spi_davinci.1", NULL, &spi1_clk),
443 CLK("spi_davinci.2", NULL, &spi2_clk),
444 CLK("spi_davinci.3", NULL, &spi3_clk),
445 CLK("spi_davinci.4", NULL, &spi4_clk),
446 CLK(NULL, "gpio", &gpio_clk),
447 CLK(NULL, "aemif", &aemif_clk),
448 CLK(NULL, "pwm0", &pwm0_clk),
449 CLK(NULL, "pwm1", &pwm1_clk),
450 CLK(NULL, "pwm2", &pwm2_clk),
451 CLK(NULL, "pwm3", &pwm3_clk),
452 CLK(NULL, "timer0", &timer0_clk),
453 CLK(NULL, "timer1", &timer1_clk),
454 CLK("watchdog", NULL, &timer2_clk),
455 CLK(NULL, "timer3", &timer3_clk),
456 CLK(NULL, "usb", &usb_clk),
457 CLK("davinci_emac.1", NULL, &emac_clk),
458 CLK("voice_codec", NULL, &voicecodec_clk),
459 CLK("soc-audio.0", NULL, &asp0_clk),
460 CLK(NULL, "rto", &rto_clk),
461 CLK(NULL, "mjcp", &mjcp_clk),
462 CLK(NULL, NULL, NULL),
465 /*----------------------------------------------------------------------*/
476 static const struct mux_config dm365_pins[] = {
477 #ifdef CONFIG_DAVINCI_MUX
478 MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
480 MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
481 MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
482 MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
483 MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
484 MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
485 MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
487 MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
488 MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
490 MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false)
491 MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
492 MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
493 MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
494 MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
496 MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
497 MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
498 MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
499 MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
500 MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
501 MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
503 MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
504 MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
505 MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
506 MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
507 MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
509 MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
510 MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
511 MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
512 MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
513 MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
514 MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
516 MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
517 MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
518 MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
519 MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
520 MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
521 MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
522 MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
523 MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
524 MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
525 MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
526 MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
527 MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
528 MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
529 MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
530 MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
531 MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
532 MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
534 MUX_CFG(DM365, KEYPAD, 2, 0, 0x3f, 0x3f, false)
536 MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
537 MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
538 MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
539 MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
540 MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
541 MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
542 MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
543 MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
544 MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
545 MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
546 MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
547 MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
549 MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
550 MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
551 MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
552 MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
553 MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
555 MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
556 MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
557 MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
558 MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
559 MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
561 MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
562 MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
563 MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
564 MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
565 MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
567 MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
568 MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
569 MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
570 MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
571 MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
573 MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
574 MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
575 MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
577 MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
578 MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
579 MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
580 MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
581 MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
582 MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
583 MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
584 MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
585 MUX_CFG(DM365, VIN_YIN_EN, 0, 0, 0xfff, 0, false)
587 INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
588 INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
589 INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
590 INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
591 INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
592 INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
593 INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
594 INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
595 INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
596 INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
600 static struct emac_platform_data dm365_emac_pdata = {
601 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
602 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
603 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
604 .mdio_reg_offset = DM365_EMAC_MDIO_OFFSET,
605 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
606 .version = EMAC_VERSION_2,
609 static struct resource dm365_emac_resources[] = {
611 .start = DM365_EMAC_BASE,
612 .end = DM365_EMAC_BASE + 0x47ff,
613 .flags = IORESOURCE_MEM,
616 .start = IRQ_DM365_EMAC_RXTHRESH,
617 .end = IRQ_DM365_EMAC_RXTHRESH,
618 .flags = IORESOURCE_IRQ,
621 .start = IRQ_DM365_EMAC_RXPULSE,
622 .end = IRQ_DM365_EMAC_RXPULSE,
623 .flags = IORESOURCE_IRQ,
626 .start = IRQ_DM365_EMAC_TXPULSE,
627 .end = IRQ_DM365_EMAC_TXPULSE,
628 .flags = IORESOURCE_IRQ,
631 .start = IRQ_DM365_EMAC_MISCPULSE,
632 .end = IRQ_DM365_EMAC_MISCPULSE,
633 .flags = IORESOURCE_IRQ,
637 static struct platform_device dm365_emac_device = {
638 .name = "davinci_emac",
641 .platform_data = &dm365_emac_pdata,
643 .num_resources = ARRAY_SIZE(dm365_emac_resources),
644 .resource = dm365_emac_resources,
647 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
655 [IRQ_DM365_INSFINT] = 7,
659 [IRQ_DM365_IMCOPINT] = 4,
661 [IRQ_DM365_RTOINT] = 7,
662 [IRQ_DM365_TINT5] = 7,
663 [IRQ_DM365_TINT6] = 5,
669 [IRQ_DM365_SPINT2_1] = 7,
670 [IRQ_DM365_TINT7] = 7,
671 [IRQ_DM365_SDIOINT0] = 7,
675 [IRQ_DM365_MMCINT1] = 7,
676 [IRQ_DM365_PWMINT3] = 7,
679 [IRQ_DM365_SDIOINT1] = 2,
680 [IRQ_TINT0_TINT12] = 7,
681 [IRQ_TINT0_TINT34] = 7,
682 [IRQ_TINT1_TINT12] = 7,
683 [IRQ_TINT1_TINT34] = 7,
690 [IRQ_DM365_SPIINT0_0] = 3,
691 [IRQ_DM365_SPIINT3_0] = 3,
692 [IRQ_DM365_GPIO0] = 3,
693 [IRQ_DM365_GPIO1] = 7,
694 [IRQ_DM365_GPIO2] = 4,
695 [IRQ_DM365_GPIO3] = 4,
696 [IRQ_DM365_GPIO4] = 7,
697 [IRQ_DM365_GPIO5] = 7,
698 [IRQ_DM365_GPIO6] = 7,
699 [IRQ_DM365_GPIO7] = 7,
700 [IRQ_DM365_EMAC_RXTHRESH] = 7,
701 [IRQ_DM365_EMAC_RXPULSE] = 7,
702 [IRQ_DM365_EMAC_TXPULSE] = 7,
703 [IRQ_DM365_EMAC_MISCPULSE] = 7,
704 [IRQ_DM365_GPIO12] = 7,
705 [IRQ_DM365_GPIO13] = 7,
706 [IRQ_DM365_GPIO14] = 7,
707 [IRQ_DM365_GPIO15] = 7,
708 [IRQ_DM365_KEYINT] = 7,
709 [IRQ_DM365_TCERRINT2] = 7,
710 [IRQ_DM365_TCERRINT3] = 7,
711 [IRQ_DM365_EMUINT] = 7,
714 /* Four Transfer Controllers on DM365 */
716 dm365_queue_tc_mapping[][2] = {
717 /* {event queue no, TC no} */
726 dm365_queue_priority_mapping[][2] = {
727 /* {event queue no, Priority} */
735 static struct edma_soc_info dm365_edma_info[] = {
742 .queue_tc_mapping = dm365_queue_tc_mapping,
743 .queue_priority_mapping = dm365_queue_priority_mapping,
747 static struct resource edma_resources[] = {
751 .end = 0x01c00000 + SZ_64K - 1,
752 .flags = IORESOURCE_MEM,
757 .end = 0x01c10000 + SZ_1K - 1,
758 .flags = IORESOURCE_MEM,
763 .end = 0x01c10400 + SZ_1K - 1,
764 .flags = IORESOURCE_MEM,
769 .end = 0x01c10800 + SZ_1K - 1,
770 .flags = IORESOURCE_MEM,
775 .end = 0x01c10c00 + SZ_1K - 1,
776 .flags = IORESOURCE_MEM,
781 .flags = IORESOURCE_IRQ,
785 .start = IRQ_CCERRINT,
786 .flags = IORESOURCE_IRQ,
788 /* not using TC*_ERR */
791 static struct platform_device dm365_edma_device = {
794 .dev.platform_data = dm365_edma_info,
795 .num_resources = ARRAY_SIZE(edma_resources),
796 .resource = edma_resources,
799 static struct map_desc dm365_io_desc[] = {
802 .pfn = __phys_to_pfn(IO_PHYS),
807 .virtual = SRAM_VIRT,
808 .pfn = __phys_to_pfn(0x00010000),
810 /* MT_MEMORY_NONCACHED requires supersection alignment */
815 /* Contents of JTAG ID register used to identify exact cpu type */
816 static struct davinci_id dm365_ids[] = {
820 .manufacturer = 0x017,
821 .cpu_id = DAVINCI_CPU_ID_DM365,
826 static void __iomem *dm365_psc_bases[] = {
827 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
830 struct davinci_timer_info dm365_timer_info = {
831 .timers = davinci_timer_instance,
832 .clockevent_id = T0_BOT,
833 .clocksource_id = T0_TOP,
836 static struct plat_serial8250_port dm365_serial_platform_data[] = {
838 .mapbase = DAVINCI_UART0_BASE,
840 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
846 .mapbase = DAVINCI_UART1_BASE,
848 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
858 static struct platform_device dm365_serial_device = {
859 .name = "serial8250",
860 .id = PLAT8250_DEV_PLATFORM,
862 .platform_data = dm365_serial_platform_data,
866 static struct davinci_soc_info davinci_soc_info_dm365 = {
867 .io_desc = dm365_io_desc,
868 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
869 .jtag_id_base = IO_ADDRESS(0x01c40028),
871 .ids_num = ARRAY_SIZE(dm365_ids),
872 .cpu_clks = dm365_clks,
873 .psc_bases = dm365_psc_bases,
874 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
875 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
876 .pinmux_pins = dm365_pins,
877 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
878 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
879 .intc_type = DAVINCI_INTC_TYPE_AINTC,
880 .intc_irq_prios = dm365_default_priorities,
881 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
882 .timer_info = &dm365_timer_info,
883 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
886 .serial_dev = &dm365_serial_device,
887 .emac_pdata = &dm365_emac_pdata,
888 .sram_dma = 0x00010000,
892 void __init dm365_init(void)
894 davinci_common_init(&davinci_soc_info_dm365);
897 static int __init dm365_init_devices(void)
899 if (!cpu_is_davinci_dm365())
902 davinci_cfg_reg(DM365_INT_EDMA_CC);
903 platform_device_register(&dm365_edma_device);
904 platform_device_register(&dm365_emac_device);
908 postcore_initcall(dm365_init_devices);