arch/arm/mach-highbank/highbank.c

   1 /*
   2  * Copyright 2010-2011 Calxeda, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #include <linux/clk.h>
  17 #include <linux/clkdev.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/of.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/of_address.h>
  25 #include <linux/smp.h>
  26
  27 #include <asm/cacheflush.h>
  28 #include <asm/smp_plat.h>
  29 #include <asm/smp_scu.h>
  30 #include <asm/smp_twd.h>
  31 #include <asm/hardware/arm_timer.h>
  32 #include <asm/hardware/timer-sp.h>
  33 #include <asm/hardware/gic.h>
  34 #include <asm/hardware/cache-l2x0.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/time.h>
  38
  39 #include "core.h"
  40 #include "sysregs.h"
  41
  42 void __iomem *sregs_base;
  43
  44 #define HB_SCU_VIRT_BASE        0xfee00000
  45 void __iomem *scu_base_addr = ((void __iomem *)(HB_SCU_VIRT_BASE));
  46
  47 static struct map_desc scu_io_desc __initdata = {
  48         .virtual        = HB_SCU_VIRT_BASE,
  49         .pfn            = 0, /* run-time */
  50         .length         = SZ_4K,
  51         .type           = MT_DEVICE,
  52 };
  53
  54 static void __init highbank_scu_map_io(void)
  55 {
  56         unsigned long base;
  57
  58         /* Get SCU base */
  59         asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
  60
  61         scu_io_desc.pfn = __phys_to_pfn(base);
  62         iotable_init(&scu_io_desc, 1);
  63 }
  64
  65 static void __init highbank_map_io(void)
  66 {
  67         highbank_scu_map_io();
  68         highbank_lluart_map_io();
  69 }
  70
  71 #define HB_JUMP_TABLE_PHYS(cpu)         (0x40 + (0x10 * (cpu)))
  72 #define HB_JUMP_TABLE_VIRT(cpu)         phys_to_virt(HB_JUMP_TABLE_PHYS(cpu))
  73
  74 void highbank_set_cpu_jump(int cpu, void *jump_addr)
  75 {
  76         cpu = cpu_logical_map(cpu);
  77         writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
  78         __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
  79         outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
  80                           HB_JUMP_TABLE_PHYS(cpu) + 15);
  81 }
  82
  83 const static struct of_device_id irq_match[] = {
  84         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
  85         {}
  86 };
  87
  88 #ifdef CONFIG_CACHE_L2X0
  89 static void highbank_l2x0_disable(void)
  90 {
  91         /* Disable PL310 L2 Cache controller */
  92         highbank_smc1(0x102, 0x0);
  93 }
  94 #endif
  95
  96 static void __init highbank_init_irq(void)
  97 {
  98         of_irq_init(irq_match);
  99
 100 #ifdef CONFIG_CACHE_L2X0
 101         /* Enable PL310 L2 Cache controller */
 102         highbank_smc1(0x102, 0x1);
 103         l2x0_of_init(0, ~0UL);
 104         outer_cache.disable = highbank_l2x0_disable;
 105 #endif
 106 }
 107
 108 static struct clk_lookup lookup = {
 109         .dev_id = "sp804",
 110         .con_id = NULL,
 111 };
 112
 113 static void __init highbank_timer_init(void)
 114 {
 115         int irq;
 116         struct device_node *np;
 117         void __iomem *timer_base;
 118
 119         /* Map system registers */
 120         np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
 121         sregs_base = of_iomap(np, 0);
 122         WARN_ON(!sregs_base);
 123
 124         np = of_find_compatible_node(NULL, NULL, "arm,sp804");
 125         timer_base = of_iomap(np, 0);
 126         WARN_ON(!timer_base);
 127         irq = irq_of_parse_and_map(np, 0);
 128
 129         highbank_clocks_init();
 130         lookup.clk = of_clk_get(np, 0);
 131         clkdev_add(&lookup);
 132
 133         sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
 134         sp804_clockevents_init(timer_base, irq, "timer0");
 135
 136         twd_local_timer_of_register();
 137 }
 138
 139 static struct sys_timer highbank_timer = {
 140         .init = highbank_timer_init,
 141 };
 142
 143 static void highbank_power_off(void)
 144 {
 145         hignbank_set_pwr_shutdown();
 146         scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
 147
 148         while (1)
 149                 cpu_do_idle();
 150 }
 151
 152 static void __init highbank_init(void)
 153 {
 154         pm_power_off = highbank_power_off;
 155         highbank_pm_init();
 156
 157         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 158 }
 159
 160 static const char *highbank_match[] __initconst = {
 161         "calxeda,highbank",
 162         NULL,
 163 };
 164
 165 DT_MACHINE_START(HIGHBANK, "Highbank")
 166         .smp            = smp_ops(highbank_smp_ops),
 167         .map_io         = highbank_map_io,
 168         .init_irq       = highbank_init_irq,
 169         .timer          = &highbank_timer,
 170         .handle_irq     = gic_handle_irq,
 171         .init_machine   = highbank_init,
 172         .dt_compat      = highbank_match,
 173         .restart        = highbank_restart,
 174 MACHINE_END