2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/timex.h>
27 #include <linux/clocksource.h>
28 #include <linux/clockchips.h>
30 #include <linux/export.h>
31 #include <linux/gpio.h>
34 #include <mach/hardware.h>
36 #include <asm/uaccess.h>
37 #include <asm/pgtable.h>
40 #include <asm/sched_clock.h>
41 #include <asm/system_misc.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
47 static void __init ixp4xx_clocksource_init(void);
48 static void __init ixp4xx_clockevent_init(void);
49 static struct clock_event_device clockevent_ixp4xx;
51 /*************************************************************************
52 * IXP4xx chipset I/O mapping
53 *************************************************************************/
54 static struct map_desc ixp4xx_io_desc[] __initdata = {
55 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
56 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
57 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
58 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
60 }, { /* Expansion Bus Config Registers */
61 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
62 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
63 .length = IXP4XX_EXP_CFG_REGION_SIZE,
65 }, { /* PCI Registers */
66 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
67 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
68 .length = IXP4XX_PCI_CFG_REGION_SIZE,
70 }, { /* Queue Manager */
71 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
72 .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
73 .length = IXP4XX_QMGR_REGION_SIZE,
78 void __init ixp4xx_map_io(void)
80 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
84 /*************************************************************************
85 * IXP4xx chipset IRQ handling
87 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
88 * (be it PCI or something else) configures that GPIO line
90 **************************************************************************/
91 enum ixp4xx_irq_type {
92 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
95 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
96 static unsigned long long ixp4xx_irq_edge = 0;
99 * IRQ -> GPIO mapping table
101 static signed char irq2gpio[32] = {
102 -1, -1, -1, -1, -1, -1, 0, 1,
103 -1, -1, -1, -1, -1, -1, -1, -1,
104 -1, -1, -1, 2, 3, 4, 5, 6,
105 7, 8, 9, 10, 11, 12, -1, -1,
108 static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
112 for (irq = 0; irq < 32; irq++) {
113 if (irq2gpio[irq] == gpio)
119 int irq_to_gpio(unsigned int irq)
121 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
128 EXPORT_SYMBOL(irq_to_gpio);
130 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
132 int line = irq2gpio[d->irq];
134 enum ixp4xx_irq_type irq_type;
135 volatile u32 *int_reg;
144 case IRQ_TYPE_EDGE_BOTH:
145 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
146 irq_type = IXP4XX_IRQ_EDGE;
148 case IRQ_TYPE_EDGE_RISING:
149 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
150 irq_type = IXP4XX_IRQ_EDGE;
152 case IRQ_TYPE_EDGE_FALLING:
153 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
154 irq_type = IXP4XX_IRQ_EDGE;
156 case IRQ_TYPE_LEVEL_HIGH:
157 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
158 irq_type = IXP4XX_IRQ_LEVEL;
160 case IRQ_TYPE_LEVEL_LOW:
161 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
162 irq_type = IXP4XX_IRQ_LEVEL;
168 if (irq_type == IXP4XX_IRQ_EDGE)
169 ixp4xx_irq_edge |= (1 << d->irq);
171 ixp4xx_irq_edge &= ~(1 << d->irq);
173 if (line >= 8) { /* pins 8-15 */
175 int_reg = IXP4XX_GPIO_GPIT2R;
176 } else { /* pins 0-7 */
177 int_reg = IXP4XX_GPIO_GPIT1R;
180 /* Clear the style for the appropriate pin */
181 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
182 (line * IXP4XX_GPIO_STYLE_SIZE));
184 *IXP4XX_GPIO_GPISR = (1 << line);
186 /* Set the new style */
187 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
189 /* Configure the line as an input */
190 gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
195 static void ixp4xx_irq_mask(struct irq_data *d)
197 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
198 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
200 *IXP4XX_ICMR &= ~(1 << d->irq);
203 static void ixp4xx_irq_ack(struct irq_data *d)
205 int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
208 *IXP4XX_GPIO_GPISR = (1 << line);
212 * Level triggered interrupts on GPIO lines can only be cleared when the
213 * interrupt condition disappears.
215 static void ixp4xx_irq_unmask(struct irq_data *d)
217 if (!(ixp4xx_irq_edge & (1 << d->irq)))
220 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
221 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
223 *IXP4XX_ICMR |= (1 << d->irq);
226 static struct irq_chip ixp4xx_irq_chip = {
228 .irq_ack = ixp4xx_irq_ack,
229 .irq_mask = ixp4xx_irq_mask,
230 .irq_unmask = ixp4xx_irq_unmask,
231 .irq_set_type = ixp4xx_set_irq_type,
234 void __init ixp4xx_init_irq(void)
239 * ixp4xx does not implement the XScale PWRMODE register
240 * so it must not call cpu_do_idle().
244 /* Route all sources to IRQ instead of FIQ */
247 /* Disable all interrupt */
250 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
251 /* Route upper 32 sources to IRQ instead of FIQ */
252 *IXP4XX_ICLR2 = 0x00;
254 /* Disable upper 32 interrupts */
255 *IXP4XX_ICMR2 = 0x00;
258 /* Default to all level triggered */
259 for(i = 0; i < NR_IRQS; i++) {
260 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
262 set_irq_flags(i, IRQF_VALID);
267 /*************************************************************************
269 * We use OS timer1 on the CPU for the timer tick and the timestamp
270 * counter as a source of real clock ticks to account for missed jiffies.
271 *************************************************************************/
273 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
275 struct clock_event_device *evt = dev_id;
277 /* Clear Pending Interrupt by writing '1' to it */
278 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
280 evt->event_handler(evt);
285 static struct irqaction ixp4xx_timer_irq = {
287 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
288 .handler = ixp4xx_timer_interrupt,
289 .dev_id = &clockevent_ixp4xx,
292 void __init ixp4xx_timer_init(void)
294 /* Reset/disable counter */
297 /* Clear Pending Interrupt by writing '1' to it */
298 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
300 /* Reset time-stamp counter */
303 /* Connect the interrupt handler and enable the interrupt */
304 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
306 ixp4xx_clocksource_init();
307 ixp4xx_clockevent_init();
310 struct sys_timer ixp4xx_timer = {
311 .init = ixp4xx_timer_init,
314 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
316 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
318 memcpy(&ixp4xx_udc_info, info, sizeof *info);
321 static struct resource ixp4xx_udc_resources[] = {
325 .flags = IORESOURCE_MEM,
328 .start = IRQ_IXP4XX_USB,
329 .end = IRQ_IXP4XX_USB,
330 .flags = IORESOURCE_IRQ,
335 * USB device controller. The IXP4xx uses the same controller as PXA25X,
336 * so we just use the same device.
338 static struct platform_device ixp4xx_udc_device = {
339 .name = "pxa25x-udc",
342 .resource = ixp4xx_udc_resources,
344 .platform_data = &ixp4xx_udc_info,
348 static struct platform_device *ixp4xx_devices[] __initdata = {
352 static struct resource ixp46x_i2c_resources[] = {
356 .flags = IORESOURCE_MEM,
359 .start = IRQ_IXP4XX_I2C,
360 .end = IRQ_IXP4XX_I2C,
361 .flags = IORESOURCE_IRQ
366 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
367 * we just use the same device name.
369 static struct platform_device ixp46x_i2c_controller = {
370 .name = "IOP3xx-I2C",
373 .resource = ixp46x_i2c_resources
376 static struct platform_device *ixp46x_devices[] __initdata = {
377 &ixp46x_i2c_controller
380 unsigned long ixp4xx_exp_bus_size;
381 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
383 static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
385 gpio_line_config(gpio, IXP4XX_GPIO_IN);
390 static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
393 gpio_line_set(gpio, level);
394 gpio_line_config(gpio, IXP4XX_GPIO_OUT);
399 static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
403 gpio_line_get(gpio, &value);
408 static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
411 gpio_line_set(gpio, value);
414 static struct gpio_chip ixp4xx_gpio_chip = {
415 .label = "IXP4XX_GPIO_CHIP",
416 .direction_input = ixp4xx_gpio_direction_input,
417 .direction_output = ixp4xx_gpio_direction_output,
418 .get = ixp4xx_gpio_get_value,
419 .set = ixp4xx_gpio_set_value,
420 .to_irq = ixp4xx_gpio_to_irq,
425 void __init ixp4xx_sys_init(void)
427 ixp4xx_exp_bus_size = SZ_16M;
429 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
431 gpiochip_add(&ixp4xx_gpio_chip);
433 if (cpu_is_ixp46x()) {
436 platform_add_devices(ixp46x_devices,
437 ARRAY_SIZE(ixp46x_devices));
439 for (region = 0; region < 7; region++) {
440 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
441 ixp4xx_exp_bus_size = SZ_32M;
447 printk("IXP4xx: Using %luMiB expansion bus window size\n",
448 ixp4xx_exp_bus_size >> 20);
454 static u32 notrace ixp4xx_read_sched_clock(void)
463 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
468 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
469 EXPORT_SYMBOL(ixp4xx_timer_freq);
470 static void __init ixp4xx_clocksource_init(void)
472 setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
474 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
475 ixp4xx_clocksource_read);
481 static int ixp4xx_set_next_event(unsigned long evt,
482 struct clock_event_device *unused)
484 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
486 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
491 static void ixp4xx_set_mode(enum clock_event_mode mode,
492 struct clock_event_device *evt)
494 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
495 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
498 case CLOCK_EVT_MODE_PERIODIC:
499 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
500 opts = IXP4XX_OST_ENABLE;
502 case CLOCK_EVT_MODE_ONESHOT:
503 /* period set by 'set next_event' */
505 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
507 case CLOCK_EVT_MODE_SHUTDOWN:
508 opts &= ~IXP4XX_OST_ENABLE;
510 case CLOCK_EVT_MODE_RESUME:
511 opts |= IXP4XX_OST_ENABLE;
513 case CLOCK_EVT_MODE_UNUSED:
519 *IXP4XX_OSRT1 = osrt | opts;
522 static struct clock_event_device clockevent_ixp4xx = {
523 .name = "ixp4xx timer1",
524 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
527 .set_mode = ixp4xx_set_mode,
528 .set_next_event = ixp4xx_set_next_event,
531 static void __init ixp4xx_clockevent_init(void)
533 clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
534 clockevent_ixp4xx.shift);
535 clockevent_ixp4xx.max_delta_ns =
536 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
537 clockevent_ixp4xx.min_delta_ns =
538 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
539 clockevent_ixp4xx.cpumask = cpumask_of(0);
541 clockevents_register_device(&clockevent_ixp4xx);
544 void ixp4xx_restart(char mode, const char *cmd)
546 if ( 1 && mode == 's') {
547 /* Jump into ROM at address 0 */
550 /* Use on-chip reset capability */
552 /* set the "key" register to enable access to
553 * "timer" and "enable" registers
555 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
557 /* write 0 to the timer register for an immediate reset */
560 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
564 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
566 * In the case of using indirect PCI, we simply return the actual PCI
567 * address and our read/write implementation use that to drive the
568 * access registers. If something outside of PCI is ioremap'd, we
569 * fallback to the default.
572 static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
573 unsigned int mtype, void *caller)
575 if (!is_pci_memory(addr))
576 return __arm_ioremap_caller(addr, size, mtype, caller);
578 return (void __iomem *)addr;
581 static void ixp4xx_iounmap(void __iomem *addr)
583 if (!is_pci_memory((__force u32)addr))
587 void __init ixp4xx_init_early(void)
589 arch_ioremap_caller = ixp4xx_ioremap_caller;
590 arch_iounmap = ixp4xx_iounmap;
593 void __init ixp4xx_init_early(void) {}