2 * Copyright (C) 2009-2011 Freescale Semiconductor, Inc.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/init.h>
14 #include <linux/clk.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/i2c.h>
18 #include <linux/gpio.h>
19 #include <linux/delay.h>
21 #include <linux/fsl_devices.h>
22 #include <linux/fec.h>
23 #include <linux/gpio_keys.h>
24 #include <linux/input.h>
25 #include <linux/spi/flash.h>
26 #include <linux/spi/spi.h>
27 #include <linux/ipu.h>
28 #include <linux/mxcfb.h>
29 #include <linux/pwm_backlight.h>
31 #include <mach/common.h>
32 #include <mach/hardware.h>
33 #include <mach/iomux-mx51.h>
34 #include <mach/mxc_ehci.h>
35 #include <mach/ipu-v3.h>
36 #include <mach/mxc_dvfs.h>
39 #include <asm/setup.h>
40 #include <asm/mach-types.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/time.h>
44 #include "devices-imx51.h"
47 #include "cpu_op-mx51.h"
49 #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
50 #define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
51 #define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5)
52 #define BABBAGE_VGA_RESET IMX_GPIO_NR(2, 13)
53 #define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
54 #define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
55 #define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
56 #define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
57 #define MX51_BBG_SD1_CD IMX_GPIO_NR(1, 0)
58 #define MX51_BBG_SD1_WP IMX_GPIO_NR(1, 1)
59 #define MX51_BBG_SD2_CD IMX_GPIO_NR(1, 6)
60 #define MX51_BBG_SD2_WP IMX_GPIO_NR(1, 5)
61 #define BABBAGE_AUDAMP_STBY IMX_GPIO_NR(2, 17)
62 #define BABBAGE_HEADPHONE_DET IMX_GPIO_NR(3, 26)
63 #define BABBAGE_AUDIO_CLK_EN IMX_GPIO_NR(4, 26)
64 #define BABBAGE_OSC_EN_B IMX_GPIO_NR(2, 2)
66 #define BABBAGE_26M_OSC_EN IMX_GPIO_NR(3, 1)
67 #define BABBAGE_LVDS_POWER_DOWN IMX_GPIO_NR(3, 3) /* GPIO_3_3 */
68 #define BABBAGE_DISP_BRIGHTNESS_CTL IMX_GPIO_NR(3, 4) /* GPIO_3_4 */
69 #define BABBAGE_DVI_RESET IMX_GPIO_NR(3, 5) /* GPIO_3_5 */
70 #define BABBAGE_DVI_POWER IMX_GPIO_NR(3, 6) /* GPIO_3_6 */
71 #define BABBAGE_HEADPHONE_DET IMX_GPIO_NR(3, 26) /* GPIO_3_26 */
72 #define BABBAGE_DVI_DET IMX_GPIO_NR(3, 28) /* GPIO_3_28 */
74 #define BABBAGE_LCD_3V3_ON IMX_GPIO_NR(4, 9) /* GPIO_4_9 */
75 #define BABBAGE_LCD_5V_ON IMX_GPIO_NR(4, 10) /* GPIO_4_10 */
76 #define BABBAGE_DVI_I2C_EN IMX_GPIO_NR(4, 14) /* GPIO_4_14 */
79 #define MX51_USB_CTRL_1_OFFSET 0x10
80 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
82 #define MX51_USB_PLLDIV_12_MHZ 0x00
83 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
84 #define MX51_USB_PLL_DIV_24_MHZ 0x02
86 extern char *lp_reg_id;
87 extern int (*set_cpu_voltage)(u32 volt);
88 extern int mx5_set_cpu_voltage(struct regulator *gp_reg, u32 cpu_volt);
90 static struct regulator *cpu_regulator;
91 static char *gp_reg_id;
93 static struct gpio_keys_button babbage_buttons[] = {
95 .gpio = BABBAGE_POWER_KEY,
103 static const struct gpio_keys_platform_data imx_button_data __initconst = {
104 .buttons = babbage_buttons,
105 .nbuttons = ARRAY_SIZE(babbage_buttons),
108 static iomux_v3_cfg_t mx51babbage_pads[] = {
110 MX51_PAD_UART1_RXD__UART1_RXD,
111 MX51_PAD_UART1_TXD__UART1_TXD,
112 MX51_PAD_UART1_RTS__UART1_RTS,
113 MX51_PAD_UART1_CTS__UART1_CTS,
116 MX51_PAD_UART2_RXD__UART2_RXD,
117 MX51_PAD_UART2_TXD__UART2_TXD,
120 MX51_PAD_EIM_D25__UART3_RXD,
121 MX51_PAD_EIM_D26__UART3_TXD,
122 MX51_PAD_EIM_D27__UART3_RTS,
123 MX51_PAD_EIM_D24__UART3_CTS,
126 MX51_PAD_EIM_D16__I2C1_SDA,
127 MX51_PAD_EIM_D19__I2C1_SCL,
130 MX51_PAD_KEY_COL4__I2C2_SCL,
131 MX51_PAD_KEY_COL5__I2C2_SDA,
134 MX51_PAD_I2C1_CLK__I2C1_CLK,
135 MX51_PAD_I2C1_DAT__I2C1_DAT,
138 MX51_PAD_USBH1_CLK__USBH1_CLK,
139 MX51_PAD_USBH1_DIR__USBH1_DIR,
140 MX51_PAD_USBH1_NXT__USBH1_NXT,
141 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
142 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
143 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
144 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
145 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
146 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
147 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
148 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
150 /* USB HUB reset line*/
151 MX51_PAD_GPIO1_7__GPIO1_7,
154 MX51_PAD_EIM_EB2__FEC_MDIO,
155 MX51_PAD_EIM_EB3__FEC_RDATA1,
156 MX51_PAD_EIM_CS2__FEC_RDATA2,
157 MX51_PAD_EIM_CS3__FEC_RDATA3,
158 MX51_PAD_EIM_CS4__FEC_RX_ER,
159 MX51_PAD_EIM_CS5__FEC_CRS,
160 MX51_PAD_NANDF_RB2__FEC_COL,
161 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
162 MX51_PAD_NANDF_D9__FEC_RDATA0,
163 MX51_PAD_NANDF_D8__FEC_TDATA0,
164 MX51_PAD_NANDF_CS2__FEC_TX_ER,
165 MX51_PAD_NANDF_CS3__FEC_MDC,
166 MX51_PAD_NANDF_CS4__FEC_TDATA1,
167 MX51_PAD_NANDF_CS5__FEC_TDATA2,
168 MX51_PAD_NANDF_CS6__FEC_TDATA3,
169 MX51_PAD_NANDF_CS7__FEC_TX_EN,
170 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
172 /* FEC PHY reset line */
173 MX51_PAD_EIM_A20__GPIO2_14,
175 MX51_PAD_GPIO1_0__GPIO1_0,
176 MX51_PAD_GPIO1_1__GPIO1_1,
177 MX51_PAD_GPIO1_5__GPIO1_5,
178 MX51_PAD_GPIO1_6__GPIO1_6,
180 MX51_PAD_SD1_CMD__SD1_CMD,
181 MX51_PAD_SD1_CLK__SD1_CLK,
182 MX51_PAD_SD1_DATA0__SD1_DATA0,
183 MX51_PAD_SD1_DATA1__SD1_DATA1,
184 MX51_PAD_SD1_DATA2__SD1_DATA2,
185 MX51_PAD_SD1_DATA3__SD1_DATA3,
188 MX51_PAD_SD2_CMD__SD2_CMD,
189 MX51_PAD_SD2_CLK__SD2_CLK,
190 MX51_PAD_SD2_DATA0__SD2_DATA0,
191 MX51_PAD_SD2_DATA1__SD2_DATA1,
192 MX51_PAD_SD2_DATA2__SD2_DATA2,
193 MX51_PAD_SD2_DATA3__SD2_DATA3,
196 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
197 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
198 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
199 MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
200 MX51_PAD_CSPI1_SS0__GPIO4_24,
201 MX51_PAD_CSPI1_SS1__GPIO4_25,
202 MX51_PAD_CSPI1_RDY__GPIO4_26,
203 MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
206 MX51_PAD_EIM_A19__GPIO2_13,
207 MX51_PAD_DI1_D0_CS__GPIO3_3,
208 MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
209 MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
210 MX51_PAD_NANDF_D14__GPIO3_26,
211 MX51_PAD_NANDF_D12__GPIO3_28,
212 MX51_PAD_CSI2_D12__GPIO4_9,
213 MX51_PAD_CSI2_D13__GPIO4_10,
214 MX51_PAD_CSI2_HSYNC__GPIO4_14,
216 MX51_PAD_DI_GP4__DI2_PIN15,
217 MX51_PAD_GPIO1_2__PWM1_PWMO,
219 #ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL
220 MX51_PAD_DISP1_DAT22__DISP2_DAT16,
221 MX51_PAD_DISP1_DAT23__DISP2_DAT17,
223 MX51_PAD_DI1_D1_CS__GPIO3_4,
225 MX51_PAD_EIM_LBA__GPIO3_1,
226 MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
227 MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
228 MX51_PAD_AUD3_BB_CK__AUD3_TXC,
229 MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
231 MX51_PAD_OWIRE_LINE__SPDIF_OUT,
234 static struct mxc_dvfs_platform_data bbg_dvfscore_data = {
236 .clk1_id = "cpu_clk",
237 .clk2_id = "gpc_dvfs_clk",
238 .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
239 .gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
240 .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
241 .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
242 .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
243 .prediv_mask = 0x1F800,
246 .div3ck_mask = 0xE0000000,
258 static struct mxc_regulator_platform_data bbg_regulator_data = {
259 .cpu_reg_id = "cpu_vcc",
263 static const struct imxuart_platform_data uart_pdata __initconst = {
264 .flags = IMXUART_HAVE_RTSCTS,
267 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
271 static struct imxi2c_platform_data babbage_hsi2c_data = {
275 static const struct esdhc_platform_data mx51_bbg_sd1_data __initconst = {
276 .wp_gpio = MX51_BBG_SD1_WP,
277 .cd_gpio = MX51_BBG_SD1_CD,
280 static const struct esdhc_platform_data mx51_bbg_sd2_data __initconst = {
281 .wp_gpio = MX51_BBG_SD2_WP,
282 .cd_gpio = MX51_BBG_SD2_CD,
285 static void babbage_suspend_enter(void)
289 static void babbage_suspend_exit(void)
291 /*clear the EMPGC0/1 bits */
292 __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
293 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
296 static struct mxc_pm_platform_data babbage_pm_data = {
297 .suspend_enter = babbage_suspend_enter,
298 .suspend_exit = babbage_suspend_exit,
301 static int gpio_usbh1_active(void)
303 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
304 iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
307 /* Set USBH1_STP to GPIO and toggle it */
308 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
309 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
312 pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
315 gpio_direction_output(BABBAGE_USBH1_STP, 0);
316 gpio_set_value(BABBAGE_USBH1_STP, 1);
318 gpio_free(BABBAGE_USBH1_STP);
320 /* De-assert USB PHY RESETB */
321 mxc_iomux_v3_setup_pad(phyreset_gpio);
322 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
325 pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
328 gpio_direction_output(BABBAGE_PHY_RESET, 1);
332 static inline void babbage_usbhub_reset(void)
336 /* Bring USB hub out of reset */
337 ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
339 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
342 gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
344 /* USB HUB RESET - De-assert USB HUB RESET_N */
346 gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
348 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
351 static inline void babbage_fec_reset(void)
356 ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
357 GPIOF_OUT_INIT_LOW, "fec-phy-reset");
359 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
363 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
366 /* This function is board specific as the bit mask for the plldiv will also
367 be different for other Freescale SoCs, thus a common bitmask is not
368 possible and cannot get place in /plat-mxc/ehci.c.*/
369 static int initialize_otg_port(struct platform_device *pdev)
372 void __iomem *usb_base;
373 void __iomem *usbother_base;
375 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
378 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
380 /* Set the PHY clock to 19.2MHz */
381 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
382 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
383 v |= MX51_USB_PLL_DIV_19_2_MHZ;
384 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
389 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
392 static int initialize_usbh1_port(struct platform_device *pdev)
395 void __iomem *usb_base;
396 void __iomem *usbother_base;
398 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
401 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
403 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
404 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
405 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
410 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
411 MXC_EHCI_ITC_NO_THRESHOLD);
414 static struct mxc_usbh_platform_data dr_utmi_config = {
415 .init = initialize_otg_port,
416 .portsc = MXC_EHCI_UTMI_16BIT,
419 static struct fsl_usb2_platform_data usb_pdata = {
420 .operating_mode = FSL_USB2_DR_DEVICE,
421 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
424 static struct mxc_usbh_platform_data usbh1_config = {
425 .init = initialize_usbh1_port,
426 .portsc = MXC_EHCI_MODE_ULPI,
429 static int otg_mode_host;
431 static int __init babbage_otg_mode(char *options)
433 if (!strcmp(options, "host"))
435 else if (!strcmp(options, "device"))
438 pr_info("otg_mode neither \"host\" nor \"device\". "
439 "Defaulting to device\n");
442 __setup("otg_mode=", babbage_otg_mode);
444 static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
446 .modalias = "mtd_dataflash",
447 .max_speed_hz = 25000000,
451 .platform_data = NULL,
455 static int mx51_babbage_spi_cs[] = {
460 static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
461 .chipselect = mx51_babbage_spi_cs,
462 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
465 static struct fsl_mxc_lcd_platform_data lcdif_data = {
468 .default_ifmt = IPU_PIX_FMT_RGB565,
471 static struct ipuv3_fb_platform_data bbg_fb_data[] = {
474 .interface_pix_fmt = IPU_PIX_FMT_RGB24,
475 .mode_str = "1024x768M-16@60",
480 .interface_pix_fmt = IPU_PIX_FMT_RGB565,
481 .mode_str = "CLAA-WVGA",
487 static struct imx_ipuv3_platform_data ipu_data = {
491 static struct platform_pwm_backlight_data bbg_pwm_backlight_data = {
493 .max_brightness = 255,
494 .dft_brightness = 128,
495 .pwm_period_ns = 78770,
498 static struct fsl_mxc_tve_platform_data tve_data = {
502 static void vga_reset(void)
505 gpio_set_value(BABBAGE_VGA_RESET, 0);
508 gpio_set_value(BABBAGE_VGA_RESET, 1);
509 msleep(10); /* tRES >= 50us */
510 gpio_set_value(BABBAGE_VGA_RESET, 0);
513 static struct fsl_mxc_lcd_platform_data vga_data = {
516 .analog_reg = "VAUDIO",
520 static void ddc_dvi_init(void)
523 gpio_set_value(BABBAGE_DVI_I2C_EN, 1);
526 static int ddc_dvi_update(void)
528 /* DVI cable state */
529 if (gpio_get_value(BABBAGE_DVI_DET) == 1)
535 static struct fsl_mxc_dvi_platform_data bbg_ddc_dvi_data = {
538 .init = ddc_dvi_init,
539 .update = ddc_dvi_update,
542 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
550 .irq = gpio_to_irq(BABBAGE_DVI_DET),
551 .platform_data = &bbg_ddc_dvi_data,
555 static struct i2c_board_info mxc_i2c_hs_board_info[] __initdata = {
559 .platform_data = &vga_data,
563 static struct mxc_gpu_platform_data gpu_data __initdata;
565 static int mx51_bbg_set_cpu_voltage(u32 cpu_volt)
569 if (cpu_regulator == NULL)
570 cpu_regulator = regulator_get(NULL, gp_reg_id);
571 if (!IS_ERR(cpu_regulator))
572 ret = mx5_set_cpu_voltage(cpu_regulator, cpu_volt);
578 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
579 char **cmdline, struct meminfo *mi)
582 struct tag *mem_tag = 0;
583 int total_mem = SZ_512M;
585 int gpu_mem = SZ_64M;
589 set_cpu_voltage = mx51_bbg_set_cpu_voltage;
591 for_each_tag(mem_tag, tags) {
592 if (mem_tag->hdr.tag == ATAG_MEM) {
593 total_mem = mem_tag->u.mem.size;
594 left_mem = total_mem - gpu_mem - fb_mem;
599 for_each_tag(t, tags) {
600 if (t->hdr.tag == ATAG_CMDLINE) {
601 str = t->u.cmdline.cmdline;
602 str = strstr(str, "mem=");
605 left_mem = memparse(str, &str);
606 if (left_mem == 0 || left_mem > total_mem)
607 left_mem = total_mem - gpu_mem - fb_mem;
610 str = t->u.cmdline.cmdline;
611 str = strstr(str, "gpu_memory=");
614 gpu_mem = memparse(str, &str);
622 fb_mem = total_mem - left_mem - gpu_mem;
624 gpu_mem = total_mem - left_mem;
627 mem_tag->u.mem.size = left_mem;
629 /*reserve memory for gpu*/
630 gpu_data.reserved_mem_base =
631 mem_tag->u.mem.start + left_mem;
632 gpu_data.reserved_mem_size = gpu_mem;
634 /* reserver memory for fb */
635 bbg_fb_data[0].res_base = gpu_data.reserved_mem_base
636 + gpu_data.reserved_mem_size;
637 bbg_fb_data[0].res_size = fb_mem;
641 static struct imx_ssi_platform_data bbg_ssi_pdata = {
642 .flags = IMX_SSI_DMA | IMX_SSI_SYN,
645 extern int mx51_babbage_init_mc13892(void);
646 static int bbg_sgtl5000_init(void)
648 gpio_request(BABBAGE_AUDAMP_STBY, "audio_amp");
649 gpio_direction_input(BABBAGE_AUDAMP_STBY);
651 /* Enable OSC_CKIH1_EN for audio */
652 gpio_request(BABBAGE_AUDIO_CLK_EN, "audio_clk");
653 gpio_direction_output(BABBAGE_AUDIO_CLK_EN, 0);
654 gpio_set_value(BABBAGE_AUDIO_CLK_EN, 0);
659 static struct mxc_audio_platform_data bbg_audio_data = {
663 .init = bbg_sgtl5000_init,
665 .hp_gpio = BABBAGE_HEADPHONE_DET,
669 static struct platform_device bbg_audio_device = {
670 .name = "imx-sgtl5000",
673 static struct mxc_spdif_platform_data mxc_spdif_data = {
676 .spdif_clk_44100 = 0, /* spdif_ext_clk source for 44.1KHz */
677 .spdif_clk_48000 = 7, /* audio osc source */
679 .spdif_clk = NULL, /* spdif bus clk */
683 * Board specific initialization.
685 static void __init mx51_babbage_init(void)
689 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
690 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
691 MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
693 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
694 ARRAY_SIZE(mx51babbage_pads));
696 gp_reg_id = bbg_regulator_data.cpu_reg_id;
697 lp_reg_id = bbg_regulator_data.vcc_reg_id;
699 mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
700 clk_put(mxc_spdif_data.spdif_core_clk);
702 imx51_add_imx_uart(0, &uart_pdata);
703 imx51_add_imx_uart(1, &uart_pdata);
704 imx51_add_imx_uart(2, &uart_pdata);
711 imx51_add_ipuv3(0, &ipu_data);
712 for (i = 0; i < ARRAY_SIZE(bbg_fb_data); i++)
713 imx51_add_ipuv3fb(i, &bbg_fb_data[i]);
714 imx51_add_lcdif(&lcdif_data);
716 imx51_add_tve(&tve_data);
717 imx51_add_v4l2_output(0);
719 imx51_add_mxc_pwm(0);
720 imx51_add_mxc_pwm_backlight(0, &bbg_pwm_backlight_data);
722 /* Set the PAD settings for the pwr key. */
723 mxc_iomux_v3_setup_pad(power_key);
724 imx51_add_gpio_keys(&imx_button_data);
726 imx51_add_imx_i2c(0, &babbage_i2c_data);
727 imx51_add_imx_i2c(1, &babbage_i2c_data);
729 imx51_add_spdif(&mxc_spdif_data);
730 imx51_add_spdif_dai();
731 imx51_add_spdif_audio_device();
733 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
734 mxc_register_device(&mxc_pm_device, &babbage_pm_data);
735 i2c_register_board_info(1, mxc_i2c1_board_info,
736 ARRAY_SIZE(mxc_i2c1_board_info));
738 vga_data.core_reg = NULL;
739 vga_data.io_reg = NULL;
740 vga_data.analog_reg = NULL;
742 i2c_register_board_info(3, mxc_i2c_hs_board_info,
743 ARRAY_SIZE(mxc_i2c_hs_board_info));
746 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
748 initialize_otg_port(NULL);
749 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
753 mxc_register_device(&mxc_usbh1_device, &usbh1_config);*/
754 /* setback USBH1_STP to be function */
755 mxc_iomux_v3_setup_pad(usbh1stp);
756 babbage_usbhub_reset();
758 imx51_add_sdhci_esdhc_imx(0, &mx51_bbg_sd1_data);
759 imx51_add_sdhci_esdhc_imx(1, &mx51_bbg_sd2_data);
761 spi_register_board_info(mx51_babbage_spi_board_info,
762 ARRAY_SIZE(mx51_babbage_spi_board_info));
764 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
765 imx51_add_imx2_wdt(0, NULL);
766 imx51_add_mxc_gpu(&gpu_data);
768 /* this call required to release IRAM partition held by ROM during boot,
769 * even if SCC2 driver is not part of the image
771 imx51_add_mxc_scc2();
773 if (mx51_revision() >= IMX_CHIP_REVISION_3_0) {
774 /* DVI_I2C_ENB = 0 tristates the DVI I2C level shifter */
775 gpio_request(BABBAGE_DVI_I2C_EN, "dvi-i2c-en");
776 gpio_direction_output(BABBAGE_DVI_I2C_EN, 0);
779 /* Deassert VGA reset to free i2c bus */
780 gpio_request(BABBAGE_VGA_RESET, "vga-reset");
781 gpio_direction_output(BABBAGE_VGA_RESET, 1);
783 /* LCD related gpio */
784 gpio_request(BABBAGE_DISP_BRIGHTNESS_CTL, "disp-brightness-ctl");
785 gpio_request(BABBAGE_LVDS_POWER_DOWN, "lvds-power-down");
786 gpio_request(BABBAGE_LCD_3V3_ON, "lcd-3v3-on");
787 gpio_request(BABBAGE_LCD_5V_ON, "lcd-5v-on");
788 gpio_direction_output(BABBAGE_DISP_BRIGHTNESS_CTL, 0);
789 gpio_direction_output(BABBAGE_LVDS_POWER_DOWN, 0);
790 gpio_direction_output(BABBAGE_LCD_3V3_ON, 0);
791 gpio_direction_output(BABBAGE_LCD_5V_ON, 0);
794 gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 0);
796 gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 1);
797 gpio_set_value(BABBAGE_LCD_3V3_ON, 1);
798 gpio_set_value(BABBAGE_LCD_5V_ON, 1);
801 gpio_request(BABBAGE_DVI_DET, "dvi-detect");
802 gpio_direction_input(BABBAGE_DVI_DET);
803 /* DVI Reset - Assert for i2c disabled mode */
804 gpio_request(BABBAGE_DVI_RESET, "dvi-reset");
805 gpio_direction_output(BABBAGE_DVI_RESET, 0);
807 gpio_request(BABBAGE_DVI_POWER, "dvi-power");
808 gpio_direction_output(BABBAGE_DVI_POWER, 1);
810 gpio_request(BABBAGE_26M_OSC_EN, "26M-OSC-CLK");
811 gpio_direction_output(BABBAGE_26M_OSC_EN, 1);
814 gpio_request(BABBAGE_OSC_EN_B, "osc-en");
815 gpio_direction_output(BABBAGE_OSC_EN_B, 1);
818 gpio_set_value(BABBAGE_DISP_BRIGHTNESS_CTL, 1);
820 mx51_babbage_init_mc13892();
821 mxc_register_device(&bbg_audio_device, &bbg_audio_data);
822 imx51_add_imx_ssi(1, &bbg_ssi_pdata);
824 imx51_add_dvfs_core(&bbg_dvfscore_data);
828 static void __init mx51_babbage_timer_init(void)
830 mx51_clocks_init(32768, 24000000, 22579200, 0);
833 static struct sys_timer mx51_babbage_timer = {
834 .init = mx51_babbage_timer_init,
837 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
838 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
839 .fixup = fixup_mxc_board,
840 .boot_params = MX51_PHYS_OFFSET + 0x100,
841 .map_io = mx51_map_io,
842 .init_early = imx51_init_early,
843 .init_irq = mx51_init_irq,
844 .timer = &mx51_babbage_timer,
845 .init_machine = mx51_babbage_init,