2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/gpio.h>
25 #include <linux/mxcfb.h>
26 #include <linux/ipu.h>
27 #include <linux/pwm_backlight.h>
28 #include <linux/smsc911x.h>
29 #include <linux/i2c/pca953x.h>
30 #include <linux/regulator/consumer.h>
32 #include <mach/common.h>
33 #include <mach/hardware.h>
34 #include <mach/imx-uart.h>
35 #include <mach/iomux-mx53.h>
36 #include <mach/ipu-v3.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
43 #include "devices-imx53.h"
45 #define ARD_SD1_CD IMX_GPIO_NR(1, 1)
46 #define ARD_SD1_WP IMX_GPIO_NR(1, 9)
47 #define ARD_SD2_CD IMX_GPIO_NR(1, 4)
48 #define ARD_SD2_WP IMX_GPIO_NR(1, 2)
49 #define ARD_ESAI_INT IMX_GPIO_NR(2, 4)
50 #define ARD_TS_INT IMX_GPIO_NR(7, 12)
51 #define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
53 /* Start directly after the CPU's GPIO*/
54 #define MAX7310_BASE_ADDR 224 /* 7x32 */
55 #define ARD_BACKLIGHT_ON MAX7310_BASE_ADDR
56 #define ARD_SPARE (MAX7310_BASE_ADDR + 1)
57 #define ARD_CPU_PER_RST_B (MAX7310_BASE_ADDR + 2)
58 #define ARD_MAIN_PER_RST_B (MAX7310_BASE_ADDR + 3)
59 #define ARD_IPOD_RST_B (MAX7310_BASE_ADDR + 4)
60 #define ARD_MLB_RST_B (MAX7310_BASE_ADDR + 5)
61 #define ARD_SSI_STEERING (MAX7310_BASE_ADDR + 6)
62 #define ARD_GPS_RST_B (MAX7310_BASE_ADDR + 7)
64 static struct regulator *cpu_regulator;
65 static char *gp_reg_id;
67 extern char *lp_reg_id;
68 extern void (*set_cpu_voltage)(u32 volt);
69 extern int mx5_set_cpu_voltage(struct regulator *gp_reg, u32 cpu_volt);
71 static iomux_v3_cfg_t mx53_ard_pads[] = {
73 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
74 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
75 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
76 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
77 MX53_PAD_PATA_DIOR__UART2_RTS,
78 MX53_PAD_PATA_INTRQ__UART2_CTS,
79 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
80 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
81 MX53_PAD_PATA_DA_1__UART3_CTS,
82 MX53_PAD_PATA_DA_2__UART3_RTS,
85 MX53_PAD_SD1_CMD__ESDHC1_CMD,
86 MX53_PAD_SD1_CLK__ESDHC1_CLK,
87 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
88 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
89 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
90 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
91 MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
92 MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
93 MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
94 MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
95 MX53_PAD_GPIO_1__GPIO1_1,
96 MX53_PAD_GPIO_9__GPIO1_9,
99 MX53_PAD_SD2_CLK__ESDHC2_CLK,
100 MX53_PAD_SD2_CMD__ESDHC2_CMD,
101 MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
102 MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
103 MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
104 MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
105 MX53_PAD_PATA_DATA12__ESDHC2_DAT4,
106 MX53_PAD_PATA_DATA13__ESDHC2_DAT5,
107 MX53_PAD_PATA_DATA14__ESDHC2_DAT6,
108 MX53_PAD_PATA_DATA15__ESDHC2_DAT7,
109 MX53_PAD_GPIO_4__GPIO1_4,
110 MX53_PAD_GPIO_2__GPIO1_2,
114 MX53_PAD_EIM_EB3__GPIO2_31,
115 MX53_PAD_EIM_D16__EMI_WEIM_D_16,
116 MX53_PAD_EIM_D17__EMI_WEIM_D_17,
117 MX53_PAD_EIM_D18__EMI_WEIM_D_18,
118 MX53_PAD_EIM_D19__EMI_WEIM_D_19,
119 MX53_PAD_EIM_D20__EMI_WEIM_D_20,
120 MX53_PAD_EIM_D21__EMI_WEIM_D_21,
121 MX53_PAD_EIM_D22__EMI_WEIM_D_22,
122 MX53_PAD_EIM_D23__EMI_WEIM_D_23,
123 MX53_PAD_EIM_D24__EMI_WEIM_D_24,
124 MX53_PAD_EIM_D25__EMI_WEIM_D_25,
125 MX53_PAD_EIM_D26__EMI_WEIM_D_26,
126 MX53_PAD_EIM_D27__EMI_WEIM_D_27,
127 MX53_PAD_EIM_D28__EMI_WEIM_D_28,
128 MX53_PAD_EIM_D29__EMI_WEIM_D_29,
129 MX53_PAD_EIM_D30__EMI_WEIM_D_30,
130 MX53_PAD_EIM_D31__EMI_WEIM_D_31,
131 MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
132 MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
133 MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
134 MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
135 MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
136 MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
137 MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
138 MX53_PAD_EIM_OE__EMI_WEIM_OE,
139 MX53_PAD_EIM_RW__EMI_WEIM_RW,
140 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
142 MX53_PAD_EIM_EB2__I2C2_SCL,
143 MX53_PAD_KEY_ROW3__I2C2_SDA,
146 MX53_PAD_GPIO_3__I2C3_SCL,
147 MX53_PAD_GPIO_16__I2C3_SDA,
150 MX53_PAD_GPIO_17__GPIO7_12,
152 /* MAINBRD_SPDIF_IN */
153 MX53_PAD_KEY_COL3__SPDIF_IN1,
155 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
156 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
157 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
158 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
159 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
160 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
161 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
162 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
163 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
164 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
166 MX53_PAD_DISP0_DAT8__PWM1_PWMO,
167 MX53_PAD_DISP0_DAT9__PWM2_PWMO
170 /* Config CS1 settings for ethernet controller */
171 static void weim_cs_config(void)
174 void __iomem *weim_base, *iomuxc_base;
175 weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
176 iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
178 /* CS1 timings for LAN9220 */
179 writel(0x20001, (weim_base + 0x18));
180 writel(0x0, (weim_base + 0x1C));
181 writel(0x16000202, (weim_base + 0x20));
182 writel(0x00000002, (weim_base + 0x24));
183 writel(0x16002082, (weim_base + 0x28));
184 writel(0x00000000, (weim_base + 0x2C));
185 writel(0x00000000, (weim_base + 0x90));
187 /* specify 64 MB on CS1 and CS0 on GPR1 */
188 reg = readl(iomuxc_base + 0x4);
191 writel(reg, (iomuxc_base + 0x4));
192 iounmap(iomuxc_base);
196 static struct resource ard_smsc911x_resources[] = {
198 .start = MX53_CS1_BASE_ADDR,
199 .end = MX53_CS1_BASE_ADDR + SZ_4K - 1,
200 .flags = IORESOURCE_MEM,
203 .start = gpio_to_irq(ARD_ETHERNET_INT_B),
204 .end = gpio_to_irq(ARD_ETHERNET_INT_B),
205 .flags = IORESOURCE_IRQ,
210 struct smsc911x_platform_config ard_smsc911x_config = {
211 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
212 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
213 .flags = SMSC911X_USE_32BIT,
216 static struct platform_device ard_smsc_lan9220_device = {
219 .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
220 .resource = ard_smsc911x_resources,
223 static iomux_v3_cfg_t mx53_ard_esai_pads[] = {
224 MX53_PAD_FEC_MDIO__ESAI1_SCKR,
225 MX53_PAD_FEC_REF_CLK__ESAI1_FSR,
226 MX53_PAD_FEC_CRS_DV__ESAI1_SCKT,
227 MX53_PAD_FEC_RXD1__ESAI1_FST,
228 MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2,
229 MX53_PAD_GPIO_5__ESAI1_TX2_RX3,
230 MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1,
231 MX53_PAD_GPIO_8__ESAI1_TX5_RX0,
232 MX53_PAD_NANDF_CS2__ESAI1_TX0,
233 MX53_PAD_NANDF_CS3__ESAI1_TX1,
234 MX53_PAD_PATA_DATA4__GPIO2_4,
237 void ard_gpio_activate_esai_ports(void)
239 mxc_iomux_v3_setup_multiple_pads(mx53_ard_esai_pads,
240 ARRAY_SIZE(mx53_ard_esai_pads));
242 gpio_request(ARD_ESAI_INT, "esai-int");
243 gpio_direction_input(ARD_ESAI_INT);
247 static struct imx_esai_platform_data esai_data = {
248 .flags = IMX_ESAI_NET,
251 static struct platform_device mxc_alsa_surround_device = {
252 .name = "imx-cs42888",
255 static struct mxc_audio_platform_data mxc_surround_audio_data = {
260 static int imx53_init_audio(void)
262 ard_gpio_activate_esai_ports();
264 mxc_register_device(&mxc_alsa_surround_device,
265 &mxc_surround_audio_data);
266 imx53_add_imx_esai(0, &esai_data);
271 static int mx53_ard_max7310_setup(struct i2c_client *client,
272 unsigned gpio_base, unsigned ngpio,
275 static int max7310_gpio_value[] = {
276 1, 1, 1, 1, 0, 0, 0, 0,
280 for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) {
281 gpio_request(gpio_base + n, "MAX7310 GPIO Expander");
282 if (max7310_gpio_value[n] < 0)
283 gpio_direction_input(gpio_base + n);
285 gpio_direction_output(gpio_base + n,
286 max7310_gpio_value[n]);
287 /* Export, direction locked down */
288 gpio_export(gpio_base + n, 0);
294 static struct pca953x_platform_data mx53_i2c_max7310_platdata = {
295 .gpio_base = MAX7310_BASE_ADDR,
296 .invert = 0, /* Do not invert */
297 .setup = mx53_ard_max7310_setup,
300 static const struct imxuart_platform_data mx53_ard_uart_data __initconst = {
301 .flags = IMXUART_HAVE_RTSCTS,
304 static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
305 .cd_gpio = ARD_SD1_CD,
306 .wp_gpio = ARD_SD1_WP,
309 static const struct esdhc_platform_data mx53_ard_sd2_data __initconst = {
310 .cd_gpio = ARD_SD2_CD,
311 .wp_gpio = ARD_SD2_WP,
314 static struct imxi2c_platform_data mx53_ard_i2c1_data = {
318 static struct imxi2c_platform_data mx53_ard_i2c2_data = {
322 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
329 static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
331 I2C_BOARD_INFO("max11801", 0x49),
332 .irq = gpio_to_irq(ARD_TS_INT),
337 .platform_data = &mx53_i2c_max7310_platdata,
341 static struct mxc_spdif_platform_data mxc_spdif_data = {
344 .spdif_clk_44100 = 0, /* Souce from CKIH1 for 44.1K */
345 .spdif_clk_48000 = 7, /* Source from CKIH2 for 48k and 32k */
347 .spdif_clk = NULL, /* spdif bus clk */
350 static struct mxc_regulator_platform_data ard_regulator_data = {
354 static int mx53_ard_set_cpu_voltage(u32 cpu_volt)
358 if (cpu_regulator == NULL)
359 cpu_regulator = regulator_get(NULL, gp_reg_id);
360 if (!IS_ERR(cpu_regulator))
361 ret = mx5_set_cpu_voltage(cpu_regulator, cpu_volt);
366 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
367 char **cmdline, struct meminfo *mi)
369 set_cpu_voltage = mx53_ard_set_cpu_voltage;
372 static inline void mx53_ard_init_uart(void)
374 imx53_add_imx_uart(0, NULL);
375 imx53_add_imx_uart(1, &mx53_ard_uart_data);
376 imx53_add_imx_uart(2, &mx53_ard_uart_data);
379 static struct ipuv3_fb_platform_data ard_fb_data[] = {
382 .interface_pix_fmt = IPU_PIX_FMT_RGB666,
383 .mode_str = "LDB-XGA",
389 .interface_pix_fmt = IPU_PIX_FMT_GBR24,
390 .mode_str = "VGA-XGA",
396 static struct imx_ipuv3_platform_data ipu_data = {
400 static struct platform_pwm_backlight_data ard_pwm1_backlight_data = {
402 .max_brightness = 255,
403 .dft_brightness = 128,
404 .pwm_period_ns = 50000,
407 static struct platform_pwm_backlight_data ard_pwm2_backlight_data = {
409 .max_brightness = 255,
410 .dft_brightness = 128,
411 .pwm_period_ns = 50000,
414 static struct fsl_mxc_tve_platform_data tve_data = {
418 static struct fsl_mxc_ldb_platform_data ldb_data = {
425 static void __init mx53_ard_io_init(void)
428 pr_info("MX53 ARD board \n");
429 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
430 gpio_direction_input(ARD_ETHERNET_INT_B);
433 static int __initdata enable_ard_vga = { 0 };
434 static int __init ard_vga_setup(char *__unused)
437 printk(KERN_INFO "Enable MX53 ARD VGA\n");
438 return cpu_is_mx53();
440 __setup("ard-vga", ard_vga_setup);
442 static void __init mx53_ard_board_init(void)
445 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
446 ARRAY_SIZE(mx53_ard_pads));
449 if (enable_ard_vga) {
451 vga = MX53_PAD_EIM_OE__IPU_DI1_PIN7;
452 mxc_iomux_v3_setup_pad(vga);
453 vga = MX53_PAD_EIM_RW__IPU_DI1_PIN8;
454 mxc_iomux_v3_setup_pad(vga);
457 gp_reg_id = ard_regulator_data.cpu_reg_id;
458 lp_reg_id = ard_regulator_data.vcc_reg_id;
460 mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
461 clk_put(mxc_spdif_data.spdif_core_clk);
462 mx53_ard_init_uart();
464 imx53_add_ipuv3(0, &ipu_data);
465 for (i = 0; i < ARRAY_SIZE(ard_fb_data); i++)
466 imx53_add_ipuv3fb(i, &ard_fb_data[i]);
469 imx53_add_ldb(&ldb_data);
470 imx53_add_tve(&tve_data);
471 imx53_add_v4l2_output(0);
473 imx53_add_mxc_pwm(0);
474 imx53_add_mxc_pwm_backlight(0, &ard_pwm1_backlight_data);
475 imx53_add_mxc_pwm(1);
476 imx53_add_mxc_pwm_backlight(1, &ard_pwm2_backlight_data);
479 imx53_add_imx2_wdt(0, NULL);
480 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
481 imx53_add_sdhci_esdhc_imx(1, &mx53_ard_sd2_data);
482 mxc_register_device(&imx_ahci_device_hwmon, NULL);
486 mxc_register_device(&ard_smsc_lan9220_device, &ard_smsc911x_config);
487 imx53_add_imx_i2c(1, &mx53_ard_i2c1_data);
488 imx53_add_imx_i2c(2, &mx53_ard_i2c2_data);
490 imx53_add_spdif(&mxc_spdif_data);
491 imx53_add_spdif_dai();
492 imx53_add_spdif_audio_device();
494 i2c_register_board_info(1, mxc_i2c1_board_info,
495 ARRAY_SIZE(mxc_i2c1_board_info));
496 i2c_register_board_info(2, mxc_i2c2_board_info,
497 ARRAY_SIZE(mxc_i2c2_board_info));
501 /* this call required to release SCC RAM partition held by ROM
502 * during boot, even if SCC2 driver is not part of the image
504 imx53_add_mxc_scc2();
507 static void __init mx53_ard_timer_init(void)
509 mx53_clocks_init(32768, 24000000, 22579200, 0);
512 static struct sys_timer mx53_ard_timer = {
513 .init = mx53_ard_timer_init,
516 MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
517 .fixup = fixup_mxc_board,
518 .map_io = mx53_map_io,
519 .init_early = imx53_init_early,
520 .init_irq = mx53_init_irq,
521 .timer = &mx53_ard_timer,
522 .init_machine = mx53_ard_board_init,