2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/fec.h>
24 #include <linux/delay.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/gpio.h>
27 #include <linux/mxcfb.h>
28 #include <linux/ipu.h>
29 #include <linux/pwm_backlight.h>
30 #include <linux/ahci_platform.h>
31 #include <linux/gpio_keys.h>
33 #include <mach/common.h>
34 #include <mach/hardware.h>
35 #include <mach/imx-uart.h>
36 #include <mach/iomux-mx53.h>
37 #include <mach/ipu-v3.h>
38 #include <mach/mxc_dvfs.h>
39 #include <mach/ahci_sata.h>
41 #include <asm/mach-types.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
44 #include <asm/setup.h>
47 #include "devices-imx53.h"
51 #define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
52 #define LOCO_HEADPHONE_DET IMX_GPIO_NR(2, 5)
53 #define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
54 #define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
55 #define MX53_LOCO_SD3_CD IMX_GPIO_NR(3, 11)
56 #define MX53_LOCO_SD3_WP IMX_GPIO_NR(3, 12)
57 #define MX53_LOCO_SD1_CD IMX_GPIO_NR(3, 13)
58 #define LOCO_DISP0_PWR IMX_GPIO_NR(3, 24)
59 #define LOCO_DISP0_DET_INT IMX_GPIO_NR(3, 31)
60 #define LOCO_DISP0_RESET IMX_GPIO_NR(5, 0)
61 #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
62 #define LOCO_USBH1_VBUS IMX_GPIO_NR(7, 8)
64 static struct clk *sata_clk, *sata_ref_clk;
66 extern void __iomem *arm_plat_base;
67 extern void __iomem *gpc_base;
68 extern void __iomem *ccm_base;
69 extern void __iomem *imx_otg_base;
70 extern char *lp_reg_id;
71 extern int (*set_cpu_voltage)(u32 volt);
72 extern int mx5_set_cpu_voltage(struct regulator *gp_reg, u32 cpu_volt);
74 extern int __init mx53_loco_init_da9052(void);
76 static struct regulator *cpu_regulator;
77 static char *gp_reg_id;
79 static iomux_v3_cfg_t mx53_loco_pads[] = {
81 MX53_PAD_FEC_MDC__FEC_MDC,
82 MX53_PAD_FEC_MDIO__FEC_MDIO,
83 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
84 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
85 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
86 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
87 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
88 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
89 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
90 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
92 MX53_PAD_PATA_DA_0__GPIO7_6,
94 MX53_PAD_PATA_DATA4__GPIO2_4,
96 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
97 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
98 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
99 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
101 MX53_PAD_KEY_COL3__I2C2_SCL,
102 MX53_PAD_KEY_ROW3__I2C2_SDA,
104 MX53_PAD_SD1_CMD__ESDHC1_CMD,
105 MX53_PAD_SD1_CLK__ESDHC1_CLK,
106 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
107 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
108 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
109 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
111 MX53_PAD_EIM_DA13__GPIO3_13,
113 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
114 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
115 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
116 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
117 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
118 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
119 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
120 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
121 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
122 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
124 MX53_PAD_EIM_DA11__GPIO3_11,
126 MX53_PAD_EIM_DA12__GPIO3_12,
128 MX53_PAD_EIM_OE__IPU_DI1_PIN7,
129 MX53_PAD_EIM_RW__IPU_DI1_PIN8,
131 MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
132 MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
133 MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
134 MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
136 MX53_PAD_EIM_D24__GPIO3_24,
138 MX53_PAD_EIM_D31__GPIO3_31,
140 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
141 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
142 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
143 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
144 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
145 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
146 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
147 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
148 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
149 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
151 MX53_PAD_CSI0_DAT8__I2C1_SDA,
152 MX53_PAD_CSI0_DAT9__I2C1_SCL,
154 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
155 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
157 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
158 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
159 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
160 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
161 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
162 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
163 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
164 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
165 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
166 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
167 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
169 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
170 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
171 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
172 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
173 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
174 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
175 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
176 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
177 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
178 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
179 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
180 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
181 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
182 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
183 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
184 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
185 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
186 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
187 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
188 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
189 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
190 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
191 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
192 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
193 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
194 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
195 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
196 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
198 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
200 MX53_PAD_GPIO_1__PWM2_PWMO,
202 MX53_PAD_GPIO_7__SPDIF_PLOCK,
203 MX53_PAD_GPIO_17__SPDIF_OUT1,
205 MX53_PAD_PATA_DA_1__GPIO7_7,
206 MX53_PAD_PATA_DA_2__GPIO7_8,
207 MX53_PAD_PATA_DATA5__GPIO2_5,
208 MX53_PAD_PATA_DATA6__GPIO2_6,
209 MX53_PAD_PATA_DATA14__GPIO2_14,
210 MX53_PAD_PATA_DATA15__GPIO2_15,
211 MX53_PAD_PATA_INTRQ__GPIO7_2,
212 MX53_PAD_EIM_WAIT__GPIO5_0,
213 MX53_PAD_NANDF_WP_B__GPIO6_9,
214 MX53_PAD_NANDF_RB0__GPIO6_10,
215 MX53_PAD_NANDF_CS1__GPIO6_14,
216 MX53_PAD_NANDF_CS2__GPIO6_15,
217 MX53_PAD_NANDF_CS3__GPIO6_16,
218 MX53_PAD_GPIO_5__GPIO1_5,
219 MX53_PAD_GPIO_16__GPIO7_11,
220 MX53_PAD_GPIO_8__GPIO1_8,
223 #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
228 .active_low = act_low, \
229 .desc = "btn " descr, \
233 static const struct gpio_keys_button loco_buttons[] __initconst = {
234 GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 1),
235 GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
236 GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
239 static const struct gpio_keys_platform_data loco_button_data __initconst = {
240 .buttons = (struct gpio_keys_button *)loco_buttons,
241 .nbuttons = ARRAY_SIZE(loco_buttons),
244 static inline void mx53_loco_fec_reset(void)
249 ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
251 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
254 gpio_direction_output(LOCO_FEC_PHY_RST, 0);
256 gpio_set_value(LOCO_FEC_PHY_RST, 1);
259 static struct fec_platform_data mx53_loco_fec_data = {
260 .phy = PHY_INTERFACE_MODE_RMII,
263 static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
267 static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
274 static void sii902x_hdmi_reset(void)
276 gpio_set_value(LOCO_DISP0_RESET, 0);
278 gpio_set_value(LOCO_DISP0_RESET, 1);
282 static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = {
285 .reset = sii902x_hdmi_reset,
288 static void loco_suspend_enter(void)
290 /* da9053 suspend preparation */
293 static void loco_suspend_exit(void)
295 /*clear the EMPGC0/1 bits */
296 __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
297 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
298 /* da9053 resmue resore */
301 static struct mxc_pm_platform_data loco_pm_data = {
302 .suspend_enter = loco_suspend_enter,
303 .suspend_exit = loco_suspend_exit,
306 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
314 .irq = gpio_to_irq(LOCO_DISP0_DET_INT),
315 .platform_data = &sii902x_hdmi_data,
319 static struct fsl_mxc_lcd_platform_data lcdif_data = {
322 .default_ifmt = IPU_PIX_FMT_RGB565,
325 static struct ipuv3_fb_platform_data loco_fb_data[] = {
328 .interface_pix_fmt = IPU_PIX_FMT_GBR24,
329 .mode_str = "VGA-XGA",
334 .interface_pix_fmt = IPU_PIX_FMT_RGB565,
335 .mode_str = "CLAA-WVGA",
341 static struct imx_ipuv3_platform_data ipu_data = {
345 static struct platform_pwm_backlight_data loco_pwm_backlight_data = {
347 .max_brightness = 255,
348 .dft_brightness = 128,
349 .pwm_period_ns = 50000,
352 static struct fsl_mxc_tve_platform_data tve_data = {
353 .dac_reg = "DA9052_LDO7",
356 static struct mxc_dvfs_platform_data loco_dvfs_core_data = {
357 .reg_id = "cpu_vddgp",
358 .clk1_id = "cpu_clk",
359 .clk2_id = "gpc_dvfs_clk",
360 .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
361 .gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
362 .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
363 .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
364 .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
365 .prediv_mask = 0x1F800,
368 .div3ck_mask = 0xE0000000,
380 static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
381 .cd_gpio = MX53_LOCO_SD1_CD,
384 static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
385 .cd_gpio = MX53_LOCO_SD3_CD,
386 .wp_gpio = MX53_LOCO_SD3_WP,
389 static void mx53_loco_usbh1_vbus(bool on)
392 gpio_set_value(LOCO_USBH1_VBUS, 1);
394 gpio_set_value(LOCO_USBH1_VBUS, 0);
397 static void __init mx53_loco_io_init(void)
401 arm_plat_base = MX53_IO_ADDRESS(MX53_ARM_BASE_ADDR);
402 gpc_base = MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR);
403 ccm_base = MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR);
404 imx_otg_base = MX53_IO_ADDRESS(MX53_OTG_BASE_ADDR);
406 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
407 ARRAY_SIZE(mx53_loco_pads));
409 /* Sii902x HDMI controller */
410 ret = gpio_request(LOCO_DISP0_RESET, "disp0-reset");
412 printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_RESET: %d\n", ret);
415 gpio_direction_output(LOCO_DISP0_RESET, 0);
417 ret = gpio_request(LOCO_DISP0_DET_INT, "disp0-detect");
419 printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_DET_INT: %d\n", ret);
422 gpio_direction_input(LOCO_DISP0_DET_INT);
424 /* enable disp0 power */
425 ret = gpio_request(LOCO_DISP0_PWR, "disp0-power-en");
427 printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_PWR: %d\n", ret);
430 gpio_direction_output(LOCO_DISP0_PWR, 1);
433 ret = gpio_request(LOCO_USBH1_VBUS, "usbh1-vbus");
435 printk(KERN_ERR"failed to get GPIO LOCO_USBH1_VBUS: %d\n", ret);
438 gpio_direction_output(LOCO_USBH1_VBUS, 0);
441 /* HW Initialization, if return 0, initialization is successful. */
442 static int mx53_loco_sata_init(struct device *dev, void __iomem *addr)
448 sata_clk = clk_get(dev, "imx_sata_clk");
449 if (IS_ERR(sata_clk)) {
450 dev_err(dev, "no sata clock.\n");
451 return PTR_ERR(sata_clk);
453 ret = clk_enable(sata_clk);
455 dev_err(dev, "can't enable sata clock.\n");
459 sata_ref_clk = clk_get(NULL, "usb_phy1_clk");
460 if (IS_ERR(sata_ref_clk)) {
461 dev_err(dev, "no sata ref clock.\n");
462 ret = PTR_ERR(sata_ref_clk);
463 goto release_sata_clk;
465 ret = clk_enable(sata_ref_clk);
467 dev_err(dev, "can't enable sata ref clock.\n");
468 goto put_sata_ref_clk;
471 /* Get the AHB clock rate, and configure the TIMER1MS reg later */
472 clk = clk_get(NULL, "ahb_clk");
474 dev_err(dev, "no ahb clock.\n");
476 goto release_sata_ref_clk;
478 tmpdata = clk_get_rate(clk) / 1000;
481 sata_init(addr, tmpdata);
485 release_sata_ref_clk:
486 clk_disable(sata_ref_clk);
488 clk_put(sata_ref_clk);
490 clk_disable(sata_clk);
497 static void mx53_loco_sata_exit(struct device *dev)
499 clk_disable(sata_ref_clk);
500 clk_put(sata_ref_clk);
502 clk_disable(sata_clk);
506 static struct ahci_platform_data mx53_loco_sata_data = {
507 .init = mx53_loco_sata_init,
508 .exit = mx53_loco_sata_exit,
511 static struct mxc_audio_platform_data loco_audio_data;
513 static int loco_sgtl5000_init(void)
515 struct clk *ssi_ext1;
518 ssi_ext1 = clk_get(NULL, "ssi_ext1_clk");
519 if (IS_ERR(ssi_ext1)) {
522 rate = clk_round_rate(ssi_ext1, 24000000);
523 if (rate < 8000000 || rate > 27000000) {
524 printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n",
530 loco_audio_data.sysclk = rate;
531 clk_set_rate(ssi_ext1, rate);
532 clk_enable(ssi_ext1);
537 static struct imx_ssi_platform_data loco_ssi_pdata = {
538 .flags = IMX_SSI_DMA | IMX_SSI_SYN,
541 static struct mxc_audio_platform_data loco_audio_data = {
545 .init = loco_sgtl5000_init,
546 .hp_gpio = LOCO_HEADPHONE_DET,
550 static struct platform_device loco_audio_device = {
551 .name = "imx-sgtl5000",
554 static void mxc_iim_enable_fuse(void)
559 /* enable fuse blown */
560 reg = readl(ccm_base + 0x64);
562 writel(reg, ccm_base + 0x64);
565 static void mxc_iim_disable_fuse(void)
570 /* enable fuse blown */
571 reg = readl(ccm_base + 0x64);
573 writel(reg, ccm_base + 0x64);
576 static struct mxc_iim_platform_data iim_data = {
577 .bank_start = MXC_IIM_MX53_BANK_START_ADDR,
578 .bank_end = MXC_IIM_MX53_BANK_END_ADDR,
579 .enable_fuse = mxc_iim_enable_fuse,
580 .disable_fuse = mxc_iim_disable_fuse,
583 static struct mxc_gpu_platform_data gpu_data __initdata;
585 static struct fsl_mxc_ldb_platform_data ldb_data = {
592 static struct mxc_regulator_platform_data loco_regulator_data = {
593 .cpu_reg_id = "cpu_vddgp",
596 static int mx53_loco_set_cpu_voltage(u32 cpu_volt)
600 if (cpu_regulator == NULL)
601 cpu_regulator = regulator_get(NULL, gp_reg_id);
602 if (!IS_ERR(cpu_regulator))
603 ret = mx5_set_cpu_voltage(cpu_regulator, cpu_volt);
607 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
608 char **cmdline, struct meminfo *mi)
611 struct tag *mem_tag = 0;
612 int total_mem = SZ_1G;
614 int gpu_mem = SZ_128M;
618 set_cpu_voltage = mx53_loco_set_cpu_voltage;
620 for_each_tag(mem_tag, tags) {
621 if (mem_tag->hdr.tag == ATAG_MEM) {
622 total_mem = mem_tag->u.mem.size;
623 left_mem = total_mem - gpu_mem - fb_mem;
628 for_each_tag(t, tags) {
629 if (t->hdr.tag == ATAG_CMDLINE) {
630 str = t->u.cmdline.cmdline;
631 str = strstr(str, "mem=");
634 left_mem = memparse(str, &str);
635 if (left_mem == 0 || left_mem > total_mem)
636 left_mem = total_mem - gpu_mem - fb_mem;
639 str = t->u.cmdline.cmdline;
640 str = strstr(str, "gpu_memory=");
643 gpu_mem = memparse(str, &str);
651 fb_mem = total_mem - left_mem - gpu_mem;
653 gpu_mem = total_mem - left_mem;
656 mem_tag->u.mem.size = left_mem;
658 /* reserve memory for gpu */
659 gpu_data.reserved_mem_base =
660 mem_tag->u.mem.start + left_mem;
661 gpu_data.reserved_mem_size = gpu_mem;
663 /* reserver memory for fb */
664 loco_fb_data[0].res_base = gpu_data.reserved_mem_base
665 + gpu_data.reserved_mem_size;
666 loco_fb_data[0].res_size = fb_mem;
670 static struct mxc_spdif_platform_data mxc_spdif_data = {
673 .spdif_clk_44100 = -1, /* No source for 44.1K */
674 /* Source from CCM spdif_clk (24M) for 48k and 32k
675 * It's not accurate: for 48Khz it is actually 46875Hz (2.3% off)
677 .spdif_clk_48000 = 1,
679 .spdif_clk = NULL, /* spdif bus clk */
682 static void __init mx53_loco_board_init(void)
687 gp_reg_id = loco_regulator_data.cpu_reg_id;
688 lp_reg_id = loco_regulator_data.vcc_reg_id;
690 imx53_add_imx_uart(0, NULL);
691 mx53_loco_fec_reset();
692 imx53_add_fec(&mx53_loco_fec_data);
694 mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
695 clk_put(mxc_spdif_data.spdif_core_clk);
697 mxc_register_device(&mxc_pm_device, &loco_pm_data);
699 imx53_add_ipuv3(0, &ipu_data);
701 for (i = 0; i < ARRAY_SIZE(loco_fb_data); i++)
702 imx53_add_ipuv3fb(i, &loco_fb_data[i]);
705 imx53_add_lcdif(&lcdif_data);
706 imx53_add_ldb(&ldb_data);
707 imx53_add_tve(&tve_data);
708 imx53_add_v4l2_output(0);
710 imx53_add_mxc_pwm(1);
711 imx53_add_mxc_pwm_backlight(0, &loco_pwm_backlight_data);
713 imx53_add_imx2_wdt(0, NULL);
715 imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
716 imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
718 mx53_loco_init_da9052();
719 i2c_register_board_info(0, mxc_i2c0_board_info,
720 ARRAY_SIZE(mxc_i2c0_board_info));
721 i2c_register_board_info(1, mxc_i2c1_board_info,
722 ARRAY_SIZE(mxc_i2c1_board_info));
724 imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
725 imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
726 imx53_add_ahci(0, &mx53_loco_sata_data);
727 mxc_register_device(&imx_ahci_device_hwmon, NULL);
728 imx53_add_iim(&iim_data);
732 mx5_set_host1_vbus_func(mx53_loco_usbh1_vbus);
735 mxc_register_device(&loco_audio_device, &loco_audio_data);
736 imx53_add_imx_ssi(1, &loco_ssi_pdata);
738 imx53_add_spdif(&mxc_spdif_data);
739 imx53_add_spdif_dai();
740 imx53_add_spdif_audio_device();
743 if (mx53_revision() >= IMX_CHIP_REVISION_2_0)
744 gpu_data.z160_revision = 1;
746 gpu_data.z160_revision = 0;
747 imx53_add_mxc_gpu(&gpu_data);
748 imx_add_gpio_keys(&loco_button_data);
750 /* this call required to release SCC RAM partition held by ROM
751 * during boot, even if SCC2 driver is not part of the image
753 imx53_add_mxc_scc2();
754 imx53_add_dvfs_core(&loco_dvfs_core_data);
758 static void __init mx53_loco_timer_init(void)
760 mx53_clocks_init(32768, 24000000, 0, 0);
763 static struct sys_timer mx53_loco_timer = {
764 .init = mx53_loco_timer_init,
767 MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
768 .fixup = fixup_mxc_board,
769 .map_io = mx53_map_io,
770 .init_early = imx53_init_early,
771 .init_irq = mx53_init_irq,
772 .timer = &mx53_loco_timer,
773 .init_machine = mx53_loco_board_init,