arch/arm/mach-omap2/cclock3xxx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2011 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
   9  * With many device clock fixes by Kevin Hilman and Jouni Högander
  10  * DPLL bypass clock support added by Roman Tereshonkov
  11  *
  12  */
  13
  14 /*
  15  * Virtual clocks are introduced as convenient tools.
  16  * They are sources for other clocks and not supposed
  17  * to be requested from drivers directly.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22 #include <linux/clk-private.h>
  23 #include <linux/list.h>
  24 #include <linux/io.h>
  25
  26 #include "soc.h"
  27 #include "iomap.h"
  28 #include "clock.h"
  29 #include "clock3xxx.h"
  30 #include "clock34xx.h"
  31 #include "clock36xx.h"
  32 #include "clock3517.h"
  33 #include "cm3xxx.h"
  34 #include "cm-regbits-34xx.h"
  35 #include "prm3xxx.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "control.h"
  38
  39 /*
  40  * clocks
  41  */
  42
  43 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  44
  45 /* Maximum DPLL multiplier, divider values for OMAP3 */
  46 #define OMAP3_MAX_DPLL_MULT             2047
  47 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  48 #define OMAP3_MAX_DPLL_DIV              128
  49
  50 DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
  51
  52 DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
  53
  54 DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  55
  56 DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
  57
  58 DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
  59
  60 DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  61
  62 DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
  63
  64 DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
  65
  66 DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
  67
  68 DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
  69
  70 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  71
  72 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  73
  74 DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
  75
  76 static const char *osc_sys_ck_parent_names[] = {
  77         "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
  78         "virt_38_4m_ck", "virt_16_8m_ck",
  79 };
  80
  81 DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
  82                OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
  83                OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
  84
  85 DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
  86                    OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
  87                    OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
  88
  89 static struct dpll_data dpll3_dd = {
  90         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  91         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
  92         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
  93         .clk_bypass     = &sys_ck,
  94         .clk_ref        = &sys_ck,
  95         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
  96         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  97         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
  98         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
  99         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 100         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 101         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 102         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 103         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 104         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 105         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 106         .min_divider    = 1,
 107         .max_divider    = OMAP3_MAX_DPLL_DIV,
 108 };
 109
 110 static struct clk dpll3_ck;
 111
 112 static const char *dpll3_ck_parent_names[] = {
 113         "sys_ck",
 114 };
 115
 116 static const struct clk_ops dpll3_ck_ops = {
 117         .init           = &omap2_init_clk_clkdm,
 118         .get_parent     = &omap2_init_dpll_parent,
 119         .recalc_rate    = &omap3_dpll_recalc,
 120         .round_rate     = &omap2_dpll_round_rate,
 121 };
 122
 123 static struct clk_hw_omap dpll3_ck_hw = {
 124         .hw = {
 125                 .clk = &dpll3_ck,
 126         },
 127         .ops            = &clkhwops_omap3_dpll,
 128         .dpll_data      = &dpll3_dd,
 129         .clkdm_name     = "dpll3_clkdm",
 130 };
 131
 132 DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
 133
 134 DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
 135                    OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 136                    OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
 137                    OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
 138                    CLK_DIVIDER_ONE_BASED, NULL);
 139
 140 static struct clk core_ck;
 141
 142 static const char *core_ck_parent_names[] = {
 143         "dpll3_m2_ck",
 144 };
 145
 146 static const struct clk_ops core_ck_ops = {};
 147
 148 DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
 149 DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
 150
 151 DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
 152                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 153                    OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
 154                    CLK_DIVIDER_ONE_BASED, NULL);
 155
 156 DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
 157                    OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 158                    OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
 159                    CLK_DIVIDER_ONE_BASED, NULL);
 160
 161 static struct clk security_l4_ick2;
 162
 163 static const char *security_l4_ick2_parent_names[] = {
 164         "l4_ick",
 165 };
 166
 167 DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
 168 DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
 169
 170 static struct clk aes1_ick;
 171
 172 static const char *aes1_ick_parent_names[] = {
 173         "security_l4_ick2",
 174 };
 175
 176 static const struct clk_ops aes1_ick_ops = {
 177         .enable         = &omap2_dflt_clk_enable,
 178         .disable        = &omap2_dflt_clk_disable,
 179         .is_enabled     = &omap2_dflt_clk_is_enabled,
 180 };
 181
 182 static struct clk_hw_omap aes1_ick_hw = {
 183         .hw = {
 184                 .clk = &aes1_ick,
 185         },
 186         .ops            = &clkhwops_iclk_wait,
 187         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 188         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
 189 };
 190
 191 DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
 192
 193 static struct clk core_l4_ick;
 194
 195 static const struct clk_ops core_l4_ick_ops = {
 196         .init           = &omap2_init_clk_clkdm,
 197 };
 198
 199 DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
 200 DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
 201
 202 static struct clk aes2_ick;
 203
 204 static const char *aes2_ick_parent_names[] = {
 205         "core_l4_ick",
 206 };
 207
 208 static const struct clk_ops aes2_ick_ops = {
 209         .init           = &omap2_init_clk_clkdm,
 210         .enable         = &omap2_dflt_clk_enable,
 211         .disable        = &omap2_dflt_clk_disable,
 212         .is_enabled     = &omap2_dflt_clk_is_enabled,
 213 };
 214
 215 static struct clk_hw_omap aes2_ick_hw = {
 216         .hw = {
 217                 .clk = &aes2_ick,
 218         },
 219         .ops            = &clkhwops_iclk_wait,
 220         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 221         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
 222         .clkdm_name     = "core_l4_clkdm",
 223 };
 224
 225 DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
 226
 227 static struct clk dpll1_fck;
 228
 229 static struct dpll_data dpll1_dd = {
 230         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 231         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 232         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 233         .clk_bypass     = &dpll1_fck,
 234         .clk_ref        = &sys_ck,
 235         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 236         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 237         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 238         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 239         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 240         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 241         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 242         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 243         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 244         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 245         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 246         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 247         .min_divider    = 1,
 248         .max_divider    = OMAP3_MAX_DPLL_DIV,
 249 };
 250
 251 static struct clk dpll1_ck;
 252
 253 static const struct clk_ops dpll1_ck_ops = {
 254         .init           = &omap2_init_clk_clkdm,
 255         .enable         = &omap3_noncore_dpll_enable,
 256         .disable        = &omap3_noncore_dpll_disable,
 257         .get_parent     = &omap2_init_dpll_parent,
 258         .recalc_rate    = &omap3_dpll_recalc,
 259         .set_rate       = &omap3_noncore_dpll_set_rate,
 260         .round_rate     = &omap2_dpll_round_rate,
 261 };
 262
 263 static struct clk_hw_omap dpll1_ck_hw = {
 264         .hw = {
 265                 .clk = &dpll1_ck,
 266         },
 267         .ops            = &clkhwops_omap3_dpll,
 268         .dpll_data      = &dpll1_dd,
 269         .clkdm_name     = "dpll1_clkdm",
 270 };
 271
 272 DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 273
 274 DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
 275
 276 DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
 277                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 278                    OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
 279                    OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
 280                    CLK_DIVIDER_ONE_BASED, NULL);
 281
 282 static struct clk mpu_ck;
 283
 284 static const char *mpu_ck_parent_names[] = {
 285         "dpll1_x2m2_ck",
 286 };
 287
 288 DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
 289 DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
 290
 291 DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
 292                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 293                    OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
 294                    0x0, NULL);
 295
 296 static struct clk cam_ick;
 297
 298 static struct clk_hw_omap cam_ick_hw = {
 299         .hw = {
 300                 .clk = &cam_ick,
 301         },
 302         .ops            = &clkhwops_iclk,
 303         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
 304         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
 305         .clkdm_name     = "cam_clkdm",
 306 };
 307
 308 DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
 309
 310 /* DPLL4 */
 311 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 312 /* Type: DPLL */
 313 static struct dpll_data dpll4_dd;
 314
 315 static struct dpll_data dpll4_dd_34xx __initdata = {
 316         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 317         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 318         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 319         .clk_bypass     = &sys_ck,
 320         .clk_ref        = &sys_ck,
 321         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 322         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 323         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 324         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 325         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 326         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 327         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 328         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 329         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 330         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 331         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 332         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 333         .min_divider    = 1,
 334         .max_divider    = OMAP3_MAX_DPLL_DIV,
 335 };
 336
 337 static struct dpll_data dpll4_dd_3630 __initdata = {
 338         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 339         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 340         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 341         .clk_bypass     = &sys_ck,
 342         .clk_ref        = &sys_ck,
 343         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 344         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 345         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 346         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 347         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 348         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 349         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 350         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 351         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 352         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 353         .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 354         .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 355         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 356         .min_divider    = 1,
 357         .max_divider    = OMAP3_MAX_DPLL_DIV,
 358         .flags          = DPLL_J_TYPE
 359 };
 360
 361 static struct clk dpll4_ck;
 362
 363 static const struct clk_ops dpll4_ck_ops = {
 364         .init           = &omap2_init_clk_clkdm,
 365         .enable         = &omap3_noncore_dpll_enable,
 366         .disable        = &omap3_noncore_dpll_disable,
 367         .get_parent     = &omap2_init_dpll_parent,
 368         .recalc_rate    = &omap3_dpll_recalc,
 369         .set_rate       = &omap3_dpll4_set_rate,
 370         .round_rate     = &omap2_dpll_round_rate,
 371 };
 372
 373 static struct clk_hw_omap dpll4_ck_hw = {
 374         .hw = {
 375                 .clk = &dpll4_ck,
 376         },
 377         .dpll_data      = &dpll4_dd,
 378         .ops            = &clkhwops_omap3_dpll,
 379         .clkdm_name     = "dpll4_clkdm",
 380 };
 381
 382 DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
 383
 384 DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
 385                    OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 386                    OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
 387                    CLK_DIVIDER_ONE_BASED, NULL);
 388
 389 static struct clk dpll4_m5x2_ck;
 390
 391 static const char *dpll4_m5x2_ck_parent_names[] = {
 392         "dpll4_m5_ck",
 393 };
 394
 395 static const struct clk_ops dpll4_m5x2_ck_ops = {
 396         .init           = &omap2_init_clk_clkdm,
 397         .enable         = &omap2_dflt_clk_enable,
 398         .disable        = &omap2_dflt_clk_disable,
 399         .is_enabled     = &omap2_dflt_clk_is_enabled,
 400         .recalc_rate    = &omap3_clkoutx2_recalc,
 401 };
 402
 403 static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
 404         .init           = &omap2_init_clk_clkdm,
 405         .enable         = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
 406         .disable        = &omap2_dflt_clk_disable,
 407         .recalc_rate    = &omap3_clkoutx2_recalc,
 408 };
 409
 410 static struct clk_hw_omap dpll4_m5x2_ck_hw = {
 411         .hw = {
 412                 .clk = &dpll4_m5x2_ck,
 413         },
 414         .ops            = &clkhwops_wait,
 415         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 416         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 417         .flags          = INVERT_ENABLE,
 418         .clkdm_name     = "dpll4_clkdm",
 419 };
 420
 421 DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
 422
 423 static struct clk dpll4_m5x2_ck_3630 = {
 424         .name           = "dpll4_m5x2_ck",
 425         .hw             = &dpll4_m5x2_ck_hw.hw,
 426         .parent_names   = dpll4_m5x2_ck_parent_names,
 427         .num_parents    = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
 428         .ops            = &dpll4_m5x2_ck_3630_ops,
 429 };
 430
 431 static struct clk cam_mclk;
 432
 433 static const char *cam_mclk_parent_names[] = {
 434         "dpll4_m5x2_ck",
 435 };
 436
 437 static struct clk_hw_omap cam_mclk_hw = {
 438         .hw = {
 439                 .clk = &cam_mclk,
 440         },
 441         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 442         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
 443         .clkdm_name     = "cam_clkdm",
 444 };
 445
 446 DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);
 447
 448 static const struct clksel_rate clkout2_src_core_rates[] = {
 449         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 450         { .div = 0 }
 451 };
 452
 453 static const struct clksel_rate clkout2_src_sys_rates[] = {
 454         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 455         { .div = 0 }
 456 };
 457
 458 static const struct clksel_rate clkout2_src_96m_rates[] = {
 459         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 460         { .div = 0 }
 461 };
 462
 463 DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
 464                    OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 465                    OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
 466                    CLK_DIVIDER_ONE_BASED, NULL);
 467
 468 static struct clk dpll4_m2x2_ck;
 469
 470 static const char *dpll4_m2x2_ck_parent_names[] = {
 471         "dpll4_m2_ck",
 472 };
 473
 474 static struct clk_hw_omap dpll4_m2x2_ck_hw = {
 475         .hw = {
 476                 .clk = &dpll4_m2x2_ck,
 477         },
 478         .ops            = &clkhwops_wait,
 479         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 480         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 481         .flags          = INVERT_ENABLE,
 482         .clkdm_name     = "dpll4_clkdm",
 483 };
 484
 485 DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
 486
 487 static struct clk dpll4_m2x2_ck_3630 = {
 488         .name           = "dpll4_m2x2_ck",
 489         .hw             = &dpll4_m2x2_ck_hw.hw,
 490         .parent_names   = dpll4_m2x2_ck_parent_names,
 491         .num_parents    = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
 492         .ops            = &dpll4_m5x2_ck_3630_ops,
 493 };
 494
 495 static struct clk omap_96m_alwon_fck;
 496
 497 static const char *omap_96m_alwon_fck_parent_names[] = {
 498         "dpll4_m2x2_ck",
 499 };
 500
 501 DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
 502 DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
 503                   core_ck_ops);
 504
 505 static struct clk cm_96m_fck;
 506
 507 static const char *cm_96m_fck_parent_names[] = {
 508         "omap_96m_alwon_fck",
 509 };
 510
 511 DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
 512 DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
 513
 514 static const struct clksel_rate clkout2_src_54m_rates[] = {
 515         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 516         { .div = 0 }
 517 };
 518
 519 DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
 520                    OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 521                    OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
 522                    CLK_DIVIDER_ONE_BASED, NULL);
 523
 524 static struct clk dpll4_m3x2_ck;
 525
 526 static const char *dpll4_m3x2_ck_parent_names[] = {
 527         "dpll4_m3_ck",
 528 };
 529
 530 static struct clk_hw_omap dpll4_m3x2_ck_hw = {
 531         .hw = {
 532                 .clk = &dpll4_m3x2_ck,
 533         },
 534         .ops            = &clkhwops_wait,
 535         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 536         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 537         .flags          = INVERT_ENABLE,
 538         .clkdm_name     = "dpll4_clkdm",
 539 };
 540
 541 DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
 542
 543 static struct clk dpll4_m3x2_ck_3630 = {
 544         .name           = "dpll4_m3x2_ck",
 545         .hw             = &dpll4_m3x2_ck_hw.hw,
 546         .parent_names   = dpll4_m3x2_ck_parent_names,
 547         .num_parents    = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
 548         .ops            = &dpll4_m5x2_ck_3630_ops,
 549 };
 550
 551 static const char *omap_54m_fck_parent_names[] = {
 552         "dpll4_m3x2_ck", "sys_altclk",
 553 };
 554
 555 DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
 556                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
 557                OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
 558
 559 static const struct clksel clkout2_src_clksel[] = {
 560         { .parent = &core_ck, .rates = clkout2_src_core_rates },
 561         { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
 562         { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
 563         { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
 564         { .parent = NULL },
 565 };
 566
 567 static const char *clkout2_src_ck_parent_names[] = {
 568         "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
 569 };
 570
 571 static const struct clk_ops clkout2_src_ck_ops = {
 572         .init           = &omap2_init_clk_clkdm,
 573         .enable         = &omap2_dflt_clk_enable,
 574         .disable        = &omap2_dflt_clk_disable,
 575         .is_enabled     = &omap2_dflt_clk_is_enabled,
 576         .recalc_rate    = &omap2_clksel_recalc,
 577         .get_parent     = &omap2_clksel_find_parent_index,
 578         .set_parent     = &omap2_clksel_set_parent,
 579 };
 580
 581 DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
 582                          clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
 583                          OMAP3430_CLKOUT2SOURCE_MASK,
 584                          OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
 585                          NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
 586
 587 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 588         { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 589         { .div = 0 }
 590 };
 591
 592 static const struct clksel_rate omap_48m_alt_rates[] = {
 593         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 594         { .div = 0 }
 595 };
 596
 597 static const struct clksel omap_48m_clksel[] = {
 598         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 599         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 600         { .parent = NULL },
 601 };
 602
 603 static const char *omap_48m_fck_parent_names[] = {
 604         "cm_96m_fck", "sys_altclk",
 605 };
 606
 607 static struct clk omap_48m_fck;
 608
 609 static const struct clk_ops omap_48m_fck_ops = {
 610         .recalc_rate    = &omap2_clksel_recalc,
 611         .get_parent     = &omap2_clksel_find_parent_index,
 612         .set_parent     = &omap2_clksel_set_parent,
 613 };
 614
 615 static struct clk_hw_omap omap_48m_fck_hw = {
 616         .hw = {
 617                 .clk = &omap_48m_fck,
 618         },
 619         .clksel         = omap_48m_clksel,
 620         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 621         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 622 };
 623
 624 DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
 625
 626 DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
 627
 628 static struct clk core_12m_fck;
 629
 630 static const char *core_12m_fck_parent_names[] = {
 631         "omap_12m_fck",
 632 };
 633
 634 DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
 635 DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
 636
 637 static struct clk core_48m_fck;
 638
 639 static const char *core_48m_fck_parent_names[] = {
 640         "omap_48m_fck",
 641 };
 642
 643 DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
 644 DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
 645
 646 static const char *omap_96m_fck_parent_names[] = {
 647         "cm_96m_fck", "sys_ck",
 648 };
 649
 650 DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
 651                OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 652                OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
 653
 654 static struct clk core_96m_fck;
 655
 656 static const char *core_96m_fck_parent_names[] = {
 657         "omap_96m_fck",
 658 };
 659
 660 DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
 661 DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
 662
 663 static struct clk core_l3_ick;
 664
 665 static const char *core_l3_ick_parent_names[] = {
 666         "l3_ick",
 667 };
 668
 669 DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
 670 DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
 671
 672 DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
 673
 674 static struct clk corex2_fck;
 675
 676 static const char *corex2_fck_parent_names[] = {
 677         "dpll3_m2x2_ck",
 678 };
 679
 680 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
 681 DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
 682
 683 static struct clk cpefuse_fck;
 684
 685 static struct clk_hw_omap cpefuse_fck_hw = {
 686         .hw = {
 687                 .clk = &cpefuse_fck,
 688         },
 689         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
 690         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
 691         .clkdm_name     = "core_l4_clkdm",
 692 };
 693
 694 DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
 695
 696 static struct clk csi2_96m_fck;
 697
 698 static const char *csi2_96m_fck_parent_names[] = {
 699         "core_96m_fck",
 700 };
 701
 702 static struct clk_hw_omap csi2_96m_fck_hw = {
 703         .hw = {
 704                 .clk = &csi2_96m_fck,
 705         },
 706         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
 707         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
 708         .clkdm_name     = "cam_clkdm",
 709 };
 710
 711 DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
 712
 713 static struct clk d2d_26m_fck;
 714
 715 static struct clk_hw_omap d2d_26m_fck_hw = {
 716         .hw = {
 717                 .clk = &d2d_26m_fck,
 718         },
 719         .ops            = &clkhwops_wait,
 720         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 721         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
 722         .clkdm_name     = "d2d_clkdm",
 723 };
 724
 725 DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
 726
 727 static struct clk des1_ick;
 728
 729 static struct clk_hw_omap des1_ick_hw = {
 730         .hw = {
 731                 .clk = &des1_ick,
 732         },
 733         .ops            = &clkhwops_iclk_wait,
 734         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 735         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
 736 };
 737
 738 DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
 739
 740 static struct clk des2_ick;
 741
 742 static struct clk_hw_omap des2_ick_hw = {
 743         .hw = {
 744                 .clk = &des2_ick,
 745         },
 746         .ops            = &clkhwops_iclk_wait,
 747         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 748         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
 749         .clkdm_name     = "core_l4_clkdm",
 750 };
 751
 752 DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
 753
 754 DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
 755                    OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 756                    OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
 757                    CLK_DIVIDER_ONE_BASED, NULL);
 758
 759 static struct clk dpll2_fck;
 760
 761 static struct dpll_data dpll2_dd = {
 762         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 763         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 764         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 765         .clk_bypass     = &dpll2_fck,
 766         .clk_ref        = &sys_ck,
 767         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 768         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 769         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 770         .modes          = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 771                            (1 << DPLL_LOW_POWER_BYPASS)),
 772         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 773         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 774         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 775         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 776         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 777         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 778         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 779         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 780         .min_divider    = 1,
 781         .max_divider    = OMAP3_MAX_DPLL_DIV,
 782 };
 783
 784 static struct clk dpll2_ck;
 785
 786 static struct clk_hw_omap dpll2_ck_hw = {
 787         .hw = {
 788                 .clk = &dpll2_ck,
 789         },
 790         .ops            = &clkhwops_omap3_dpll,
 791         .dpll_data      = &dpll2_dd,
 792         .clkdm_name     = "dpll2_clkdm",
 793 };
 794
 795 DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 796
 797 DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
 798                    OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 799                    OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
 800                    CLK_DIVIDER_ONE_BASED, NULL);
 801
 802 DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
 803                    OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
 804                    OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
 805                    OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
 806                    CLK_DIVIDER_ONE_BASED, NULL);
 807
 808 DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
 809                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 810                    OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
 811                    CLK_DIVIDER_ONE_BASED, NULL);
 812
 813 static struct clk dpll3_m3x2_ck;
 814
 815 static const char *dpll3_m3x2_ck_parent_names[] = {
 816         "dpll3_m3_ck",
 817 };
 818
 819 static struct clk_hw_omap dpll3_m3x2_ck_hw = {
 820         .hw = {
 821                 .clk = &dpll3_m3x2_ck,
 822         },
 823         .ops            = &clkhwops_wait,
 824         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 825         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 826         .flags          = INVERT_ENABLE,
 827         .clkdm_name     = "dpll3_clkdm",
 828 };
 829
 830 DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
 831
 832 static struct clk dpll3_m3x2_ck_3630 = {
 833         .name           = "dpll3_m3x2_ck",
 834         .hw             = &dpll3_m3x2_ck_hw.hw,
 835         .parent_names   = dpll3_m3x2_ck_parent_names,
 836         .num_parents    = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
 837         .ops            = &dpll4_m5x2_ck_3630_ops,
 838 };
 839
 840 DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
 841
 842 DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
 843                    OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 844                    OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
 845                    CLK_DIVIDER_ONE_BASED, NULL);
 846
 847 static struct clk dpll4_m4x2_ck;
 848
 849 static const char *dpll4_m4x2_ck_parent_names[] = {
 850         "dpll4_m4_ck",
 851 };
 852
 853 static struct clk_hw_omap dpll4_m4x2_ck_hw = {
 854         .hw = {
 855                 .clk = &dpll4_m4x2_ck,
 856         },
 857         .ops            = &clkhwops_wait,
 858         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 859         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 860         .flags          = INVERT_ENABLE,
 861         .clkdm_name     = "dpll4_clkdm",
 862 };
 863
 864 DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops);
 865
 866 static struct clk dpll4_m4x2_ck_3630 = {
 867         .name           = "dpll4_m4x2_ck",
 868         .hw             = &dpll4_m4x2_ck_hw.hw,
 869         .parent_names   = dpll4_m4x2_ck_parent_names,
 870         .num_parents    = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
 871         .ops            = &dpll4_m5x2_ck_3630_ops,
 872 };
 873
 874 DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
 875                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 876                    OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
 877                    CLK_DIVIDER_ONE_BASED, NULL);
 878
 879 static struct clk dpll4_m6x2_ck;
 880
 881 static const char *dpll4_m6x2_ck_parent_names[] = {
 882         "dpll4_m6_ck",
 883 };
 884
 885 static struct clk_hw_omap dpll4_m6x2_ck_hw = {
 886         .hw = {
 887                 .clk = &dpll4_m6x2_ck,
 888         },
 889         .ops            = &clkhwops_wait,
 890         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 891         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 892         .flags          = INVERT_ENABLE,
 893         .clkdm_name     = "dpll4_clkdm",
 894 };
 895
 896 DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
 897
 898 static struct clk dpll4_m6x2_ck_3630 = {
 899         .name           = "dpll4_m6x2_ck",
 900         .hw             = &dpll4_m6x2_ck_hw.hw,
 901         .parent_names   = dpll4_m6x2_ck_parent_names,
 902         .num_parents    = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
 903         .ops            = &dpll4_m5x2_ck_3630_ops,
 904 };
 905
 906 DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
 907
 908 static struct dpll_data dpll5_dd = {
 909         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 910         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 911         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 912         .clk_bypass     = &sys_ck,
 913         .clk_ref        = &sys_ck,
 914         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 915         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 916         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 917         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 918         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 919         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 920         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 921         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 922         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 923         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 924         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 925         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 926         .min_divider    = 1,
 927         .max_divider    = OMAP3_MAX_DPLL_DIV,
 928 };
 929
 930 static struct clk dpll5_ck;
 931
 932 static struct clk_hw_omap dpll5_ck_hw = {
 933         .hw = {
 934                 .clk = &dpll5_ck,
 935         },
 936         .ops            = &clkhwops_omap3_dpll,
 937         .dpll_data      = &dpll5_dd,
 938         .clkdm_name     = "dpll5_clkdm",
 939 };
 940
 941 DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
 942
 943 DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
 944                    OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 945                    OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
 946                    CLK_DIVIDER_ONE_BASED, NULL);
 947
 948 static struct clk dss1_alwon_fck_3430es1;
 949
 950 static const char *dss1_alwon_fck_3430es1_parent_names[] = {
 951         "dpll4_m4x2_ck",
 952 };
 953
 954 static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
 955         .hw = {
 956                 .clk = &dss1_alwon_fck_3430es1,
 957         },
 958         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 959         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
 960         .clkdm_name     = "dss_clkdm",
 961 };
 962
 963 DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names,
 964                   aes2_ick_ops);
 965
 966 static struct clk dss1_alwon_fck_3430es2;
 967
 968 static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
 969         .hw = {
 970                 .clk = &dss1_alwon_fck_3430es2,
 971         },
 972         .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
 973         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 974         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
 975         .clkdm_name     = "dss_clkdm",
 976 };
 977
 978 DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names,
 979                   aes2_ick_ops);
 980
 981 static struct clk dss2_alwon_fck;
 982
 983 static struct clk_hw_omap dss2_alwon_fck_hw = {
 984         .hw = {
 985                 .clk = &dss2_alwon_fck,
 986         },
 987         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
 988         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
 989         .clkdm_name     = "dss_clkdm",
 990 };
 991
 992 DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
 993
 994 static struct clk dss_96m_fck;
 995
 996 static struct clk_hw_omap dss_96m_fck_hw = {
 997         .hw = {
 998                 .clk = &dss_96m_fck,
 999         },
1000         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1001         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1002         .clkdm_name     = "dss_clkdm",
1003 };
1004
1005 DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1006
1007 static struct clk dss_ick_3430es1;
1008
1009 static struct clk_hw_omap dss_ick_3430es1_hw = {
1010         .hw = {
1011                 .clk = &dss_ick_3430es1,
1012         },
1013         .ops            = &clkhwops_iclk,
1014         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1015         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1016         .clkdm_name     = "dss_clkdm",
1017 };
1018
1019 DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1020
1021 static struct clk dss_ick_3430es2;
1022
1023 static struct clk_hw_omap dss_ick_3430es2_hw = {
1024         .hw = {
1025                 .clk = &dss_ick_3430es2,
1026         },
1027         .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1028         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1029         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1030         .clkdm_name     = "dss_clkdm",
1031 };
1032
1033 DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1034
1035 static struct clk dss_tv_fck;
1036
1037 static const char *dss_tv_fck_parent_names[] = {
1038         "omap_54m_fck",
1039 };
1040
1041 static struct clk_hw_omap dss_tv_fck_hw = {
1042         .hw = {
1043                 .clk = &dss_tv_fck,
1044         },
1045         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1046         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1047         .clkdm_name     = "dss_clkdm",
1048 };
1049
1050 DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1051
1052 static struct clk emac_fck;
1053
1054 static const char *emac_fck_parent_names[] = {
1055         "rmii_ck",
1056 };
1057
1058 static struct clk_hw_omap emac_fck_hw = {
1059         .hw = {
1060                 .clk = &emac_fck,
1061         },
1062         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1063         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
1064 };
1065
1066 DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1067
1068 static struct clk ipss_ick;
1069
1070 static const char *ipss_ick_parent_names[] = {
1071         "core_l3_ick",
1072 };
1073
1074 static struct clk_hw_omap ipss_ick_hw = {
1075         .hw = {
1076                 .clk = &ipss_ick,
1077         },
1078         .ops            = &clkhwops_am35xx_ipss_wait,
1079         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1080         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
1081         .clkdm_name     = "core_l3_clkdm",
1082 };
1083
1084 DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1085
1086 static struct clk emac_ick;
1087
1088 static const char *emac_ick_parent_names[] = {
1089         "ipss_ick",
1090 };
1091
1092 static struct clk_hw_omap emac_ick_hw = {
1093         .hw = {
1094                 .clk = &emac_ick,
1095         },
1096         .ops            = &clkhwops_am35xx_ipss_module_wait,
1097         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1098         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1099         .clkdm_name     = "core_l3_clkdm",
1100 };
1101
1102 DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1103
1104 static struct clk emu_core_alwon_ck;
1105
1106 static const char *emu_core_alwon_ck_parent_names[] = {
1107         "dpll3_m3x2_ck",
1108 };
1109
1110 DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1111 DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1112                   core_l4_ick_ops);
1113
1114 static struct clk emu_mpu_alwon_ck;
1115
1116 static const char *emu_mpu_alwon_ck_parent_names[] = {
1117         "mpu_ck",
1118 };
1119
1120 DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1121 DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1122
1123 static struct clk emu_per_alwon_ck;
1124
1125 static const char *emu_per_alwon_ck_parent_names[] = {
1126         "dpll4_m6x2_ck",
1127 };
1128
1129 DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1130 DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1131                   core_l4_ick_ops);
1132
1133 static const char *emu_src_ck_parent_names[] = {
1134         "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1135 };
1136
1137 static const struct clksel_rate emu_src_sys_rates[] = {
1138         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1139         { .div = 0 },
1140 };
1141
1142 static const struct clksel_rate emu_src_core_rates[] = {
1143         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1144         { .div = 0 },
1145 };
1146
1147 static const struct clksel_rate emu_src_per_rates[] = {
1148         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1149         { .div = 0 },
1150 };
1151
1152 static const struct clksel_rate emu_src_mpu_rates[] = {
1153         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1154         { .div = 0 },
1155 };
1156
1157 static const struct clksel emu_src_clksel[] = {
1158         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
1159         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1160         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
1161         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
1162         { .parent = NULL },
1163 };
1164
1165 static const struct clk_ops emu_src_ck_ops = {
1166         .init           = &omap2_init_clk_clkdm,
1167         .recalc_rate    = &omap2_clksel_recalc,
1168         .get_parent     = &omap2_clksel_find_parent_index,
1169         .set_parent     = &omap2_clksel_set_parent,
1170 };
1171
1172 static struct clk emu_src_ck;
1173
1174 static struct clk_hw_omap emu_src_ck_hw = {
1175         .hw = {
1176                 .clk = &emu_src_ck,
1177         },
1178         .clksel         = emu_src_clksel,
1179         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1180         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
1181         .clkdm_name     = "emu_clkdm",
1182 };
1183
1184 DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1185
1186 DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1187                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1188                    OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1189                    CLK_DIVIDER_ONE_BASED, NULL);
1190
1191 static struct clk fac_ick;
1192
1193 static struct clk_hw_omap fac_ick_hw = {
1194         .hw = {
1195                 .clk = &fac_ick,
1196         },
1197         .ops            = &clkhwops_iclk_wait,
1198         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1199         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1200         .clkdm_name     = "core_l4_clkdm",
1201 };
1202
1203 DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1204
1205 static struct clk fshostusb_fck;
1206
1207 static const char *fshostusb_fck_parent_names[] = {
1208         "core_48m_fck",
1209 };
1210
1211 static struct clk_hw_omap fshostusb_fck_hw = {
1212         .hw = {
1213                 .clk = &fshostusb_fck,
1214         },
1215         .ops            = &clkhwops_wait,
1216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1217         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1218         .clkdm_name     = "core_l4_clkdm",
1219 };
1220
1221 DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1222
1223 static struct clk gfx_l3_ck;
1224
1225 static struct clk_hw_omap gfx_l3_ck_hw = {
1226         .hw = {
1227                 .clk = &gfx_l3_ck,
1228         },
1229         .ops            = &clkhwops_wait,
1230         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1231         .enable_bit     = OMAP_EN_GFX_SHIFT,
1232         .clkdm_name     = "gfx_3430es1_clkdm",
1233 };
1234
1235 DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1236
1237 DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1238                    OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1239                    OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1240                    CLK_DIVIDER_ONE_BASED, NULL);
1241
1242 static struct clk gfx_cg1_ck;
1243
1244 static const char *gfx_cg1_ck_parent_names[] = {
1245         "gfx_l3_fck",
1246 };
1247
1248 static struct clk_hw_omap gfx_cg1_ck_hw = {
1249         .hw = {
1250                 .clk = &gfx_cg1_ck,
1251         },
1252         .ops            = &clkhwops_wait,
1253         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1254         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1255         .clkdm_name     = "gfx_3430es1_clkdm",
1256 };
1257
1258 DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1259
1260 static struct clk gfx_cg2_ck;
1261
1262 static struct clk_hw_omap gfx_cg2_ck_hw = {
1263         .hw = {
1264                 .clk = &gfx_cg2_ck,
1265         },
1266         .ops            = &clkhwops_wait,
1267         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1268         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1269         .clkdm_name     = "gfx_3430es1_clkdm",
1270 };
1271
1272 DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1273
1274 static struct clk gfx_l3_ick;
1275
1276 static const char *gfx_l3_ick_parent_names[] = {
1277         "gfx_l3_ck",
1278 };
1279
1280 DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1281 DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1282
1283 static struct clk wkup_32k_fck;
1284
1285 static const char *wkup_32k_fck_parent_names[] = {
1286         "omap_32k_fck",
1287 };
1288
1289 DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1290 DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1291
1292 static struct clk gpio1_dbck;
1293
1294 static const char *gpio1_dbck_parent_names[] = {
1295         "wkup_32k_fck",
1296 };
1297
1298 static struct clk_hw_omap gpio1_dbck_hw = {
1299         .hw = {
1300                 .clk = &gpio1_dbck,
1301         },
1302         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1303         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1304         .clkdm_name     = "wkup_clkdm",
1305 };
1306
1307 DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1308
1309 static struct clk wkup_l4_ick;
1310
1311 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1312 DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
1313
1314 static struct clk gpio1_ick;
1315
1316 static const char *gpio1_ick_parent_names[] = {
1317         "wkup_l4_ick",
1318 };
1319
1320 static struct clk_hw_omap gpio1_ick_hw = {
1321         .hw = {
1322                 .clk = &gpio1_ick,
1323         },
1324         .ops            = &clkhwops_iclk_wait,
1325         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1326         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
1327         .clkdm_name     = "wkup_clkdm",
1328 };
1329
1330 DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1331
1332 static struct clk per_32k_alwon_fck;
1333
1334 DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1335 DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1336                   core_l4_ick_ops);
1337
1338 static struct clk gpio2_dbck;
1339
1340 static const char *gpio2_dbck_parent_names[] = {
1341         "per_32k_alwon_fck",
1342 };
1343
1344 static struct clk_hw_omap gpio2_dbck_hw = {
1345         .hw = {
1346                 .clk = &gpio2_dbck,
1347         },
1348         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1349         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1350         .clkdm_name     = "per_clkdm",
1351 };
1352
1353 DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1354
1355 static struct clk per_l4_ick;
1356
1357 DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1358 DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1359
1360 static struct clk gpio2_ick;
1361
1362 static const char *gpio2_ick_parent_names[] = {
1363         "per_l4_ick",
1364 };
1365
1366 static struct clk_hw_omap gpio2_ick_hw = {
1367         .hw = {
1368                 .clk = &gpio2_ick,
1369         },
1370         .ops            = &clkhwops_iclk_wait,
1371         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1372         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
1373         .clkdm_name     = "per_clkdm",
1374 };
1375
1376 DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1377
1378 static struct clk gpio3_dbck;
1379
1380 static struct clk_hw_omap gpio3_dbck_hw = {
1381         .hw = {
1382                 .clk = &gpio3_dbck,
1383         },
1384         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1385         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1386         .clkdm_name     = "per_clkdm",
1387 };
1388
1389 DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1390
1391 static struct clk gpio3_ick;
1392
1393 static struct clk_hw_omap gpio3_ick_hw = {
1394         .hw = {
1395                 .clk = &gpio3_ick,
1396         },
1397         .ops            = &clkhwops_iclk_wait,
1398         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1399         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
1400         .clkdm_name     = "per_clkdm",
1401 };
1402
1403 DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1404
1405 static struct clk gpio4_dbck;
1406
1407 static struct clk_hw_omap gpio4_dbck_hw = {
1408         .hw = {
1409                 .clk = &gpio4_dbck,
1410         },
1411         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1412         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1413         .clkdm_name     = "per_clkdm",
1414 };
1415
1416 DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1417
1418 static struct clk gpio4_ick;
1419
1420 static struct clk_hw_omap gpio4_ick_hw = {
1421         .hw = {
1422                 .clk = &gpio4_ick,
1423         },
1424         .ops            = &clkhwops_iclk_wait,
1425         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1426         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
1427         .clkdm_name     = "per_clkdm",
1428 };
1429
1430 DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1431
1432 static struct clk gpio5_dbck;
1433
1434 static struct clk_hw_omap gpio5_dbck_hw = {
1435         .hw = {
1436                 .clk = &gpio5_dbck,
1437         },
1438         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1439         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1440         .clkdm_name     = "per_clkdm",
1441 };
1442
1443 DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1444
1445 static struct clk gpio5_ick;
1446
1447 static struct clk_hw_omap gpio5_ick_hw = {
1448         .hw = {
1449                 .clk = &gpio5_ick,
1450         },
1451         .ops            = &clkhwops_iclk_wait,
1452         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1453         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
1454         .clkdm_name     = "per_clkdm",
1455 };
1456
1457 DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1458
1459 static struct clk gpio6_dbck;
1460
1461 static struct clk_hw_omap gpio6_dbck_hw = {
1462         .hw = {
1463                 .clk = &gpio6_dbck,
1464         },
1465         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1466         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1467         .clkdm_name     = "per_clkdm",
1468 };
1469
1470 DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1471
1472 static struct clk gpio6_ick;
1473
1474 static struct clk_hw_omap gpio6_ick_hw = {
1475         .hw = {
1476                 .clk = &gpio6_ick,
1477         },
1478         .ops            = &clkhwops_iclk_wait,
1479         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1480         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
1481         .clkdm_name     = "per_clkdm",
1482 };
1483
1484 DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1485
1486 static struct clk gpmc_fck;
1487
1488 static struct clk_hw_omap gpmc_fck_hw = {
1489         .hw = {
1490                 .clk = &gpmc_fck,
1491         },
1492         .flags          = ENABLE_ON_INIT,
1493         .clkdm_name     = "core_l3_clkdm",
1494 };
1495
1496 DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1497
1498 static const struct clksel omap343x_gpt_clksel[] = {
1499         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1500         { .parent = &sys_ck, .rates = gpt_sys_rates },
1501         { .parent = NULL },
1502 };
1503
1504 static const char *gpt10_fck_parent_names[] = {
1505         "omap_32k_fck", "sys_ck",
1506 };
1507
1508 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1509                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1510                          OMAP3430_CLKSEL_GPT10_MASK,
1511                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1512                          OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1513                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1514
1515 static struct clk gpt10_ick;
1516
1517 static struct clk_hw_omap gpt10_ick_hw = {
1518         .hw = {
1519                 .clk = &gpt10_ick,
1520         },
1521         .ops            = &clkhwops_iclk_wait,
1522         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1523         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1524         .clkdm_name     = "core_l4_clkdm",
1525 };
1526
1527 DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1528
1529 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1530                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1531                          OMAP3430_CLKSEL_GPT11_MASK,
1532                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1533                          OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1534                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1535
1536 static struct clk gpt11_ick;
1537
1538 static struct clk_hw_omap gpt11_ick_hw = {
1539         .hw = {
1540                 .clk = &gpt11_ick,
1541         },
1542         .ops            = &clkhwops_iclk_wait,
1543         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1544         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1545         .clkdm_name     = "core_l4_clkdm",
1546 };
1547
1548 DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1549
1550 static struct clk gpt12_fck;
1551
1552 static const char *gpt12_fck_parent_names[] = {
1553         "secure_32k_fck",
1554 };
1555
1556 DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1557 DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1558
1559 static struct clk gpt12_ick;
1560
1561 static struct clk_hw_omap gpt12_ick_hw = {
1562         .hw = {
1563                 .clk = &gpt12_ick,
1564         },
1565         .ops            = &clkhwops_iclk_wait,
1566         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1567         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
1568         .clkdm_name     = "wkup_clkdm",
1569 };
1570
1571 DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1572
1573 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1574                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1575                          OMAP3430_CLKSEL_GPT1_MASK,
1576                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1577                          OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1578                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1579
1580 static struct clk gpt1_ick;
1581
1582 static struct clk_hw_omap gpt1_ick_hw = {
1583         .hw = {
1584                 .clk = &gpt1_ick,
1585         },
1586         .ops            = &clkhwops_iclk_wait,
1587         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1588         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
1589         .clkdm_name     = "wkup_clkdm",
1590 };
1591
1592 DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1593
1594 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1595                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1596                          OMAP3430_CLKSEL_GPT2_MASK,
1597                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1598                          OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1599                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1600
1601 static struct clk gpt2_ick;
1602
1603 static struct clk_hw_omap gpt2_ick_hw = {
1604         .hw = {
1605                 .clk = &gpt2_ick,
1606         },
1607         .ops            = &clkhwops_iclk_wait,
1608         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1609         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
1610         .clkdm_name     = "per_clkdm",
1611 };
1612
1613 DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1614
1615 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1616                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1617                          OMAP3430_CLKSEL_GPT3_MASK,
1618                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1619                          OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1620                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1621
1622 static struct clk gpt3_ick;
1623
1624 static struct clk_hw_omap gpt3_ick_hw = {
1625         .hw = {
1626                 .clk = &gpt3_ick,
1627         },
1628         .ops            = &clkhwops_iclk_wait,
1629         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1630         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
1631         .clkdm_name     = "per_clkdm",
1632 };
1633
1634 DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1635
1636 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1637                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1638                          OMAP3430_CLKSEL_GPT4_MASK,
1639                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1640                          OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1641                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1642
1643 static struct clk gpt4_ick;
1644
1645 static struct clk_hw_omap gpt4_ick_hw = {
1646         .hw = {
1647                 .clk = &gpt4_ick,
1648         },
1649         .ops            = &clkhwops_iclk_wait,
1650         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1651         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
1652         .clkdm_name     = "per_clkdm",
1653 };
1654
1655 DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1656
1657 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1658                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1659                          OMAP3430_CLKSEL_GPT5_MASK,
1660                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1661                          OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1662                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1663
1664 static struct clk gpt5_ick;
1665
1666 static struct clk_hw_omap gpt5_ick_hw = {
1667         .hw = {
1668                 .clk = &gpt5_ick,
1669         },
1670         .ops            = &clkhwops_iclk_wait,
1671         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1672         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
1673         .clkdm_name     = "per_clkdm",
1674 };
1675
1676 DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1677
1678 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1679                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1680                          OMAP3430_CLKSEL_GPT6_MASK,
1681                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1682                          OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1683                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1684
1685 static struct clk gpt6_ick;
1686
1687 static struct clk_hw_omap gpt6_ick_hw = {
1688         .hw = {
1689                 .clk = &gpt6_ick,
1690         },
1691         .ops            = &clkhwops_iclk_wait,
1692         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1693         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
1694         .clkdm_name     = "per_clkdm",
1695 };
1696
1697 DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1698
1699 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1700                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1701                          OMAP3430_CLKSEL_GPT7_MASK,
1702                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1703                          OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1704                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1705
1706 static struct clk gpt7_ick;
1707
1708 static struct clk_hw_omap gpt7_ick_hw = {
1709         .hw = {
1710                 .clk = &gpt7_ick,
1711         },
1712         .ops            = &clkhwops_iclk_wait,
1713         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1714         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
1715         .clkdm_name     = "per_clkdm",
1716 };
1717
1718 DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1719
1720 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1721                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1722                          OMAP3430_CLKSEL_GPT8_MASK,
1723                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1724                          OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1725                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1726
1727 static struct clk gpt8_ick;
1728
1729 static struct clk_hw_omap gpt8_ick_hw = {
1730         .hw = {
1731                 .clk = &gpt8_ick,
1732         },
1733         .ops            = &clkhwops_iclk_wait,
1734         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1735         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
1736         .clkdm_name     = "per_clkdm",
1737 };
1738
1739 DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1740
1741 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1742                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1743                          OMAP3430_CLKSEL_GPT9_MASK,
1744                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1745                          OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1746                          gpt10_fck_parent_names, clkout2_src_ck_ops);
1747
1748 static struct clk gpt9_ick;
1749
1750 static struct clk_hw_omap gpt9_ick_hw = {
1751         .hw = {
1752                 .clk = &gpt9_ick,
1753         },
1754         .ops            = &clkhwops_iclk_wait,
1755         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1756         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
1757         .clkdm_name     = "per_clkdm",
1758 };
1759
1760 DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1761
1762 static struct clk hdq_fck;
1763
1764 static const char *hdq_fck_parent_names[] = {
1765         "core_12m_fck",
1766 };
1767
1768 static struct clk_hw_omap hdq_fck_hw = {
1769         .hw = {
1770                 .clk = &hdq_fck,
1771         },
1772         .ops            = &clkhwops_wait,
1773         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1774         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1775         .clkdm_name     = "core_l4_clkdm",
1776 };
1777
1778 DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1779
1780 static struct clk hdq_ick;
1781
1782 static struct clk_hw_omap hdq_ick_hw = {
1783         .hw = {
1784                 .clk = &hdq_ick,
1785         },
1786         .ops            = &clkhwops_iclk_wait,
1787         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1789         .clkdm_name     = "core_l4_clkdm",
1790 };
1791
1792 DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1793
1794 static struct clk hecc_ck;
1795
1796 static struct clk_hw_omap hecc_ck_hw = {
1797         .hw = {
1798                 .clk = &hecc_ck,
1799         },
1800         .ops            = &clkhwops_am35xx_ipss_module_wait,
1801         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1802         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
1803         .clkdm_name     = "core_l3_clkdm",
1804 };
1805
1806 DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
1807
1808 static struct clk hsotgusb_fck_am35xx;
1809
1810 static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1811         .hw = {
1812                 .clk = &hsotgusb_fck_am35xx,
1813         },
1814         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1815         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
1816         .clkdm_name     = "core_l3_clkdm",
1817 };
1818
1819 DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
1820
1821 static struct clk hsotgusb_ick_3430es1;
1822
1823 static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1824         .hw = {
1825                 .clk = &hsotgusb_ick_3430es1,
1826         },
1827         .ops            = &clkhwops_iclk,
1828         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1830         .clkdm_name     = "core_l3_clkdm",
1831 };
1832
1833 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1834
1835 static struct clk hsotgusb_ick_3430es2;
1836
1837 static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1838         .hw = {
1839                 .clk = &hsotgusb_ick_3430es2,
1840         },
1841         .ops            = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1844         .clkdm_name     = "core_l3_clkdm",
1845 };
1846
1847 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1848
1849 static struct clk hsotgusb_ick_am35xx;
1850
1851 static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1852         .hw = {
1853                 .clk = &hsotgusb_ick_am35xx,
1854         },
1855         .ops            = &clkhwops_am35xx_ipss_module_wait,
1856         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1857         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1858         .clkdm_name     = "core_l3_clkdm",
1859 };
1860
1861 DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1862
1863 static struct clk i2c1_fck;
1864
1865 static struct clk_hw_omap i2c1_fck_hw = {
1866         .hw = {
1867                 .clk = &i2c1_fck,
1868         },
1869         .ops            = &clkhwops_wait,
1870         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1871         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1872         .clkdm_name     = "core_l4_clkdm",
1873 };
1874
1875 DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1876
1877 static struct clk i2c1_ick;
1878
1879 static struct clk_hw_omap i2c1_ick_hw = {
1880         .hw = {
1881                 .clk = &i2c1_ick,
1882         },
1883         .ops            = &clkhwops_iclk_wait,
1884         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1885         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1886         .clkdm_name     = "core_l4_clkdm",
1887 };
1888
1889 DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1890
1891 static struct clk i2c2_fck;
1892
1893 static struct clk_hw_omap i2c2_fck_hw = {
1894         .hw = {
1895                 .clk = &i2c2_fck,
1896         },
1897         .ops            = &clkhwops_wait,
1898         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1899         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1900         .clkdm_name     = "core_l4_clkdm",
1901 };
1902
1903 DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1904
1905 static struct clk i2c2_ick;
1906
1907 static struct clk_hw_omap i2c2_ick_hw = {
1908         .hw = {
1909                 .clk = &i2c2_ick,
1910         },
1911         .ops            = &clkhwops_iclk_wait,
1912         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1914         .clkdm_name     = "core_l4_clkdm",
1915 };
1916
1917 DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1918
1919 static struct clk i2c3_fck;
1920
1921 static struct clk_hw_omap i2c3_fck_hw = {
1922         .hw = {
1923                 .clk = &i2c3_fck,
1924         },
1925         .ops            = &clkhwops_wait,
1926         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1927         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1928         .clkdm_name     = "core_l4_clkdm",
1929 };
1930
1931 DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1932
1933 static struct clk i2c3_ick;
1934
1935 static struct clk_hw_omap i2c3_ick_hw = {
1936         .hw = {
1937                 .clk = &i2c3_ick,
1938         },
1939         .ops            = &clkhwops_iclk_wait,
1940         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1942         .clkdm_name     = "core_l4_clkdm",
1943 };
1944
1945 DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
1946
1947 static struct clk icr_ick;
1948
1949 static struct clk_hw_omap icr_ick_hw = {
1950         .hw = {
1951                 .clk = &icr_ick,
1952         },
1953         .ops            = &clkhwops_iclk_wait,
1954         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1955         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1956         .clkdm_name     = "core_l4_clkdm",
1957 };
1958
1959 DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
1960
1961 static struct clk iva2_ck;
1962
1963 static const char *iva2_ck_parent_names[] = {
1964         "dpll2_m2_ck",
1965 };
1966
1967 static struct clk_hw_omap iva2_ck_hw = {
1968         .hw = {
1969                 .clk = &iva2_ck,
1970         },
1971         .ops            = &clkhwops_wait,
1972         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1973         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1974         .clkdm_name     = "iva2_clkdm",
1975 };
1976
1977 DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
1978
1979 static struct clk mad2d_ick;
1980
1981 static struct clk_hw_omap mad2d_ick_hw = {
1982         .hw = {
1983                 .clk = &mad2d_ick,
1984         },
1985         .ops            = &clkhwops_iclk_wait,
1986         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1987         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1988         .clkdm_name     = "d2d_clkdm",
1989 };
1990
1991 DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
1992
1993 static struct clk mailboxes_ick;
1994
1995 static struct clk_hw_omap mailboxes_ick_hw = {
1996         .hw = {
1997                 .clk = &mailboxes_ick,
1998         },
1999         .ops            = &clkhwops_iclk_wait,
2000         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2001         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2002         .clkdm_name     = "core_l4_clkdm",
2003 };
2004
2005 DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2006
2007 static const struct clksel_rate common_mcbsp_96m_rates[] = {
2008         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2009         { .div = 0 }
2010 };
2011
2012 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2013         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2014         { .div = 0 }
2015 };
2016
2017 static const struct clksel mcbsp_15_clksel[] = {
2018         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2019         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2020         { .parent = NULL },
2021 };
2022
2023 static const char *mcbsp1_fck_parent_names[] = {
2024         "core_96m_fck", "mcbsp_clks",
2025 };
2026
2027 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2028                          OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2029                          OMAP2_MCBSP1_CLKS_MASK,
2030                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2031                          OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2032                          mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2033
2034 static struct clk mcbsp1_ick;
2035
2036 static struct clk_hw_omap mcbsp1_ick_hw = {
2037         .hw = {
2038                 .clk = &mcbsp1_ick,
2039         },
2040         .ops            = &clkhwops_iclk_wait,
2041         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2042         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2043         .clkdm_name     = "core_l4_clkdm",
2044 };
2045
2046 DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2047
2048 static struct clk per_96m_fck;
2049
2050 DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2051 DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2052
2053 static const struct clksel mcbsp_234_clksel[] = {
2054         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2055         { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2056         { .parent = NULL },
2057 };
2058
2059 static const char *mcbsp2_fck_parent_names[] = {
2060         "per_96m_fck", "mcbsp_clks",
2061 };
2062
2063 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2064                          OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2065                          OMAP2_MCBSP2_CLKS_MASK,
2066                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2067                          OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2068                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2069
2070 static struct clk mcbsp2_ick;
2071
2072 static struct clk_hw_omap mcbsp2_ick_hw = {
2073         .hw = {
2074                 .clk = &mcbsp2_ick,
2075         },
2076         .ops            = &clkhwops_iclk_wait,
2077         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2078         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2079         .clkdm_name     = "per_clkdm",
2080 };
2081
2082 DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2083
2084 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2085                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2086                          OMAP2_MCBSP3_CLKS_MASK,
2087                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2088                          OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2089                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2090
2091 static struct clk mcbsp3_ick;
2092
2093 static struct clk_hw_omap mcbsp3_ick_hw = {
2094         .hw = {
2095                 .clk = &mcbsp3_ick,
2096         },
2097         .ops            = &clkhwops_iclk_wait,
2098         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2099         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2100         .clkdm_name     = "per_clkdm",
2101 };
2102
2103 DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2104
2105 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2106                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2107                          OMAP2_MCBSP4_CLKS_MASK,
2108                          OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2109                          OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2110                          mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2111
2112 static struct clk mcbsp4_ick;
2113
2114 static struct clk_hw_omap mcbsp4_ick_hw = {
2115         .hw = {
2116                 .clk = &mcbsp4_ick,
2117         },
2118         .ops            = &clkhwops_iclk_wait,
2119         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2120         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2121         .clkdm_name     = "per_clkdm",
2122 };
2123
2124 DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2125
2126 DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2127                          OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2128                          OMAP2_MCBSP5_CLKS_MASK,
2129                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2130                          OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2131                          mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2132
2133 static struct clk mcbsp5_ick;
2134
2135 static struct clk_hw_omap mcbsp5_ick_hw = {
2136         .hw = {
2137                 .clk = &mcbsp5_ick,
2138         },
2139         .ops            = &clkhwops_iclk_wait,
2140         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2141         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2142         .clkdm_name     = "core_l4_clkdm",
2143 };
2144
2145 DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2146
2147 static struct clk mcspi1_fck;
2148
2149 static struct clk_hw_omap mcspi1_fck_hw = {
2150         .hw = {
2151                 .clk = &mcspi1_fck,
2152         },
2153         .ops            = &clkhwops_wait,
2154         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2155         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2156         .clkdm_name     = "core_l4_clkdm",
2157 };
2158
2159 DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2160
2161 static struct clk mcspi1_ick;
2162
2163 static struct clk_hw_omap mcspi1_ick_hw = {
2164         .hw = {
2165                 .clk = &mcspi1_ick,
2166         },
2167         .ops            = &clkhwops_iclk_wait,
2168         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2169         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2170         .clkdm_name     = "core_l4_clkdm",
2171 };
2172
2173 DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2174
2175 static struct clk mcspi2_fck;
2176
2177 static struct clk_hw_omap mcspi2_fck_hw = {
2178         .hw = {
2179                 .clk = &mcspi2_fck,
2180         },
2181         .ops            = &clkhwops_wait,
2182         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2183         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2184         .clkdm_name     = "core_l4_clkdm",
2185 };
2186
2187 DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2188
2189 static struct clk mcspi2_ick;
2190
2191 static struct clk_hw_omap mcspi2_ick_hw = {
2192         .hw = {
2193                 .clk = &mcspi2_ick,
2194         },
2195         .ops            = &clkhwops_iclk_wait,
2196         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2197         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
2198         .clkdm_name     = "core_l4_clkdm",
2199 };
2200
2201 DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2202
2203 static struct clk mcspi3_fck;
2204
2205 static struct clk_hw_omap mcspi3_fck_hw = {
2206         .hw = {
2207                 .clk = &mcspi3_fck,
2208         },
2209         .ops            = &clkhwops_wait,
2210         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2211         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2212         .clkdm_name     = "core_l4_clkdm",
2213 };
2214
2215 DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2216
2217 static struct clk mcspi3_ick;
2218
2219 static struct clk_hw_omap mcspi3_ick_hw = {
2220         .hw = {
2221                 .clk = &mcspi3_ick,
2222         },
2223         .ops            = &clkhwops_iclk_wait,
2224         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2225         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
2226         .clkdm_name     = "core_l4_clkdm",
2227 };
2228
2229 DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2230
2231 static struct clk mcspi4_fck;
2232
2233 static struct clk_hw_omap mcspi4_fck_hw = {
2234         .hw = {
2235                 .clk = &mcspi4_fck,
2236         },
2237         .ops            = &clkhwops_wait,
2238         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2239         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
2240         .clkdm_name     = "core_l4_clkdm",
2241 };
2242
2243 DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2244
2245 static struct clk mcspi4_ick;
2246
2247 static struct clk_hw_omap mcspi4_ick_hw = {
2248         .hw = {
2249                 .clk = &mcspi4_ick,
2250         },
2251         .ops            = &clkhwops_iclk_wait,
2252         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2253         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
2254         .clkdm_name     = "core_l4_clkdm",
2255 };
2256
2257 DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2258
2259 static struct clk mmchs1_fck;
2260
2261 static struct clk_hw_omap mmchs1_fck_hw = {
2262         .hw = {
2263                 .clk = &mmchs1_fck,
2264         },
2265         .ops            = &clkhwops_wait,
2266         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2267         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
2268         .clkdm_name     = "core_l4_clkdm",
2269 };
2270
2271 DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2272
2273 static struct clk mmchs1_ick;
2274
2275 static struct clk_hw_omap mmchs1_ick_hw = {
2276         .hw = {
2277                 .clk = &mmchs1_ick,
2278         },
2279         .ops            = &clkhwops_iclk_wait,
2280         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2281         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
2282         .clkdm_name     = "core_l4_clkdm",
2283 };
2284
2285 DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2286
2287 static struct clk mmchs2_fck;
2288
2289 static struct clk_hw_omap mmchs2_fck_hw = {
2290         .hw = {
2291                 .clk = &mmchs2_fck,
2292         },
2293         .ops            = &clkhwops_wait,
2294         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2295         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
2296         .clkdm_name     = "core_l4_clkdm",
2297 };
2298
2299 DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2300
2301 static struct clk mmchs2_ick;
2302
2303 static struct clk_hw_omap mmchs2_ick_hw = {
2304         .hw = {
2305                 .clk = &mmchs2_ick,
2306         },
2307         .ops            = &clkhwops_iclk_wait,
2308         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2309         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
2310         .clkdm_name     = "core_l4_clkdm",
2311 };
2312
2313 DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2314
2315 static struct clk mmchs3_fck;
2316
2317 static struct clk_hw_omap mmchs3_fck_hw = {
2318         .hw = {
2319                 .clk = &mmchs3_fck,
2320         },
2321         .ops            = &clkhwops_wait,
2322         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2323         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
2324         .clkdm_name     = "core_l4_clkdm",
2325 };
2326
2327 DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2328
2329 static struct clk mmchs3_ick;
2330
2331 static struct clk_hw_omap mmchs3_ick_hw = {
2332         .hw = {
2333                 .clk = &mmchs3_ick,
2334         },
2335         .ops            = &clkhwops_iclk_wait,
2336         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2337         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
2338         .clkdm_name     = "core_l4_clkdm",
2339 };
2340
2341 DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2342
2343 static struct clk modem_fck;
2344
2345 static struct clk_hw_omap modem_fck_hw = {
2346         .hw = {
2347                 .clk = &modem_fck,
2348         },
2349         .ops            = &clkhwops_iclk_wait,
2350         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2351         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
2352         .clkdm_name     = "d2d_clkdm",
2353 };
2354
2355 DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
2356
2357 static struct clk mspro_fck;
2358
2359 static struct clk_hw_omap mspro_fck_hw = {
2360         .hw = {
2361                 .clk = &mspro_fck,
2362         },
2363         .ops            = &clkhwops_wait,
2364         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2365         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
2366         .clkdm_name     = "core_l4_clkdm",
2367 };
2368
2369 DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2370
2371 static struct clk mspro_ick;
2372
2373 static struct clk_hw_omap mspro_ick_hw = {
2374         .hw = {
2375                 .clk = &mspro_ick,
2376         },
2377         .ops            = &clkhwops_iclk_wait,
2378         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2379         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
2380         .clkdm_name     = "core_l4_clkdm",
2381 };
2382
2383 DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2384
2385 static struct clk omap_192m_alwon_fck;
2386
2387 DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2388 DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2389                   core_ck_ops);
2390
2391 static struct clk omap_32ksync_ick;
2392
2393 static struct clk_hw_omap omap_32ksync_ick_hw = {
2394         .hw = {
2395                 .clk = &omap_32ksync_ick,
2396         },
2397         .ops            = &clkhwops_iclk_wait,
2398         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2399         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2400         .clkdm_name     = "wkup_clkdm",
2401 };
2402
2403 DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2404
2405 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2406         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2407         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2408         { .div = 0 }
2409 };
2410
2411 static const struct clksel omap_96m_alwon_fck_clksel[] = {
2412         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2413         { .parent = NULL }
2414 };
2415
2416 static struct clk omap_96m_alwon_fck_3630;
2417
2418 static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2419         "omap_192m_alwon_fck",
2420 };
2421
2422 static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2423         .set_rate       = &omap2_clksel_set_rate,
2424         .recalc_rate    = &omap2_clksel_recalc,
2425         .round_rate     = &omap2_clksel_round_rate,
2426 };
2427
2428 static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2429         .hw = {
2430                 .clk = &omap_96m_alwon_fck_3630,
2431         },
2432         .clksel         = omap_96m_alwon_fck_clksel,
2433         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2434         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
2435 };
2436
2437 static struct clk omap_96m_alwon_fck_3630 = {
2438         .name   = "omap_96m_alwon_fck",
2439         .hw     = &omap_96m_alwon_fck_3630_hw.hw,
2440         .parent_names   = omap_96m_alwon_fck_3630_parent_names,
2441         .num_parents    = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2442         .ops    = &omap_96m_alwon_fck_3630_ops,
2443 };
2444
2445 static struct clk omapctrl_ick;
2446
2447 static struct clk_hw_omap omapctrl_ick_hw = {
2448         .hw = {
2449                 .clk = &omapctrl_ick,
2450         },
2451         .ops            = &clkhwops_iclk_wait,
2452         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2453         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2454         .flags          = ENABLE_ON_INIT,
2455         .clkdm_name     = "core_l4_clkdm",
2456 };
2457
2458 DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2459
2460 DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2461                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2462                    OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2463                    CLK_DIVIDER_ONE_BASED, NULL);
2464
2465 DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2466                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2467                    OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2468                    CLK_DIVIDER_ONE_BASED, NULL);
2469
2470 static struct clk per_48m_fck;
2471
2472 DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2473 DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2474
2475 static struct clk security_l3_ick;
2476
2477 DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2478 DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2479
2480 static struct clk pka_ick;
2481
2482 static const char *pka_ick_parent_names[] = {
2483         "security_l3_ick",
2484 };
2485
2486 static struct clk_hw_omap pka_ick_hw = {
2487         .hw = {
2488                 .clk = &pka_ick,
2489         },
2490         .ops            = &clkhwops_iclk_wait,
2491         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2492         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
2493 };
2494
2495 DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2496
2497 DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2498                    OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2499                    OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2500                    CLK_DIVIDER_ONE_BASED, NULL);
2501
2502 static struct clk rng_ick;
2503
2504 static struct clk_hw_omap rng_ick_hw = {
2505         .hw = {
2506                 .clk = &rng_ick,
2507         },
2508         .ops            = &clkhwops_iclk_wait,
2509         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2510         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2511 };
2512
2513 DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2514
2515 static struct clk sad2d_ick;
2516
2517 static struct clk_hw_omap sad2d_ick_hw = {
2518         .hw = {
2519                 .clk = &sad2d_ick,
2520         },
2521         .ops            = &clkhwops_iclk_wait,
2522         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2523         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
2524         .clkdm_name     = "d2d_clkdm",
2525 };
2526
2527 DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2528
2529 static struct clk sdrc_ick;
2530
2531 static struct clk_hw_omap sdrc_ick_hw = {
2532         .hw = {
2533                 .clk = &sdrc_ick,
2534         },
2535         .ops            = &clkhwops_wait,
2536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2537         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
2538         .flags          = ENABLE_ON_INIT,
2539         .clkdm_name     = "core_l3_clkdm",
2540 };
2541
2542 DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2543
2544 static const struct clksel_rate sgx_core_rates[] = {
2545         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2546         { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2547         { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2548         { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2549         { .div = 0 }
2550 };
2551
2552 static const struct clksel_rate sgx_96m_rates[] = {
2553         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2554         { .div = 0 }
2555 };
2556
2557 static const struct clksel_rate sgx_192m_rates[] = {
2558         { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2559         { .div = 0 }
2560 };
2561
2562 static const struct clksel_rate sgx_corex2_rates[] = {
2563         { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2564         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2565         { .div = 0 }
2566 };
2567
2568 static const struct clksel sgx_clksel[] = {
2569         { .parent = &core_ck, .rates = sgx_core_rates },
2570         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2571         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2572         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2573         { .parent = NULL },
2574 };
2575
2576 static const char *sgx_fck_parent_names[] = {
2577         "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2578 };
2579
2580 static struct clk sgx_fck;
2581
2582 static const struct clk_ops sgx_fck_ops = {
2583         .init           = &omap2_init_clk_clkdm,
2584         .enable         = &omap2_dflt_clk_enable,
2585         .disable        = &omap2_dflt_clk_disable,
2586         .is_enabled     = &omap2_dflt_clk_is_enabled,
2587         .recalc_rate    = &omap2_clksel_recalc,
2588         .set_rate       = &omap2_clksel_set_rate,
2589         .round_rate     = &omap2_clksel_round_rate,
2590         .get_parent     = &omap2_clksel_find_parent_index,
2591         .set_parent     = &omap2_clksel_set_parent,
2592 };
2593
2594 DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2595                          OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2596                          OMAP3430ES2_CLKSEL_SGX_MASK,
2597                          OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2598                          OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2599                          &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2600
2601 static struct clk sgx_ick;
2602
2603 static struct clk_hw_omap sgx_ick_hw = {
2604         .hw = {
2605                 .clk = &sgx_ick,
2606         },
2607         .ops            = &clkhwops_wait,
2608         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2609         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2610         .clkdm_name     = "sgx_clkdm",
2611 };
2612
2613 DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2614
2615 static struct clk sha11_ick;
2616
2617 static struct clk_hw_omap sha11_ick_hw = {
2618         .hw = {
2619                 .clk = &sha11_ick,
2620         },
2621         .ops            = &clkhwops_iclk_wait,
2622         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2623         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2624 };
2625
2626 DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2627
2628 static struct clk sha12_ick;
2629
2630 static struct clk_hw_omap sha12_ick_hw = {
2631         .hw = {
2632                 .clk = &sha12_ick,
2633         },
2634         .ops            = &clkhwops_iclk_wait,
2635         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2636         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
2637         .clkdm_name     = "core_l4_clkdm",
2638 };
2639
2640 DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2641
2642 static struct clk sr1_fck;
2643
2644 static struct clk_hw_omap sr1_fck_hw = {
2645         .hw = {
2646                 .clk = &sr1_fck,
2647         },
2648         .ops            = &clkhwops_wait,
2649         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2650         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2651         .clkdm_name     = "wkup_clkdm",
2652 };
2653
2654 DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
2655
2656 static struct clk sr2_fck;
2657
2658 static struct clk_hw_omap sr2_fck_hw = {
2659         .hw = {
2660                 .clk = &sr2_fck,
2661         },
2662         .ops            = &clkhwops_wait,
2663         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2664         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2665         .clkdm_name     = "wkup_clkdm",
2666 };
2667
2668 DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
2669
2670 static struct clk sr_l4_ick;
2671
2672 DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2673 DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2674
2675 static struct clk ssi_l4_ick;
2676
2677 DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2678 DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2679
2680 static struct clk ssi_ick_3430es1;
2681
2682 static const char *ssi_ick_3430es1_parent_names[] = {
2683         "ssi_l4_ick",
2684 };
2685
2686 static struct clk_hw_omap ssi_ick_3430es1_hw = {
2687         .hw = {
2688                 .clk = &ssi_ick_3430es1,
2689         },
2690         .ops            = &clkhwops_iclk,
2691         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2692         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2693         .clkdm_name     = "core_l4_clkdm",
2694 };
2695
2696 DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2697
2698 static struct clk ssi_ick_3430es2;
2699
2700 static struct clk_hw_omap ssi_ick_3430es2_hw = {
2701         .hw = {
2702                 .clk = &ssi_ick_3430es2,
2703         },
2704         .ops            = &clkhwops_omap3430es2_iclk_ssi_wait,
2705         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2706         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2707         .clkdm_name     = "core_l4_clkdm",
2708 };
2709
2710 DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2711
2712 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2713         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2714         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2715         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2716         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2717         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2718         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2719         { .div = 0 }
2720 };
2721
2722 static const struct clksel ssi_ssr_clksel[] = {
2723         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2724         { .parent = NULL },
2725 };
2726
2727 static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2728         "corex2_fck",
2729 };
2730
2731 static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2732         .init           = &omap2_init_clk_clkdm,
2733         .enable         = &omap2_dflt_clk_enable,
2734         .disable        = &omap2_dflt_clk_disable,
2735         .is_enabled     = &omap2_dflt_clk_is_enabled,
2736         .recalc_rate    = &omap2_clksel_recalc,
2737         .set_rate       = &omap2_clksel_set_rate,
2738         .round_rate     = &omap2_clksel_round_rate,
2739 };
2740
2741 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2742                          ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2743                          OMAP3430_CLKSEL_SSI_MASK,
2744                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2745                          OMAP3430_EN_SSI_SHIFT,
2746                          NULL, ssi_ssr_fck_3430es1_parent_names,
2747                          ssi_ssr_fck_3430es1_ops);
2748
2749 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2750                          ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2751                          OMAP3430_CLKSEL_SSI_MASK,
2752                          OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2753                          OMAP3430_EN_SSI_SHIFT,
2754                          NULL, ssi_ssr_fck_3430es1_parent_names,
2755                          ssi_ssr_fck_3430es1_ops);
2756
2757 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2758                         &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2759
2760 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2761                         &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2762
2763 static struct clk sys_clkout1;
2764
2765 static const char *sys_clkout1_parent_names[] = {
2766         "osc_sys_ck",
2767 };
2768
2769 static struct clk_hw_omap sys_clkout1_hw = {
2770         .hw = {
2771                 .clk = &sys_clkout1,
2772         },
2773         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
2774         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
2775 };
2776
2777 DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2778
2779 DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2780                    OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2781                    OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2782
2783 DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2784                OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2785                OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2786                0x0, NULL);
2787
2788 DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2789                    OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2790                    OMAP3430_CLKSEL_TRACECLK_SHIFT,
2791                    OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2792
2793 static struct clk ts_fck;
2794
2795 static struct clk_hw_omap ts_fck_hw = {
2796         .hw = {
2797                 .clk = &ts_fck,
2798         },
2799         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2800         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
2801         .clkdm_name     = "core_l4_clkdm",
2802 };
2803
2804 DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2805
2806 static struct clk uart1_fck;
2807
2808 static struct clk_hw_omap uart1_fck_hw = {
2809         .hw = {
2810                 .clk = &uart1_fck,
2811         },
2812         .ops            = &clkhwops_wait,
2813         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2814         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2815         .clkdm_name     = "core_l4_clkdm",
2816 };
2817
2818 DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2819
2820 static struct clk uart1_ick;
2821
2822 static struct clk_hw_omap uart1_ick_hw = {
2823         .hw = {
2824                 .clk = &uart1_ick,
2825         },
2826         .ops            = &clkhwops_iclk_wait,
2827         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2828         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2829         .clkdm_name     = "core_l4_clkdm",
2830 };
2831
2832 DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2833
2834 static struct clk uart2_fck;
2835
2836 static struct clk_hw_omap uart2_fck_hw = {
2837         .hw = {
2838                 .clk = &uart2_fck,
2839         },
2840         .ops            = &clkhwops_wait,
2841         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2842         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2843         .clkdm_name     = "core_l4_clkdm",
2844 };
2845
2846 DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2847
2848 static struct clk uart2_ick;
2849
2850 static struct clk_hw_omap uart2_ick_hw = {
2851         .hw = {
2852                 .clk = &uart2_ick,
2853         },
2854         .ops            = &clkhwops_iclk_wait,
2855         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2856         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2857         .clkdm_name     = "core_l4_clkdm",
2858 };
2859
2860 DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2861
2862 static struct clk uart3_fck;
2863
2864 static const char *uart3_fck_parent_names[] = {
2865         "per_48m_fck",
2866 };
2867
2868 static struct clk_hw_omap uart3_fck_hw = {
2869         .hw = {
2870                 .clk = &uart3_fck,
2871         },
2872         .ops            = &clkhwops_wait,
2873         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2874         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2875         .clkdm_name     = "per_clkdm",
2876 };
2877
2878 DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2879
2880 static struct clk uart3_ick;
2881
2882 static struct clk_hw_omap uart3_ick_hw = {
2883         .hw = {
2884                 .clk = &uart3_ick,
2885         },
2886         .ops            = &clkhwops_iclk_wait,
2887         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2888         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2889         .clkdm_name     = "per_clkdm",
2890 };
2891
2892 DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2893
2894 static struct clk uart4_fck;
2895
2896 static struct clk_hw_omap uart4_fck_hw = {
2897         .hw = {
2898                 .clk = &uart4_fck,
2899         },
2900         .ops            = &clkhwops_wait,
2901         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2902         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2903         .clkdm_name     = "per_clkdm",
2904 };
2905
2906 DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2907
2908 static struct clk uart4_fck_am35xx;
2909
2910 static struct clk_hw_omap uart4_fck_am35xx_hw = {
2911         .hw = {
2912                 .clk = &uart4_fck_am35xx,
2913         },
2914         .ops            = &clkhwops_wait,
2915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2916         .enable_bit     = AM35XX_EN_UART4_SHIFT,
2917         .clkdm_name     = "core_l4_clkdm",
2918 };
2919
2920 DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2921
2922 static struct clk uart4_ick;
2923
2924 static struct clk_hw_omap uart4_ick_hw = {
2925         .hw = {
2926                 .clk = &uart4_ick,
2927         },
2928         .ops            = &clkhwops_iclk_wait,
2929         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2930         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2931         .clkdm_name     = "per_clkdm",
2932 };
2933
2934 DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2935
2936 static struct clk uart4_ick_am35xx;
2937
2938 static struct clk_hw_omap uart4_ick_am35xx_hw = {
2939         .hw = {
2940                 .clk = &uart4_ick_am35xx,
2941         },
2942         .ops            = &clkhwops_iclk_wait,
2943         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2944         .enable_bit     = AM35XX_EN_UART4_SHIFT,
2945         .clkdm_name     = "core_l4_clkdm",
2946 };
2947
2948 DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
2949
2950 static const struct clksel_rate div2_rates[] = {
2951         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2952         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2953         { .div = 0 }
2954 };
2955
2956 static const struct clksel usb_l4_clksel[] = {
2957         { .parent = &l4_ick, .rates = div2_rates },
2958         { .parent = NULL },
2959 };
2960
2961 static const char *usb_l4_ick_parent_names[] = {
2962         "l4_ick",
2963 };
2964
2965 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
2966                          OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2967                          OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2968                          OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2969                          OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2970                          &clkhwops_iclk_wait, usb_l4_ick_parent_names,
2971                          ssi_ssr_fck_3430es1_ops);
2972
2973 static struct clk usbhost_120m_fck;
2974
2975 static const char *usbhost_120m_fck_parent_names[] = {
2976         "dpll5_m2_ck",
2977 };
2978
2979 static struct clk_hw_omap usbhost_120m_fck_hw = {
2980         .hw = {
2981                 .clk = &usbhost_120m_fck,
2982         },
2983         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2984         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2985         .clkdm_name     = "usbhost_clkdm",
2986 };
2987
2988 DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
2989                   aes2_ick_ops);
2990
2991 static struct clk usbhost_48m_fck;
2992
2993 static struct clk_hw_omap usbhost_48m_fck_hw = {
2994         .hw = {
2995                 .clk = &usbhost_48m_fck,
2996         },
2997         .ops            = &clkhwops_omap3430es2_dss_usbhost_wait,
2998         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2999         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
3000         .clkdm_name     = "usbhost_clkdm",
3001 };
3002
3003 DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3004
3005 static struct clk usbhost_ick;
3006
3007 static struct clk_hw_omap usbhost_ick_hw = {
3008         .hw = {
3009                 .clk = &usbhost_ick,
3010         },
3011         .ops            = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3012         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3013         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
3014         .clkdm_name     = "usbhost_clkdm",
3015 };
3016
3017 DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3018
3019 static struct clk usbtll_fck;
3020
3021 static struct clk_hw_omap usbtll_fck_hw = {
3022         .hw = {
3023                 .clk = &usbtll_fck,
3024         },
3025         .ops            = &clkhwops_wait,
3026         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3027         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
3028         .clkdm_name     = "core_l4_clkdm",
3029 };
3030
3031 DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3032
3033 static struct clk usbtll_ick;
3034
3035 static struct clk_hw_omap usbtll_ick_hw = {
3036         .hw = {
3037                 .clk = &usbtll_ick,
3038         },
3039         .ops            = &clkhwops_iclk_wait,
3040         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3041         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
3042         .clkdm_name     = "core_l4_clkdm",
3043 };
3044
3045 DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3046
3047 static const struct clksel_rate usim_96m_rates[] = {
3048         { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3049         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3050         { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3051         { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3052         { .div = 0 }
3053 };
3054
3055 static const struct clksel_rate usim_120m_rates[] = {
3056         { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3057         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3058         { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3059         { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3060         { .div = 0 }
3061 };
3062
3063 static const struct clksel usim_clksel[] = {
3064         { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3065         { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3066         { .parent = &sys_ck, .rates = div2_rates },
3067         { .parent = NULL },
3068 };
3069
3070 static const char *usim_fck_parent_names[] = {
3071         "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3072 };
3073
3074 static struct clk usim_fck;
3075
3076 static const struct clk_ops usim_fck_ops = {
3077         .enable         = &omap2_dflt_clk_enable,
3078         .disable        = &omap2_dflt_clk_disable,
3079         .is_enabled     = &omap2_dflt_clk_is_enabled,
3080         .recalc_rate    = &omap2_clksel_recalc,
3081         .get_parent     = &omap2_clksel_find_parent_index,
3082         .set_parent     = &omap2_clksel_set_parent,
3083 };
3084
3085 DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3086                          OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3087                          OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3088                          OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3089                          OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3090                          usim_fck_parent_names, usim_fck_ops);
3091
3092 static struct clk usim_ick;
3093
3094 static struct clk_hw_omap usim_ick_hw = {
3095         .hw = {
3096                 .clk = &usim_ick,
3097         },
3098         .ops            = &clkhwops_iclk_wait,
3099         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3100         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
3101         .clkdm_name     = "wkup_clkdm",
3102 };
3103
3104 DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3105
3106 static struct clk vpfe_fck;
3107
3108 static const char *vpfe_fck_parent_names[] = {
3109         "pclk_ck",
3110 };
3111
3112 static struct clk_hw_omap vpfe_fck_hw = {
3113         .hw = {
3114                 .clk = &vpfe_fck,
3115         },
3116         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3117         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3118 };
3119
3120 DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3121
3122 static struct clk vpfe_ick;
3123
3124 static struct clk_hw_omap vpfe_ick_hw = {
3125         .hw = {
3126                 .clk = &vpfe_ick,
3127         },
3128         .ops            = &clkhwops_am35xx_ipss_module_wait,
3129         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3130         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3131         .clkdm_name     = "core_l3_clkdm",
3132 };
3133
3134 DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3135
3136 static struct clk wdt1_fck;
3137
3138 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3139 DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3140
3141 static struct clk wdt1_ick;
3142
3143 static struct clk_hw_omap wdt1_ick_hw = {
3144         .hw = {
3145                 .clk = &wdt1_ick,
3146         },
3147         .ops            = &clkhwops_iclk_wait,
3148         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3149         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
3150         .clkdm_name     = "wkup_clkdm",
3151 };
3152
3153 DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3154
3155 static struct clk wdt2_fck;
3156
3157 static struct clk_hw_omap wdt2_fck_hw = {
3158         .hw = {
3159                 .clk = &wdt2_fck,
3160         },
3161         .ops            = &clkhwops_wait,
3162         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3163         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
3164         .clkdm_name     = "wkup_clkdm",
3165 };
3166
3167 DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3168
3169 static struct clk wdt2_ick;
3170
3171 static struct clk_hw_omap wdt2_ick_hw = {
3172         .hw = {
3173                 .clk = &wdt2_ick,
3174         },
3175         .ops            = &clkhwops_iclk_wait,
3176         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3177         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
3178         .clkdm_name     = "wkup_clkdm",
3179 };
3180
3181 DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3182
3183 static struct clk wdt3_fck;
3184
3185 static struct clk_hw_omap wdt3_fck_hw = {
3186         .hw = {
3187                 .clk = &wdt3_fck,
3188         },
3189         .ops            = &clkhwops_wait,
3190         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3191         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
3192         .clkdm_name     = "per_clkdm",
3193 };
3194
3195 DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3196
3197 static struct clk wdt3_ick;
3198
3199 static struct clk_hw_omap wdt3_ick_hw = {
3200         .hw = {
3201                 .clk = &wdt3_ick,
3202         },
3203         .ops            = &clkhwops_iclk_wait,
3204         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3205         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
3206         .clkdm_name     = "per_clkdm",
3207 };
3208
3209 DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3210
3211 /*
3212  * clkdev
3213  */
3214 static struct omap_clk omap3xxx_clks[] = {
3215         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
3216         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
3217         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
3218         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
3219         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
3220         CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
3221         CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
3222         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3223         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
3224         CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
3225         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
3226         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
3227         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
3228         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
3229         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
3230         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
3231         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3232         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
3233         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
3234         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
3235         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
3236         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
3237         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
3238         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3239         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
3240         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3241         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3242         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
3243         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
3244         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3245         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3246         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
3247         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
3248         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
3249         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
3250         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
3251         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
3252         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3253         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
3254         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3255         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
3256         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3257         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
3258         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3259         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
3260         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3261         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3262         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3263         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3264         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3265         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
3266         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
3267         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
3268         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
3269         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
3270         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3271         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
3272         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
3273         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
3274         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
3275         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
3276         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
3277         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
3278         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
3279         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
3280         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
3281         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3282         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3283         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
3284         CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
3285         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
3286         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
3287         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
3288         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
3289         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3290         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3291         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3292         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3293         CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3294         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
3295         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3296         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
3297         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
3298         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
3299         CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
3300         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
3301         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
3302         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
3303         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
3304         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
3305         CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
3306         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
3307         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
3308         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
3309         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
3310         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
3311         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3312         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
3313         CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
3314         CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
3315         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
3316         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3317         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
3318         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3319         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
3320         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
3321         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
3322         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
3323         CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
3324         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
3325         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
3326         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3327         CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
3328         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
3329         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3330         CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3331         CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3332         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3333         CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3334         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
3335         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
3336         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
3337         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
3338         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
3339         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
3340         CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
3341         CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
3342         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
3343         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
3344         CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
3345         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
3346         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
3347         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
3348         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
3349         CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
3350         CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
3351         CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
3352         CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
3353         CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
3354         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
3355         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
3356         CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
3357         CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
3358         CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
3359         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
3360         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
3361         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
3362         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
3363         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
3364         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
3365         CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
3366         CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
3367         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
3368         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3369         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
3370         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
3371         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
3372         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
3373         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
3374         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3375         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
3376         CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
3377         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
3378         CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
3379         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
3380         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3381         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
3382         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
3383         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
3384         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
3385         CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
3386         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3387         CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3388         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
3389         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
3390         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
3391         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3392         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3393         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3394         CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3395         CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
3396         CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
3397         CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
3398         CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
3399         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
3400         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
3401         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
3402         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
3403         CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
3404         CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
3405         CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
3406         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
3407         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
3408         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
3409         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
3410         CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
3411         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
3412         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
3413         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
3414         CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
3415         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
3416         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
3417         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3418         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
3419         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
3420         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
3421         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
3422         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
3423         CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
3424         CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
3425         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
3426         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
3427         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
3428         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
3429         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
3430         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
3431         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
3432         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
3433         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3434         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
3435         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
3436         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
3437         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
3438         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
3439         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
3440         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
3441         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
3442         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
3443         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
3444         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
3445         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
3446         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
3447         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
3448         CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
3449         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
3450         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
3451         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
3452         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
3453         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
3454         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
3455         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
3456         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
3457         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
3458         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
3459         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
3460         CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
3461         CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
3462         CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
3463         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
3464         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
3465         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
3466         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3467         CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3468         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
3469         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
3470         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
3471         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3472         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
3473         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
3474         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
3475         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
3476         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3477         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
3478         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
3479         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
3480         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
3481         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
3482         CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
3483         CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
3484         CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
3485         CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
3486         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
3487         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
3488         CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
3489         CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx,   CK_AM35XX),
3490         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
3491         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
3492         CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
3493         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
3494         CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
3495 };
3496
3497 static const char *enable_init_clks[] = {
3498         "sdrc_ick",
3499         "gpmc_fck",
3500         "omapctrl_ick",
3501 };
3502
3503 int __init omap3xxx_clk_init(void)
3504 {
3505         struct omap_clk *c;
3506         u32 cpu_clkflg = 0;
3507
3508         /*
3509          * 3505 must be tested before 3517, since 3517 returns true
3510          * for both AM3517 chips and AM3517 family chips, which
3511          * includes 3505.  Unfortunately there's no obvious family
3512          * test for 3517/3505 :-(
3513          */
3514         if (soc_is_am35xx()) {
3515                 cpu_mask = RATE_IN_34XX;
3516                 cpu_clkflg = CK_AM35XX;
3517         } else if (cpu_is_omap3630()) {
3518                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3519                 cpu_clkflg = CK_36XX;
3520         } else if (cpu_is_ti816x()) {
3521                 cpu_mask = RATE_IN_TI816X;
3522                 cpu_clkflg = CK_TI816X;
3523         } else if (soc_is_am33xx()) {
3524                 cpu_mask = RATE_IN_AM33XX;
3525         } else if (cpu_is_ti814x()) {
3526                 cpu_mask = RATE_IN_TI814X;
3527         } else if (cpu_is_omap34xx()) {
3528                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3529                         cpu_mask = RATE_IN_3430ES1;
3530                         cpu_clkflg = CK_3430ES1;
3531                 } else {
3532                         /*
3533                          * Assume that anything that we haven't matched yet
3534                          * has 3430ES2-type clocks.
3535                          */
3536                         cpu_mask = RATE_IN_3430ES2PLUS;
3537                         cpu_clkflg = CK_3430ES2PLUS;
3538                 }
3539         } else {
3540                 WARN(1, "clock: could not identify OMAP3 variant\n");
3541         }
3542
3543         if (omap3_has_192mhz_clk())
3544                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3545
3546         if (cpu_is_omap3630()) {
3547                 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3548                 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3549                 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3550                 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3551                 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3552                 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3553         }
3554
3555         /*
3556          * XXX This type of dynamic rewriting of the clock tree is
3557          * deprecated and should be revised soon.
3558          */
3559         if (cpu_is_omap3630())
3560                 dpll4_dd = dpll4_dd_3630;
3561         else
3562                 dpll4_dd = dpll4_dd_34xx;
3563
3564         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3565              c++)
3566                 if (c->cpu & cpu_clkflg) {
3567                         clkdev_add(&c->lk);
3568                         if (!__clk_init(NULL, c->lk.clk))
3569                                 omap2_init_clk_hw_omap_clocks(c->lk.clk);
3570                 }
3571
3572         omap2_clk_disable_autoidle_all();
3573
3574         omap2_clk_enable_init_clocks(enable_init_clks,
3575                                      ARRAY_SIZE(enable_init_clks));
3576
3577         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3578                 (clk_get_rate(&osc_sys_ck) / 1000000),
3579                 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3580                 (clk_get_rate(&core_ck) / 1000000),
3581                 (clk_get_rate(&arm_fck) / 1000000));
3582
3583         /*
3584          * Lock DPLL5 -- here only until other device init code can
3585          * handle this
3586          */
3587         if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3588                 omap3_clk_lock_dpll5();
3589
3590         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3591         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3592         arm_fck_p = clk_get(NULL, "arm_fck");
3593
3594         return 0;
3595 }