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Merge branch 'x86-boot-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[karo-tx-linux.git] / arch / arm / mach-omap2 / clkt34xx_dpll3m2.c
1 /*
2  * OMAP34xx M2 divider clock code
3  *
4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
5  * Copyright (C) 2007-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Jouni Högander
9  *
10  * Parts of this code are based on code written by
11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License version 2 as
15  * published by the Free Software Foundation.
16  */
17 #undef DEBUG
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23
24 #include "clock.h"
25 #include "clock3xxx.h"
26 #include "sdrc.h"
27 #include "sram.h"
28
29 #define CYCLES_PER_MHZ                  1000000
30
31 struct clk *sdrc_ick_p, *arm_fck_p;
32
33 /*
34  * CORE DPLL (DPLL3) M2 divider rate programming functions
35  *
36  * These call into SRAM code to do the actual CM writes, since the SDRAM
37  * is clocked from DPLL3.
38  */
39
40 /**
41  * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
42  * @clk: struct clk * of DPLL to set
43  * @rate: rounded target rate
44  *
45  * Program the DPLL M2 divider with the rounded target rate.  Returns
46  * -EINVAL upon error, or 0 upon success.
47  */
48 int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
49                                         unsigned long parent_rate)
50 {
51         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
52         u32 new_div = 0;
53         u32 unlock_dll = 0;
54         u32 c;
55         unsigned long validrate, sdrcrate, _mpurate;
56         struct omap_sdrc_params *sdrc_cs0;
57         struct omap_sdrc_params *sdrc_cs1;
58         int ret;
59         unsigned long clkrate;
60
61         if (!clk || !rate)
62                 return -EINVAL;
63
64         new_div = DIV_ROUND_UP(parent_rate, rate);
65         validrate = parent_rate / new_div;
66
67         if (validrate != rate)
68                 return -EINVAL;
69
70         sdrcrate = clk_get_rate(sdrc_ick_p);
71         clkrate = clk_hw_get_rate(hw);
72         if (rate > clkrate)
73                 sdrcrate <<= ((rate / clkrate) >> 1);
74         else
75                 sdrcrate >>= ((clkrate / rate) >> 1);
76
77         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
78         if (ret)
79                 return -EINVAL;
80
81         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
82                 pr_debug("clock: will unlock SDRC DLL\n");
83                 unlock_dll = 1;
84         }
85
86         /*
87          * XXX This only needs to be done when the CPU frequency changes
88          */
89         _mpurate = clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
90         c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
91         c += 1;  /* for safety */
92         c *= SDRC_MPURATE_LOOPS;
93         c >>= SDRC_MPURATE_SCALE;
94         if (c == 0)
95                 c = 1;
96
97         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
98                  clkrate, validrate);
99         pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
100                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
101                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
102         if (sdrc_cs1)
103                 pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
104                          sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
105                          sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
106
107         if (sdrc_cs1)
108                 omap3_configure_core_dpll(
109                                   new_div, unlock_dll, c, rate > clkrate,
110                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
111                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
112                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
113                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
114         else
115                 omap3_configure_core_dpll(
116                                   new_div, unlock_dll, c, rate > clkrate,
117                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
118                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
119                                   0, 0, 0, 0);
120         return 0;
121 }
122