2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
28 #include <asm/mach-types.h>
29 #include <plat/gpmc.h>
31 #include <plat/sdrc.h>
33 /* GPMC register offsets */
34 #define GPMC_REVISION 0x00
35 #define GPMC_SYSCONFIG 0x10
36 #define GPMC_SYSSTATUS 0x14
37 #define GPMC_IRQSTATUS 0x18
38 #define GPMC_IRQENABLE 0x1c
39 #define GPMC_TIMEOUT_CONTROL 0x40
40 #define GPMC_ERR_ADDRESS 0x44
41 #define GPMC_ERR_TYPE 0x48
42 #define GPMC_CONFIG 0x50
43 #define GPMC_STATUS 0x54
44 #define GPMC_PREFETCH_CONFIG1 0x1e0
45 #define GPMC_PREFETCH_CONFIG2 0x1e4
46 #define GPMC_PREFETCH_CONTROL 0x1ec
47 #define GPMC_PREFETCH_STATUS 0x1f0
48 #define GPMC_ECC_CONFIG 0x1f4
49 #define GPMC_ECC_CONTROL 0x1f8
50 #define GPMC_ECC_SIZE_CONFIG 0x1fc
51 #define GPMC_ECC1_RESULT 0x200
52 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
54 /* GPMC ECC control settings */
55 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
56 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
57 #define GPMC_ECC_CTRL_ECCREG1 0x001
58 #define GPMC_ECC_CTRL_ECCREG2 0x002
59 #define GPMC_ECC_CTRL_ECCREG3 0x003
60 #define GPMC_ECC_CTRL_ECCREG4 0x004
61 #define GPMC_ECC_CTRL_ECCREG5 0x005
62 #define GPMC_ECC_CTRL_ECCREG6 0x006
63 #define GPMC_ECC_CTRL_ECCREG7 0x007
64 #define GPMC_ECC_CTRL_ECCREG8 0x008
65 #define GPMC_ECC_CTRL_ECCREG9 0x009
67 #define GPMC_CS0_OFFSET 0x60
68 #define GPMC_CS_SIZE 0x30
70 #define GPMC_MEM_START 0x00000000
71 #define GPMC_MEM_END 0x3FFFFFFF
72 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
74 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
75 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
77 #define CS_NUM_SHIFT 24
78 #define ENABLE_PREFETCH (0x1 << 7)
79 #define DMA_MPU_MODE 2
81 /* Structure to save gpmc cs context */
82 struct gpmc_cs_config {
94 * Structure to save/restore gpmc context
95 * to support core off on OMAP3
97 struct omap3_gpmc_regs {
102 u32 prefetch_config1;
103 u32 prefetch_config2;
104 u32 prefetch_control;
105 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
108 static struct resource gpmc_mem_root;
109 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
110 static DEFINE_SPINLOCK(gpmc_mem_lock);
111 static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
112 static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
114 static void __iomem *gpmc_base;
116 static struct clk *gpmc_l3_clk;
118 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
120 static void gpmc_write_reg(int idx, u32 val)
122 __raw_writel(val, gpmc_base + idx);
125 static u32 gpmc_read_reg(int idx)
127 return __raw_readl(gpmc_base + idx);
130 static void gpmc_cs_write_byte(int cs, int idx, u8 val)
132 void __iomem *reg_addr;
134 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
135 __raw_writeb(val, reg_addr);
138 static u8 gpmc_cs_read_byte(int cs, int idx)
140 void __iomem *reg_addr;
142 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
143 return __raw_readb(reg_addr);
146 void gpmc_cs_write_reg(int cs, int idx, u32 val)
148 void __iomem *reg_addr;
150 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
151 __raw_writel(val, reg_addr);
154 u32 gpmc_cs_read_reg(int cs, int idx)
156 void __iomem *reg_addr;
158 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
159 return __raw_readl(reg_addr);
162 /* TODO: Add support for gpmc_fck to clock framework and use it */
163 unsigned long gpmc_get_fclk_period(void)
165 unsigned long rate = clk_get_rate(gpmc_l3_clk);
168 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
173 rate = 1000000000 / rate; /* In picoseconds */
178 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
180 unsigned long tick_ps;
182 /* Calculate in picosecs to yield more exact results */
183 tick_ps = gpmc_get_fclk_period();
185 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
188 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
190 unsigned long tick_ps;
192 /* Calculate in picosecs to yield more exact results */
193 tick_ps = gpmc_get_fclk_period();
195 return (time_ps + tick_ps - 1) / tick_ps;
198 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
200 return ticks * gpmc_get_fclk_period() / 1000;
203 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
205 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
207 return ticks * gpmc_get_fclk_period() / 1000;
211 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
212 int time, const char *name)
214 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
219 int ticks, mask, nr_bits;
224 ticks = gpmc_ns_to_ticks(time);
225 nr_bits = end_bit - st_bit + 1;
226 if (ticks >= 1 << nr_bits) {
228 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
229 cs, name, time, ticks, 1 << nr_bits);
234 mask = (1 << nr_bits) - 1;
235 l = gpmc_cs_read_reg(cs, reg);
238 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
239 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
240 (l >> st_bit) & mask, time);
242 l &= ~(mask << st_bit);
243 l |= ticks << st_bit;
244 gpmc_cs_write_reg(cs, reg, l);
250 #define GPMC_SET_ONE(reg, st, end, field) \
251 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
252 t->field, #field) < 0) \
255 #define GPMC_SET_ONE(reg, st, end, field) \
256 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
260 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
265 l = sync_clk + (gpmc_get_fclk_period() - 1);
266 div = l / gpmc_get_fclk_period();
275 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
280 div = gpmc_cs_calc_divider(cs, t->sync_clk);
284 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
285 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
286 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
288 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
289 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
290 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
292 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
293 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
294 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
295 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
297 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
298 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
299 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
301 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
303 if (cpu_is_omap34xx()) {
304 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
305 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
308 /* caller is expected to have initialized CONFIG1 to cover
309 * at least sync vs async
311 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
312 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
314 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
315 cs, (div * gpmc_get_fclk_period()) / 1000, div);
319 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
325 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
330 mask = (1 << GPMC_SECTION_SHIFT) - size;
331 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
333 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
335 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
336 l |= GPMC_CONFIG7_CSVALID;
337 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
340 static void gpmc_cs_disable_mem(int cs)
344 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
345 l &= ~GPMC_CONFIG7_CSVALID;
346 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
349 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
354 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
355 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
356 mask = (l >> 8) & 0x0f;
357 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
360 static int gpmc_cs_mem_enabled(int cs)
364 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
365 return l & GPMC_CONFIG7_CSVALID;
368 int gpmc_cs_set_reserved(int cs, int reserved)
370 if (cs > GPMC_CS_NUM)
373 gpmc_cs_map &= ~(1 << cs);
374 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
379 int gpmc_cs_reserved(int cs)
381 if (cs > GPMC_CS_NUM)
384 return gpmc_cs_map & (1 << cs);
387 static unsigned long gpmc_mem_align(unsigned long size)
391 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
392 order = GPMC_CHUNK_SHIFT - 1;
401 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
403 struct resource *res = &gpmc_cs_mem[cs];
406 size = gpmc_mem_align(size);
407 spin_lock(&gpmc_mem_lock);
409 res->end = base + size - 1;
410 r = request_resource(&gpmc_mem_root, res);
411 spin_unlock(&gpmc_mem_lock);
416 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
418 struct resource *res = &gpmc_cs_mem[cs];
421 if (cs > GPMC_CS_NUM)
424 size = gpmc_mem_align(size);
425 if (size > (1 << GPMC_SECTION_SHIFT))
428 spin_lock(&gpmc_mem_lock);
429 if (gpmc_cs_reserved(cs)) {
433 if (gpmc_cs_mem_enabled(cs))
434 r = adjust_resource(res, res->start & ~(size - 1), size);
436 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
441 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
443 gpmc_cs_set_reserved(cs, 1);
445 spin_unlock(&gpmc_mem_lock);
448 EXPORT_SYMBOL(gpmc_cs_request);
450 void gpmc_cs_free(int cs)
452 spin_lock(&gpmc_mem_lock);
453 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
454 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
456 spin_unlock(&gpmc_mem_lock);
459 gpmc_cs_disable_mem(cs);
460 release_resource(&gpmc_cs_mem[cs]);
461 gpmc_cs_set_reserved(cs, 0);
462 spin_unlock(&gpmc_mem_lock);
464 EXPORT_SYMBOL(gpmc_cs_free);
467 * gpmc_read_status - read access request to get the different gpmc status
471 int gpmc_read_status(int cmd)
473 int status = -EINVAL;
477 case GPMC_GET_IRQ_STATUS:
478 status = gpmc_read_reg(GPMC_IRQSTATUS);
481 case GPMC_PREFETCH_FIFO_CNT:
482 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
483 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
486 case GPMC_PREFETCH_COUNT:
487 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
488 status = GPMC_PREFETCH_STATUS_COUNT(regval);
491 case GPMC_STATUS_BUFFER:
492 regval = gpmc_read_reg(GPMC_STATUS);
493 /* 1 : buffer is available to write */
494 status = regval & GPMC_STATUS_BUFF_EMPTY;
498 printk(KERN_ERR "gpmc_read_status: Not supported\n");
502 EXPORT_SYMBOL(gpmc_read_status);
505 * gpmc_cs_configure - write request to configure gpmc
506 * @cs: chip select number
508 * @wval: value to write
509 * @return status of the operation
511 int gpmc_cs_configure(int cs, int cmd, int wval)
517 case GPMC_ENABLE_IRQ:
518 gpmc_write_reg(GPMC_IRQENABLE, wval);
521 case GPMC_SET_IRQ_STATUS:
522 gpmc_write_reg(GPMC_IRQSTATUS, wval);
526 regval = gpmc_read_reg(GPMC_CONFIG);
528 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
530 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
531 gpmc_write_reg(GPMC_CONFIG, regval);
534 case GPMC_CONFIG_RDY_BSY:
535 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
537 regval |= WR_RD_PIN_MONITORING;
539 regval &= ~WR_RD_PIN_MONITORING;
540 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
543 case GPMC_CONFIG_DEV_SIZE:
544 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
546 /* clear 2 target bits */
547 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
549 /* set the proper value */
550 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
552 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
555 case GPMC_CONFIG_DEV_TYPE:
556 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
557 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
558 if (wval == GPMC_DEVICETYPE_NOR)
559 regval |= GPMC_CONFIG1_MUXADDDATA;
560 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
564 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
570 EXPORT_SYMBOL(gpmc_cs_configure);
573 * gpmc_nand_read - nand specific read access request
574 * @cs: chip select number
577 int gpmc_nand_read(int cs, int cmd)
583 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
587 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
591 EXPORT_SYMBOL(gpmc_nand_read);
594 * gpmc_nand_write - nand specific write request
595 * @cs: chip select number
597 * @wval: value to write
599 int gpmc_nand_write(int cs, int cmd, int wval)
604 case GPMC_NAND_COMMAND:
605 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
608 case GPMC_NAND_ADDRESS:
609 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
613 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
616 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
621 EXPORT_SYMBOL(gpmc_nand_write);
626 * gpmc_prefetch_enable - configures and starts prefetch transfer
627 * @cs: cs (chip select) number
628 * @fifo_th: fifo threshold to be used for read/ write
629 * @dma_mode: dma mode enable (1) or disable (0)
630 * @u32_count: number of bytes to be transferred
631 * @is_write: prefetch read(0) or write post(1) mode
633 int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
634 unsigned int u32_count, int is_write)
637 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
638 pr_err("gpmc: fifo threshold is not supported\n");
640 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
641 /* Set the amount of bytes to be prefetched */
642 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
644 /* Set dma/mpu mode, the prefetch read / post write and
645 * enable the engine. Set which cs is has requested for.
647 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
648 PREFETCH_FIFOTHRESHOLD(fifo_th) |
650 (dma_mode << DMA_MPU_MODE) |
653 /* Start the prefetch engine */
654 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
661 EXPORT_SYMBOL(gpmc_prefetch_enable);
664 * gpmc_prefetch_reset - disables and stops the prefetch engine
666 int gpmc_prefetch_reset(int cs)
670 /* check if the same module/cs is trying to reset */
671 config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
672 if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
675 /* Stop the PFPW engine */
676 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
678 /* Reset/disable the PFPW engine */
679 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
683 EXPORT_SYMBOL(gpmc_prefetch_reset);
685 static void __init gpmc_mem_init(void)
688 unsigned long boot_rom_space = 0;
690 /* never allocate the first page, to facilitate bug detection;
691 * even if we didn't boot from ROM.
693 boot_rom_space = BOOT_ROM_SPACE;
694 /* In apollon the CS0 is mapped as 0x0000 0000 */
695 if (machine_is_omap_apollon())
697 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
698 gpmc_mem_root.end = GPMC_MEM_END;
700 /* Reserve all regions that has been set up by bootloader */
701 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
704 if (!gpmc_cs_mem_enabled(cs))
706 gpmc_cs_get_memconf(cs, &base, &size);
707 if (gpmc_cs_insert_mem(cs, base, size) < 0)
712 static int __init gpmc_init(void)
715 int cs, ret = -EINVAL;
719 if (cpu_is_omap24xx()) {
721 if (cpu_is_omap2420())
722 l = OMAP2420_GPMC_BASE;
724 l = OMAP34XX_GPMC_BASE;
725 gpmc_irq = INT_34XX_GPMC_IRQ;
726 } else if (cpu_is_omap34xx()) {
728 l = OMAP34XX_GPMC_BASE;
729 gpmc_irq = INT_34XX_GPMC_IRQ;
730 } else if (cpu_is_omap44xx()) {
732 l = OMAP44XX_GPMC_BASE;
733 gpmc_irq = OMAP44XX_IRQ_GPMC;
739 gpmc_l3_clk = clk_get(NULL, ck);
740 if (IS_ERR(gpmc_l3_clk)) {
741 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
745 gpmc_base = ioremap(l, SZ_4K);
747 clk_put(gpmc_l3_clk);
748 printk(KERN_ERR "Could not get GPMC register memory\n");
752 clk_enable(gpmc_l3_clk);
754 l = gpmc_read_reg(GPMC_REVISION);
755 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
756 /* Set smart idle mode and automatic L3 clock gating */
757 l = gpmc_read_reg(GPMC_SYSCONFIG);
759 l |= (0x02 << 3) | (1 << 0);
760 gpmc_write_reg(GPMC_SYSCONFIG, l);
763 /* initalize the irq_chained */
764 irq = OMAP_GPMC_IRQ_BASE;
765 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
766 irq_set_chip_and_handler(irq, &dummy_irq_chip,
768 set_irq_flags(irq, IRQF_VALID);
772 ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
774 pr_err("gpmc: irq-%d could not claim: err %d\n",
778 postcore_initcall(gpmc_init);
780 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
784 /* check cs to invoke the irq */
785 cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
786 if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
787 generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
792 #ifdef CONFIG_ARCH_OMAP3
793 static struct omap3_gpmc_regs gpmc_context;
795 void omap3_gpmc_save_context(void)
799 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
800 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
801 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
802 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
803 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
804 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
805 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
806 for (i = 0; i < GPMC_CS_NUM; i++) {
807 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
808 if (gpmc_context.cs_context[i].is_valid) {
809 gpmc_context.cs_context[i].config1 =
810 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
811 gpmc_context.cs_context[i].config2 =
812 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
813 gpmc_context.cs_context[i].config3 =
814 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
815 gpmc_context.cs_context[i].config4 =
816 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
817 gpmc_context.cs_context[i].config5 =
818 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
819 gpmc_context.cs_context[i].config6 =
820 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
821 gpmc_context.cs_context[i].config7 =
822 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
827 void omap3_gpmc_restore_context(void)
831 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
832 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
833 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
834 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
835 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
836 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
837 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
838 for (i = 0; i < GPMC_CS_NUM; i++) {
839 if (gpmc_context.cs_context[i].is_valid) {
840 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
841 gpmc_context.cs_context[i].config1);
842 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
843 gpmc_context.cs_context[i].config2);
844 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
845 gpmc_context.cs_context[i].config3);
846 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
847 gpmc_context.cs_context[i].config4);
848 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
849 gpmc_context.cs_context[i].config5);
850 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
851 gpmc_context.cs_context[i].config6);
852 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
853 gpmc_context.cs_context[i].config7);
857 #endif /* CONFIG_ARCH_OMAP3 */
860 * gpmc_enable_hwecc - enable hardware ecc functionality
861 * @cs: chip select number
862 * @mode: read/write mode
863 * @dev_width: device bus width(1 for x16, 0 for x8)
864 * @ecc_size: bytes for which ECC will be generated
866 int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
870 /* check if ecc module is in used */
871 if (gpmc_ecc_used != -EINVAL)
876 /* clear ecc and enable bits */
877 gpmc_write_reg(GPMC_ECC_CONTROL,
878 GPMC_ECC_CTRL_ECCCLEAR |
879 GPMC_ECC_CTRL_ECCREG1);
881 /* program ecc and result sizes */
882 val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
883 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
888 gpmc_write_reg(GPMC_ECC_CONTROL,
889 GPMC_ECC_CTRL_ECCCLEAR |
890 GPMC_ECC_CTRL_ECCREG1);
892 case GPMC_ECC_READSYN:
893 gpmc_write_reg(GPMC_ECC_CONTROL,
894 GPMC_ECC_CTRL_ECCCLEAR |
895 GPMC_ECC_CTRL_ECCDISABLE);
898 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
902 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
903 val = (dev_width << 7) | (cs << 1) | (0x1);
904 gpmc_write_reg(GPMC_ECC_CONFIG, val);
907 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
910 * gpmc_calculate_ecc - generate non-inverted ecc bytes
911 * @cs: chip select number
912 * @dat: data pointer over which ecc is computed
913 * @ecc_code: ecc code buffer
915 * Using non-inverted ECC is considered ugly since writing a blank
916 * page (padding) will clear the ECC bytes. This is not a problem as long
917 * no one is trying to write data on the seemingly unused page. Reading
918 * an erased page will produce an ECC mismatch between generated and read
919 * ECC bytes that has to be dealt with separately.
921 int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
923 unsigned int val = 0x0;
925 if (gpmc_ecc_used != cs)
928 /* read ecc result */
929 val = gpmc_read_reg(GPMC_ECC1_RESULT);
930 *ecc_code++ = val; /* P128e, ..., P1e */
931 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
932 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
933 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
935 gpmc_ecc_used = -EINVAL;
938 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
940 #ifdef CONFIG_ARCH_OMAP3
943 * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
944 * @cs: chip select number
945 * @nsectors: how many 512-byte sectors to process
946 * @nerrors: how many errors to correct per sector (4 or 8)
948 * This function must be executed before any call to gpmc_enable_hwecc_bch.
950 int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
952 /* check if ecc module is in use */
953 if (gpmc_ecc_used != -EINVAL)
956 /* support only OMAP3 class */
957 if (!cpu_is_omap34xx()) {
958 printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
963 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
964 * Other chips may be added if confirmed to work.
966 if ((nerrors == 4) &&
967 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
968 printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
974 printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
981 EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
984 * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
985 * @cs: chip select number
986 * @mode: read/write mode
987 * @dev_width: device bus width(1 for x16, 0 for x8)
988 * @nsectors: how many 512-byte sectors to process
989 * @nerrors: how many errors to correct per sector (4 or 8)
991 int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
996 /* check if ecc module is in use */
997 if (gpmc_ecc_used != -EINVAL)
1002 /* clear ecc and enable bits */
1003 gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
1006 * When using BCH, sector size is hardcoded to 512 bytes.
1007 * Here we are using wrapping mode 6 both for reading and writing, with:
1008 * size0 = 0 (no additional protected byte in spare area)
1009 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1011 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
1013 /* BCH configuration */
1014 val = ((1 << 16) | /* enable BCH */
1015 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1016 (0x06 << 8) | /* wrap mode = 6 */
1017 (dev_width << 7) | /* bus width */
1018 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1019 (cs << 1) | /* ECC CS */
1020 (0x1)); /* enable ECC */
1022 gpmc_write_reg(GPMC_ECC_CONFIG, val);
1023 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
1026 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
1029 * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1030 * @cs: chip select number
1031 * @dat: The pointer to data on which ecc is computed
1032 * @ecc: The ecc output buffer
1034 int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
1037 unsigned long nsectors, reg, val1, val2;
1039 if (gpmc_ecc_used != cs)
1042 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1044 for (i = 0; i < nsectors; i++) {
1046 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1048 /* Read hw-computed remainder */
1049 val1 = gpmc_read_reg(reg + 0);
1050 val2 = gpmc_read_reg(reg + 4);
1053 * Add constant polynomial to remainder, in order to get an ecc
1054 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1055 * left-justify the resulting polynomial.
1057 *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1058 *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1059 *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1060 *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1061 *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1062 *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
1063 *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
1066 gpmc_ecc_used = -EINVAL;
1069 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
1072 * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1073 * @cs: chip select number
1074 * @dat: The pointer to data on which ecc is computed
1075 * @ecc: The ecc output buffer
1077 int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
1080 unsigned long nsectors, reg, val1, val2, val3, val4;
1082 if (gpmc_ecc_used != cs)
1085 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1087 for (i = 0; i < nsectors; i++) {
1089 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1091 /* Read hw-computed remainder */
1092 val1 = gpmc_read_reg(reg + 0);
1093 val2 = gpmc_read_reg(reg + 4);
1094 val3 = gpmc_read_reg(reg + 8);
1095 val4 = gpmc_read_reg(reg + 12);
1098 * Add constant polynomial to remainder, in order to get an ecc
1099 * sequence of 0xFFs for a buffer filled with 0xFFs.
1101 *ecc++ = 0xef ^ (val4 & 0xFF);
1102 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1103 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1104 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1105 *ecc++ = 0xed ^ (val3 & 0xFF);
1106 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1107 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1108 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1109 *ecc++ = 0x97 ^ (val2 & 0xFF);
1110 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1111 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1112 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1113 *ecc++ = 0xb5 ^ (val1 & 0xFF);
1116 gpmc_ecc_used = -EINVAL;
1119 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
1121 #endif /* CONFIG_ARCH_OMAP3 */