arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod dra7xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &dra7xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2
  75  */
  76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &dra7xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &dra7xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &dra7xx_l3_hwmod_class,
 111         .clkdm_name     = "l3instr_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 116                         .modulemode   = MODULEMODE_HWCTRL,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l4' class
 123  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 124  */
 125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 126         .name   = "l4",
 127 };
 128
 129 /* l4_cfg */
 130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 131         .name           = "l4_cfg",
 132         .class          = &dra7xx_l4_hwmod_class,
 133         .clkdm_name     = "l4cfg_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 137                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /* l4_per1 */
 143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 144         .name           = "l4_per1",
 145         .class          = &dra7xx_l4_hwmod_class,
 146         .clkdm_name     = "l4per_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per2 */
 156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 157         .name           = "l4_per2",
 158         .class          = &dra7xx_l4_hwmod_class,
 159         .clkdm_name     = "l4per2_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 163                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per3 */
 169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 170         .name           = "l4_per3",
 171         .class          = &dra7xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per3_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 176                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &dra7xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'atl' class
 196  *
 197  */
 198
 199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 200         .name   = "atl",
 201 };
 202
 203 /* atl */
 204 static struct omap_hwmod dra7xx_atl_hwmod = {
 205         .name           = "atl",
 206         .class          = &dra7xx_atl_hwmod_class,
 207         .clkdm_name     = "atl_clkdm",
 208         .main_clk       = "atl_gfclk_mux",
 209         .prcm = {
 210                 .omap4 = {
 211                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 212                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 213                         .modulemode   = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 /*
 219  * 'bb2d' class
 220  *
 221  */
 222
 223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 224         .name   = "bb2d",
 225 };
 226
 227 /* bb2d */
 228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 229         .name           = "bb2d",
 230         .class          = &dra7xx_bb2d_hwmod_class,
 231         .clkdm_name     = "dss_clkdm",
 232         .main_clk       = "dpll_core_h24x2_ck",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 236                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_SWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'counter' class
 244  *
 245  */
 246
 247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 248         .rev_offs       = 0x0000,
 249         .sysc_offs      = 0x0010,
 250         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 252                            SIDLE_SMART_WKUP),
 253         .sysc_fields    = &omap_hwmod_sysc_type1,
 254 };
 255
 256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 257         .name   = "counter",
 258         .sysc   = &dra7xx_counter_sysc,
 259 };
 260
 261 /* counter_32k */
 262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 263         .name           = "counter_32k",
 264         .class          = &dra7xx_counter_hwmod_class,
 265         .clkdm_name     = "wkupaon_clkdm",
 266         .flags          = HWMOD_SWSUP_SIDLE,
 267         .main_clk       = "wkupaon_iclk_mux",
 268         .prcm = {
 269                 .omap4 = {
 270                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 271                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'ctrl_module' class
 278  *
 279  */
 280
 281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 282         .name   = "ctrl_module",
 283 };
 284
 285 /* ctrl_module_wkup */
 286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 287         .name           = "ctrl_module_wkup",
 288         .class          = &dra7xx_ctrl_module_hwmod_class,
 289         .clkdm_name     = "wkupaon_clkdm",
 290         .prcm = {
 291                 .omap4 = {
 292                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * 'gmac' class
 299  * cpsw/gmac sub system
 300  */
 301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 302         .rev_offs       = 0x0,
 303         .sysc_offs      = 0x8,
 304         .syss_offs      = 0x4,
 305         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 306                            SYSS_HAS_RESET_STATUS),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 308                            MSTANDBY_NO),
 309         .sysc_fields    = &omap_hwmod_sysc_type3,
 310 };
 311
 312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 313         .name           = "gmac",
 314         .sysc           = &dra7xx_gmac_sysc,
 315 };
 316
 317 static struct omap_hwmod dra7xx_gmac_hwmod = {
 318         .name           = "gmac",
 319         .class          = &dra7xx_gmac_hwmod_class,
 320         .clkdm_name     = "gmac_clkdm",
 321         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 322         .main_clk       = "dpll_gmac_ck",
 323         .mpu_rt_idx     = 1,
 324         .prcm           = {
 325                 .omap4  = {
 326                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 327                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 328                         .modulemode     = MODULEMODE_SWCTRL,
 329                 },
 330         },
 331 };
 332
 333 /*
 334  * 'mdio' class
 335  */
 336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 337         .name           = "davinci_mdio",
 338 };
 339
 340 static struct omap_hwmod dra7xx_mdio_hwmod = {
 341         .name           = "davinci_mdio",
 342         .class          = &dra7xx_mdio_hwmod_class,
 343         .clkdm_name     = "gmac_clkdm",
 344         .main_clk       = "dpll_gmac_ck",
 345 };
 346
 347 /*
 348  * 'dcan' class
 349  *
 350  */
 351
 352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 353         .name   = "dcan",
 354 };
 355
 356 /* dcan1 */
 357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 358         .name           = "dcan1",
 359         .class          = &dra7xx_dcan_hwmod_class,
 360         .clkdm_name     = "wkupaon_clkdm",
 361         .main_clk       = "dcan1_sys_clk_mux",
 362         .prcm = {
 363                 .omap4 = {
 364                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 365                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 366                         .modulemode   = MODULEMODE_SWCTRL,
 367                 },
 368         },
 369 };
 370
 371 /* dcan2 */
 372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 373         .name           = "dcan2",
 374         .class          = &dra7xx_dcan_hwmod_class,
 375         .clkdm_name     = "l4per2_clkdm",
 376         .main_clk       = "sys_clkin1",
 377         .prcm = {
 378                 .omap4 = {
 379                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 380                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 381                         .modulemode   = MODULEMODE_SWCTRL,
 382                 },
 383         },
 384 };
 385
 386 /*
 387  * 'dma' class
 388  *
 389  */
 390
 391 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 392         .rev_offs       = 0x0000,
 393         .sysc_offs      = 0x002c,
 394         .syss_offs      = 0x0028,
 395         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 396                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 397                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 398                            SYSS_HAS_RESET_STATUS),
 399         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 400                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 401                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 402         .sysc_fields    = &omap_hwmod_sysc_type1,
 403 };
 404
 405 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 406         .name   = "dma",
 407         .sysc   = &dra7xx_dma_sysc,
 408 };
 409
 410 /* dma dev_attr */
 411 static struct omap_dma_dev_attr dma_dev_attr = {
 412         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 413                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 414         .lch_count      = 32,
 415 };
 416
 417 /* dma_system */
 418 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 419         .name           = "dma_system",
 420         .class          = &dra7xx_dma_hwmod_class,
 421         .clkdm_name     = "dma_clkdm",
 422         .main_clk       = "l3_iclk_div",
 423         .prcm = {
 424                 .omap4 = {
 425                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 426                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 427                 },
 428         },
 429         .dev_attr       = &dma_dev_attr,
 430 };
 431
 432 /*
 433  * 'dss' class
 434  *
 435  */
 436
 437 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 438         .rev_offs       = 0x0000,
 439         .syss_offs      = 0x0014,
 440         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 441 };
 442
 443 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 444         .name   = "dss",
 445         .sysc   = &dra7xx_dss_sysc,
 446         .reset  = omap_dss_reset,
 447 };
 448
 449 /* dss */
 450 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 451         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 452         { .dma_req = -1 }
 453 };
 454
 455 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 456         { .role = "dss_clk", .clk = "dss_dss_clk" },
 457         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 458         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 459         { .role = "video2_clk", .clk = "dss_video2_clk" },
 460         { .role = "video1_clk", .clk = "dss_video1_clk" },
 461         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 462         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 463 };
 464
 465 static struct omap_hwmod dra7xx_dss_hwmod = {
 466         .name           = "dss_core",
 467         .class          = &dra7xx_dss_hwmod_class,
 468         .clkdm_name     = "dss_clkdm",
 469         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 470         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 471         .main_clk       = "dss_dss_clk",
 472         .prcm = {
 473                 .omap4 = {
 474                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 475                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 476                         .modulemode   = MODULEMODE_SWCTRL,
 477                 },
 478         },
 479         .opt_clks       = dss_opt_clks,
 480         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 481 };
 482
 483 /*
 484  * 'dispc' class
 485  * display controller
 486  */
 487
 488 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 489         .rev_offs       = 0x0000,
 490         .sysc_offs      = 0x0010,
 491         .syss_offs      = 0x0014,
 492         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 493                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 494                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 495                            SYSS_HAS_RESET_STATUS),
 496         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 497                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 498         .sysc_fields    = &omap_hwmod_sysc_type1,
 499 };
 500
 501 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 502         .name   = "dispc",
 503         .sysc   = &dra7xx_dispc_sysc,
 504 };
 505
 506 /* dss_dispc */
 507 /* dss_dispc dev_attr */
 508 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 509         .has_framedonetv_irq    = 1,
 510         .manager_count          = 4,
 511 };
 512
 513 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 514         .name           = "dss_dispc",
 515         .class          = &dra7xx_dispc_hwmod_class,
 516         .clkdm_name     = "dss_clkdm",
 517         .main_clk       = "dss_dss_clk",
 518         .prcm = {
 519                 .omap4 = {
 520                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 521                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 522                 },
 523         },
 524         .dev_attr       = &dss_dispc_dev_attr,
 525         .parent_hwmod   = &dra7xx_dss_hwmod,
 526 };
 527
 528 /*
 529  * 'hdmi' class
 530  * hdmi controller
 531  */
 532
 533 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 534         .rev_offs       = 0x0000,
 535         .sysc_offs      = 0x0010,
 536         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 537                            SYSC_HAS_SOFTRESET),
 538         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 539                            SIDLE_SMART_WKUP),
 540         .sysc_fields    = &omap_hwmod_sysc_type2,
 541 };
 542
 543 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 544         .name   = "hdmi",
 545         .sysc   = &dra7xx_hdmi_sysc,
 546 };
 547
 548 /* dss_hdmi */
 549
 550 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 551         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 552 };
 553
 554 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 555         .name           = "dss_hdmi",
 556         .class          = &dra7xx_hdmi_hwmod_class,
 557         .clkdm_name     = "dss_clkdm",
 558         .main_clk       = "dss_48mhz_clk",
 559         .prcm = {
 560                 .omap4 = {
 561                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 562                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 563                 },
 564         },
 565         .opt_clks       = dss_hdmi_opt_clks,
 566         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 567         .parent_hwmod   = &dra7xx_dss_hwmod,
 568 };
 569
 570 /*
 571  * 'elm' class
 572  *
 573  */
 574
 575 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 576         .rev_offs       = 0x0000,
 577         .sysc_offs      = 0x0010,
 578         .syss_offs      = 0x0014,
 579         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 580                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 581                            SYSS_HAS_RESET_STATUS),
 582         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 583                            SIDLE_SMART_WKUP),
 584         .sysc_fields    = &omap_hwmod_sysc_type1,
 585 };
 586
 587 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 588         .name   = "elm",
 589         .sysc   = &dra7xx_elm_sysc,
 590 };
 591
 592 /* elm */
 593
 594 static struct omap_hwmod dra7xx_elm_hwmod = {
 595         .name           = "elm",
 596         .class          = &dra7xx_elm_hwmod_class,
 597         .clkdm_name     = "l4per_clkdm",
 598         .main_clk       = "l3_iclk_div",
 599         .prcm = {
 600                 .omap4 = {
 601                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 602                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 603                 },
 604         },
 605 };
 606
 607 /*
 608  * 'gpio' class
 609  *
 610  */
 611
 612 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 613         .rev_offs       = 0x0000,
 614         .sysc_offs      = 0x0010,
 615         .syss_offs      = 0x0114,
 616         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 617                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 618                            SYSS_HAS_RESET_STATUS),
 619         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 620                            SIDLE_SMART_WKUP),
 621         .sysc_fields    = &omap_hwmod_sysc_type1,
 622 };
 623
 624 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 625         .name   = "gpio",
 626         .sysc   = &dra7xx_gpio_sysc,
 627         .rev    = 2,
 628 };
 629
 630 /* gpio dev_attr */
 631 static struct omap_gpio_dev_attr gpio_dev_attr = {
 632         .bank_width     = 32,
 633         .dbck_flag      = true,
 634 };
 635
 636 /* gpio1 */
 637 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 638         { .role = "dbclk", .clk = "gpio1_dbclk" },
 639 };
 640
 641 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 642         .name           = "gpio1",
 643         .class          = &dra7xx_gpio_hwmod_class,
 644         .clkdm_name     = "wkupaon_clkdm",
 645         .main_clk       = "wkupaon_iclk_mux",
 646         .prcm = {
 647                 .omap4 = {
 648                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 649                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 650                         .modulemode   = MODULEMODE_HWCTRL,
 651                 },
 652         },
 653         .opt_clks       = gpio1_opt_clks,
 654         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 655         .dev_attr       = &gpio_dev_attr,
 656 };
 657
 658 /* gpio2 */
 659 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 660         { .role = "dbclk", .clk = "gpio2_dbclk" },
 661 };
 662
 663 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 664         .name           = "gpio2",
 665         .class          = &dra7xx_gpio_hwmod_class,
 666         .clkdm_name     = "l4per_clkdm",
 667         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 668         .main_clk       = "l3_iclk_div",
 669         .prcm = {
 670                 .omap4 = {
 671                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 672                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 673                         .modulemode   = MODULEMODE_HWCTRL,
 674                 },
 675         },
 676         .opt_clks       = gpio2_opt_clks,
 677         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 678         .dev_attr       = &gpio_dev_attr,
 679 };
 680
 681 /* gpio3 */
 682 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 683         { .role = "dbclk", .clk = "gpio3_dbclk" },
 684 };
 685
 686 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 687         .name           = "gpio3",
 688         .class          = &dra7xx_gpio_hwmod_class,
 689         .clkdm_name     = "l4per_clkdm",
 690         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 691         .main_clk       = "l3_iclk_div",
 692         .prcm = {
 693                 .omap4 = {
 694                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 695                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 696                         .modulemode   = MODULEMODE_HWCTRL,
 697                 },
 698         },
 699         .opt_clks       = gpio3_opt_clks,
 700         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 701         .dev_attr       = &gpio_dev_attr,
 702 };
 703
 704 /* gpio4 */
 705 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 706         { .role = "dbclk", .clk = "gpio4_dbclk" },
 707 };
 708
 709 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 710         .name           = "gpio4",
 711         .class          = &dra7xx_gpio_hwmod_class,
 712         .clkdm_name     = "l4per_clkdm",
 713         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 714         .main_clk       = "l3_iclk_div",
 715         .prcm = {
 716                 .omap4 = {
 717                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 718                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 719                         .modulemode   = MODULEMODE_HWCTRL,
 720                 },
 721         },
 722         .opt_clks       = gpio4_opt_clks,
 723         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 724         .dev_attr       = &gpio_dev_attr,
 725 };
 726
 727 /* gpio5 */
 728 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 729         { .role = "dbclk", .clk = "gpio5_dbclk" },
 730 };
 731
 732 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 733         .name           = "gpio5",
 734         .class          = &dra7xx_gpio_hwmod_class,
 735         .clkdm_name     = "l4per_clkdm",
 736         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 737         .main_clk       = "l3_iclk_div",
 738         .prcm = {
 739                 .omap4 = {
 740                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 741                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 742                         .modulemode   = MODULEMODE_HWCTRL,
 743                 },
 744         },
 745         .opt_clks       = gpio5_opt_clks,
 746         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 747         .dev_attr       = &gpio_dev_attr,
 748 };
 749
 750 /* gpio6 */
 751 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 752         { .role = "dbclk", .clk = "gpio6_dbclk" },
 753 };
 754
 755 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 756         .name           = "gpio6",
 757         .class          = &dra7xx_gpio_hwmod_class,
 758         .clkdm_name     = "l4per_clkdm",
 759         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 760         .main_clk       = "l3_iclk_div",
 761         .prcm = {
 762                 .omap4 = {
 763                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 764                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 765                         .modulemode   = MODULEMODE_HWCTRL,
 766                 },
 767         },
 768         .opt_clks       = gpio6_opt_clks,
 769         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 770         .dev_attr       = &gpio_dev_attr,
 771 };
 772
 773 /* gpio7 */
 774 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 775         { .role = "dbclk", .clk = "gpio7_dbclk" },
 776 };
 777
 778 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 779         .name           = "gpio7",
 780         .class          = &dra7xx_gpio_hwmod_class,
 781         .clkdm_name     = "l4per_clkdm",
 782         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 783         .main_clk       = "l3_iclk_div",
 784         .prcm = {
 785                 .omap4 = {
 786                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 787                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 788                         .modulemode   = MODULEMODE_HWCTRL,
 789                 },
 790         },
 791         .opt_clks       = gpio7_opt_clks,
 792         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 793         .dev_attr       = &gpio_dev_attr,
 794 };
 795
 796 /* gpio8 */
 797 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 798         { .role = "dbclk", .clk = "gpio8_dbclk" },
 799 };
 800
 801 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 802         .name           = "gpio8",
 803         .class          = &dra7xx_gpio_hwmod_class,
 804         .clkdm_name     = "l4per_clkdm",
 805         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 806         .main_clk       = "l3_iclk_div",
 807         .prcm = {
 808                 .omap4 = {
 809                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 810                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 811                         .modulemode   = MODULEMODE_HWCTRL,
 812                 },
 813         },
 814         .opt_clks       = gpio8_opt_clks,
 815         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 816         .dev_attr       = &gpio_dev_attr,
 817 };
 818
 819 /*
 820  * 'gpmc' class
 821  *
 822  */
 823
 824 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
 825         .rev_offs       = 0x0000,
 826         .sysc_offs      = 0x0010,
 827         .syss_offs      = 0x0014,
 828         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 829                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 830         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 831                            SIDLE_SMART_WKUP),
 832         .sysc_fields    = &omap_hwmod_sysc_type1,
 833 };
 834
 835 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
 836         .name   = "gpmc",
 837         .sysc   = &dra7xx_gpmc_sysc,
 838 };
 839
 840 /* gpmc */
 841
 842 static struct omap_hwmod dra7xx_gpmc_hwmod = {
 843         .name           = "gpmc",
 844         .class          = &dra7xx_gpmc_hwmod_class,
 845         .clkdm_name     = "l3main1_clkdm",
 846         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 847         .flags          = HWMOD_SWSUP_SIDLE | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 848         .main_clk       = "l3_iclk_div",
 849         .prcm = {
 850                 .omap4 = {
 851                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
 852                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
 853                         .modulemode   = MODULEMODE_HWCTRL,
 854                 },
 855         },
 856 };
 857
 858 /*
 859  * 'hdq1w' class
 860  *
 861  */
 862
 863 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
 864         .rev_offs       = 0x0000,
 865         .sysc_offs      = 0x0014,
 866         .syss_offs      = 0x0018,
 867         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 868                            SYSS_HAS_RESET_STATUS),
 869         .sysc_fields    = &omap_hwmod_sysc_type1,
 870 };
 871
 872 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
 873         .name   = "hdq1w",
 874         .sysc   = &dra7xx_hdq1w_sysc,
 875 };
 876
 877 /* hdq1w */
 878
 879 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
 880         .name           = "hdq1w",
 881         .class          = &dra7xx_hdq1w_hwmod_class,
 882         .clkdm_name     = "l4per_clkdm",
 883         .flags          = HWMOD_INIT_NO_RESET,
 884         .main_clk       = "func_12m_fclk",
 885         .prcm = {
 886                 .omap4 = {
 887                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
 888                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
 889                         .modulemode   = MODULEMODE_SWCTRL,
 890                 },
 891         },
 892 };
 893
 894 /*
 895  * 'i2c' class
 896  *
 897  */
 898
 899 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
 900         .sysc_offs      = 0x0010,
 901         .syss_offs      = 0x0090,
 902         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 903                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 904                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 905         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 906                            SIDLE_SMART_WKUP),
 907         .clockact       = CLOCKACT_TEST_ICLK,
 908         .sysc_fields    = &omap_hwmod_sysc_type1,
 909 };
 910
 911 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
 912         .name   = "i2c",
 913         .sysc   = &dra7xx_i2c_sysc,
 914         .reset  = &omap_i2c_reset,
 915         .rev    = OMAP_I2C_IP_VERSION_2,
 916 };
 917
 918 /* i2c dev_attr */
 919 static struct omap_i2c_dev_attr i2c_dev_attr = {
 920         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 921 };
 922
 923 /* i2c1 */
 924 static struct omap_hwmod dra7xx_i2c1_hwmod = {
 925         .name           = "i2c1",
 926         .class          = &dra7xx_i2c_hwmod_class,
 927         .clkdm_name     = "l4per_clkdm",
 928         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 929         .main_clk       = "func_96m_fclk",
 930         .prcm = {
 931                 .omap4 = {
 932                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 933                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 934                         .modulemode   = MODULEMODE_SWCTRL,
 935                 },
 936         },
 937         .dev_attr       = &i2c_dev_attr,
 938 };
 939
 940 /* i2c2 */
 941 static struct omap_hwmod dra7xx_i2c2_hwmod = {
 942         .name           = "i2c2",
 943         .class          = &dra7xx_i2c_hwmod_class,
 944         .clkdm_name     = "l4per_clkdm",
 945         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 946         .main_clk       = "func_96m_fclk",
 947         .prcm = {
 948                 .omap4 = {
 949                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 950                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 951                         .modulemode   = MODULEMODE_SWCTRL,
 952                 },
 953         },
 954         .dev_attr       = &i2c_dev_attr,
 955 };
 956
 957 /* i2c3 */
 958 static struct omap_hwmod dra7xx_i2c3_hwmod = {
 959         .name           = "i2c3",
 960         .class          = &dra7xx_i2c_hwmod_class,
 961         .clkdm_name     = "l4per_clkdm",
 962         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 963         .main_clk       = "func_96m_fclk",
 964         .prcm = {
 965                 .omap4 = {
 966                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 967                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 968                         .modulemode   = MODULEMODE_SWCTRL,
 969                 },
 970         },
 971         .dev_attr       = &i2c_dev_attr,
 972 };
 973
 974 /* i2c4 */
 975 static struct omap_hwmod dra7xx_i2c4_hwmod = {
 976         .name           = "i2c4",
 977         .class          = &dra7xx_i2c_hwmod_class,
 978         .clkdm_name     = "l4per_clkdm",
 979         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 980         .main_clk       = "func_96m_fclk",
 981         .prcm = {
 982                 .omap4 = {
 983                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 984                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 985                         .modulemode   = MODULEMODE_SWCTRL,
 986                 },
 987         },
 988         .dev_attr       = &i2c_dev_attr,
 989 };
 990
 991 /* i2c5 */
 992 static struct omap_hwmod dra7xx_i2c5_hwmod = {
 993         .name           = "i2c5",
 994         .class          = &dra7xx_i2c_hwmod_class,
 995         .clkdm_name     = "ipu_clkdm",
 996         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 997         .main_clk       = "func_96m_fclk",
 998         .prcm = {
 999                 .omap4 = {
1000                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1001                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1002                         .modulemode   = MODULEMODE_SWCTRL,
1003                 },
1004         },
1005         .dev_attr       = &i2c_dev_attr,
1006 };
1007
1008 /*
1009  * 'mailbox' class
1010  *
1011  */
1012
1013 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1014         .rev_offs       = 0x0000,
1015         .sysc_offs      = 0x0010,
1016         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1017                            SYSC_HAS_SOFTRESET),
1018         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1019         .sysc_fields    = &omap_hwmod_sysc_type2,
1020 };
1021
1022 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1023         .name   = "mailbox",
1024         .sysc   = &dra7xx_mailbox_sysc,
1025 };
1026
1027 /* mailbox1 */
1028 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1029         .name           = "mailbox1",
1030         .class          = &dra7xx_mailbox_hwmod_class,
1031         .clkdm_name     = "l4cfg_clkdm",
1032         .prcm = {
1033                 .omap4 = {
1034                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1035                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1036                 },
1037         },
1038 };
1039
1040 /* mailbox2 */
1041 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1042         .name           = "mailbox2",
1043         .class          = &dra7xx_mailbox_hwmod_class,
1044         .clkdm_name     = "l4cfg_clkdm",
1045         .prcm = {
1046                 .omap4 = {
1047                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1048                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1049                 },
1050         },
1051 };
1052
1053 /* mailbox3 */
1054 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1055         .name           = "mailbox3",
1056         .class          = &dra7xx_mailbox_hwmod_class,
1057         .clkdm_name     = "l4cfg_clkdm",
1058         .prcm = {
1059                 .omap4 = {
1060                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1061                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1062                 },
1063         },
1064 };
1065
1066 /* mailbox4 */
1067 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1068         .name           = "mailbox4",
1069         .class          = &dra7xx_mailbox_hwmod_class,
1070         .clkdm_name     = "l4cfg_clkdm",
1071         .prcm = {
1072                 .omap4 = {
1073                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1074                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1075                 },
1076         },
1077 };
1078
1079 /* mailbox5 */
1080 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1081         .name           = "mailbox5",
1082         .class          = &dra7xx_mailbox_hwmod_class,
1083         .clkdm_name     = "l4cfg_clkdm",
1084         .prcm = {
1085                 .omap4 = {
1086                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1087                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1088                 },
1089         },
1090 };
1091
1092 /* mailbox6 */
1093 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1094         .name           = "mailbox6",
1095         .class          = &dra7xx_mailbox_hwmod_class,
1096         .clkdm_name     = "l4cfg_clkdm",
1097         .prcm = {
1098                 .omap4 = {
1099                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1100                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1101                 },
1102         },
1103 };
1104
1105 /* mailbox7 */
1106 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1107         .name           = "mailbox7",
1108         .class          = &dra7xx_mailbox_hwmod_class,
1109         .clkdm_name     = "l4cfg_clkdm",
1110         .prcm = {
1111                 .omap4 = {
1112                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1113                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1114                 },
1115         },
1116 };
1117
1118 /* mailbox8 */
1119 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1120         .name           = "mailbox8",
1121         .class          = &dra7xx_mailbox_hwmod_class,
1122         .clkdm_name     = "l4cfg_clkdm",
1123         .prcm = {
1124                 .omap4 = {
1125                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1126                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1127                 },
1128         },
1129 };
1130
1131 /* mailbox9 */
1132 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1133         .name           = "mailbox9",
1134         .class          = &dra7xx_mailbox_hwmod_class,
1135         .clkdm_name     = "l4cfg_clkdm",
1136         .prcm = {
1137                 .omap4 = {
1138                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1139                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1140                 },
1141         },
1142 };
1143
1144 /* mailbox10 */
1145 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1146         .name           = "mailbox10",
1147         .class          = &dra7xx_mailbox_hwmod_class,
1148         .clkdm_name     = "l4cfg_clkdm",
1149         .prcm = {
1150                 .omap4 = {
1151                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1152                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1153                 },
1154         },
1155 };
1156
1157 /* mailbox11 */
1158 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1159         .name           = "mailbox11",
1160         .class          = &dra7xx_mailbox_hwmod_class,
1161         .clkdm_name     = "l4cfg_clkdm",
1162         .prcm = {
1163                 .omap4 = {
1164                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1165                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1166                 },
1167         },
1168 };
1169
1170 /* mailbox12 */
1171 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1172         .name           = "mailbox12",
1173         .class          = &dra7xx_mailbox_hwmod_class,
1174         .clkdm_name     = "l4cfg_clkdm",
1175         .prcm = {
1176                 .omap4 = {
1177                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1178                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1179                 },
1180         },
1181 };
1182
1183 /* mailbox13 */
1184 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1185         .name           = "mailbox13",
1186         .class          = &dra7xx_mailbox_hwmod_class,
1187         .clkdm_name     = "l4cfg_clkdm",
1188         .prcm = {
1189                 .omap4 = {
1190                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1191                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1192                 },
1193         },
1194 };
1195
1196 /*
1197  * 'mcspi' class
1198  *
1199  */
1200
1201 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1202         .rev_offs       = 0x0000,
1203         .sysc_offs      = 0x0010,
1204         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1205                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1206         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207                            SIDLE_SMART_WKUP),
1208         .sysc_fields    = &omap_hwmod_sysc_type2,
1209 };
1210
1211 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1212         .name   = "mcspi",
1213         .sysc   = &dra7xx_mcspi_sysc,
1214         .rev    = OMAP4_MCSPI_REV,
1215 };
1216
1217 /* mcspi1 */
1218 /* mcspi1 dev_attr */
1219 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1220         .num_chipselect = 4,
1221 };
1222
1223 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1224         .name           = "mcspi1",
1225         .class          = &dra7xx_mcspi_hwmod_class,
1226         .clkdm_name     = "l4per_clkdm",
1227         .main_clk       = "func_48m_fclk",
1228         .prcm = {
1229                 .omap4 = {
1230                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1231                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1232                         .modulemode   = MODULEMODE_SWCTRL,
1233                 },
1234         },
1235         .dev_attr       = &mcspi1_dev_attr,
1236 };
1237
1238 /* mcspi2 */
1239 /* mcspi2 dev_attr */
1240 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1241         .num_chipselect = 2,
1242 };
1243
1244 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1245         .name           = "mcspi2",
1246         .class          = &dra7xx_mcspi_hwmod_class,
1247         .clkdm_name     = "l4per_clkdm",
1248         .main_clk       = "func_48m_fclk",
1249         .prcm = {
1250                 .omap4 = {
1251                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1252                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1253                         .modulemode   = MODULEMODE_SWCTRL,
1254                 },
1255         },
1256         .dev_attr       = &mcspi2_dev_attr,
1257 };
1258
1259 /* mcspi3 */
1260 /* mcspi3 dev_attr */
1261 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1262         .num_chipselect = 2,
1263 };
1264
1265 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1266         .name           = "mcspi3",
1267         .class          = &dra7xx_mcspi_hwmod_class,
1268         .clkdm_name     = "l4per_clkdm",
1269         .main_clk       = "func_48m_fclk",
1270         .prcm = {
1271                 .omap4 = {
1272                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1273                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1274                         .modulemode   = MODULEMODE_SWCTRL,
1275                 },
1276         },
1277         .dev_attr       = &mcspi3_dev_attr,
1278 };
1279
1280 /* mcspi4 */
1281 /* mcspi4 dev_attr */
1282 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1283         .num_chipselect = 1,
1284 };
1285
1286 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1287         .name           = "mcspi4",
1288         .class          = &dra7xx_mcspi_hwmod_class,
1289         .clkdm_name     = "l4per_clkdm",
1290         .main_clk       = "func_48m_fclk",
1291         .prcm = {
1292                 .omap4 = {
1293                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1294                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1295                         .modulemode   = MODULEMODE_SWCTRL,
1296                 },
1297         },
1298         .dev_attr       = &mcspi4_dev_attr,
1299 };
1300
1301 /*
1302  * 'mmc' class
1303  *
1304  */
1305
1306 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1307         .rev_offs       = 0x0000,
1308         .sysc_offs      = 0x0010,
1309         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1310                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1311                            SYSC_HAS_SOFTRESET),
1312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1313                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1314                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1315         .sysc_fields    = &omap_hwmod_sysc_type2,
1316 };
1317
1318 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1319         .name   = "mmc",
1320         .sysc   = &dra7xx_mmc_sysc,
1321 };
1322
1323 /* mmc1 */
1324 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1325         { .role = "clk32k", .clk = "mmc1_clk32k" },
1326 };
1327
1328 /* mmc1 dev_attr */
1329 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1330         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1331 };
1332
1333 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1334         .name           = "mmc1",
1335         .class          = &dra7xx_mmc_hwmod_class,
1336         .clkdm_name     = "l3init_clkdm",
1337         .main_clk       = "mmc1_fclk_div",
1338         .prcm = {
1339                 .omap4 = {
1340                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1341                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1342                         .modulemode   = MODULEMODE_SWCTRL,
1343                 },
1344         },
1345         .opt_clks       = mmc1_opt_clks,
1346         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1347         .dev_attr       = &mmc1_dev_attr,
1348 };
1349
1350 /* mmc2 */
1351 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1352         { .role = "clk32k", .clk = "mmc2_clk32k" },
1353 };
1354
1355 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1356         .name           = "mmc2",
1357         .class          = &dra7xx_mmc_hwmod_class,
1358         .clkdm_name     = "l3init_clkdm",
1359         .main_clk       = "mmc2_fclk_div",
1360         .prcm = {
1361                 .omap4 = {
1362                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1363                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1364                         .modulemode   = MODULEMODE_SWCTRL,
1365                 },
1366         },
1367         .opt_clks       = mmc2_opt_clks,
1368         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1369 };
1370
1371 /* mmc3 */
1372 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1373         { .role = "clk32k", .clk = "mmc3_clk32k" },
1374 };
1375
1376 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1377         .name           = "mmc3",
1378         .class          = &dra7xx_mmc_hwmod_class,
1379         .clkdm_name     = "l4per_clkdm",
1380         .main_clk       = "mmc3_gfclk_div",
1381         .prcm = {
1382                 .omap4 = {
1383                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1384                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1385                         .modulemode   = MODULEMODE_SWCTRL,
1386                 },
1387         },
1388         .opt_clks       = mmc3_opt_clks,
1389         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1390 };
1391
1392 /* mmc4 */
1393 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1394         { .role = "clk32k", .clk = "mmc4_clk32k" },
1395 };
1396
1397 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1398         .name           = "mmc4",
1399         .class          = &dra7xx_mmc_hwmod_class,
1400         .clkdm_name     = "l4per_clkdm",
1401         .main_clk       = "mmc4_gfclk_div",
1402         .prcm = {
1403                 .omap4 = {
1404                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1405                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1406                         .modulemode   = MODULEMODE_SWCTRL,
1407                 },
1408         },
1409         .opt_clks       = mmc4_opt_clks,
1410         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1411 };
1412
1413 /*
1414  * 'mpu' class
1415  *
1416  */
1417
1418 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1419         .name   = "mpu",
1420 };
1421
1422 /* mpu */
1423 static struct omap_hwmod dra7xx_mpu_hwmod = {
1424         .name           = "mpu",
1425         .class          = &dra7xx_mpu_hwmod_class,
1426         .clkdm_name     = "mpu_clkdm",
1427         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1428         .main_clk       = "dpll_mpu_m2_ck",
1429         .prcm = {
1430                 .omap4 = {
1431                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1432                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1433                 },
1434         },
1435 };
1436
1437 /*
1438  * 'ocp2scp' class
1439  *
1440  */
1441
1442 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1443         .rev_offs       = 0x0000,
1444         .sysc_offs      = 0x0010,
1445         .syss_offs      = 0x0014,
1446         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1447                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1448         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1449                            SIDLE_SMART_WKUP),
1450         .sysc_fields    = &omap_hwmod_sysc_type1,
1451 };
1452
1453 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1454         .name   = "ocp2scp",
1455         .sysc   = &dra7xx_ocp2scp_sysc,
1456 };
1457
1458 /* ocp2scp1 */
1459 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1460         .name           = "ocp2scp1",
1461         .class          = &dra7xx_ocp2scp_hwmod_class,
1462         .clkdm_name     = "l3init_clkdm",
1463         .main_clk       = "l4_root_clk_div",
1464         .prcm = {
1465                 .omap4 = {
1466                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1467                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1468                         .modulemode   = MODULEMODE_HWCTRL,
1469                 },
1470         },
1471 };
1472
1473 /* ocp2scp3 */
1474 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1475         .name           = "ocp2scp3",
1476         .class          = &dra7xx_ocp2scp_hwmod_class,
1477         .clkdm_name     = "l3init_clkdm",
1478         .main_clk       = "l4_root_clk_div",
1479         .prcm = {
1480                 .omap4 = {
1481                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1482                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1483                         .modulemode   = MODULEMODE_HWCTRL,
1484                 },
1485         },
1486 };
1487
1488 /*
1489  * 'PCIE' class
1490  *
1491  */
1492
1493 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1494         .name   = "pcie",
1495 };
1496
1497 /* pcie1 */
1498 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1499         .name           = "pcie1",
1500         .class          = &dra7xx_pciess_hwmod_class,
1501         .clkdm_name     = "pcie_clkdm",
1502         .main_clk       = "l4_root_clk_div",
1503         .prcm = {
1504                 .omap4 = {
1505                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1506                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1507                         .modulemode   = MODULEMODE_SWCTRL,
1508                 },
1509         },
1510 };
1511
1512 /* pcie2 */
1513 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1514         .name           = "pcie2",
1515         .class          = &dra7xx_pciess_hwmod_class,
1516         .clkdm_name     = "pcie_clkdm",
1517         .main_clk       = "l4_root_clk_div",
1518         .prcm = {
1519                 .omap4 = {
1520                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1521                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1522                         .modulemode   = MODULEMODE_SWCTRL,
1523                 },
1524         },
1525 };
1526
1527 /*
1528  * 'qspi' class
1529  *
1530  */
1531
1532 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1533         .sysc_offs      = 0x0010,
1534         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1535         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1536                            SIDLE_SMART_WKUP),
1537         .sysc_fields    = &omap_hwmod_sysc_type2,
1538 };
1539
1540 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1541         .name   = "qspi",
1542         .sysc   = &dra7xx_qspi_sysc,
1543 };
1544
1545 /* qspi */
1546 static struct omap_hwmod dra7xx_qspi_hwmod = {
1547         .name           = "qspi",
1548         .class          = &dra7xx_qspi_hwmod_class,
1549         .clkdm_name     = "l4per2_clkdm",
1550         .main_clk       = "qspi_gfclk_div",
1551         .prcm = {
1552                 .omap4 = {
1553                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1554                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1555                         .modulemode   = MODULEMODE_SWCTRL,
1556                 },
1557         },
1558 };
1559
1560 /*
1561  * 'rtcss' class
1562  *
1563  */
1564 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1565         .sysc_offs      = 0x0078,
1566         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1567         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1568                            SIDLE_SMART_WKUP),
1569         .sysc_fields    = &omap_hwmod_sysc_type3,
1570 };
1571
1572 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1573         .name   = "rtcss",
1574         .sysc   = &dra7xx_rtcss_sysc,
1575 };
1576
1577 /* rtcss */
1578 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1579         .name           = "rtcss",
1580         .class          = &dra7xx_rtcss_hwmod_class,
1581         .clkdm_name     = "rtc_clkdm",
1582         .main_clk       = "sys_32k_ck",
1583         .prcm = {
1584                 .omap4 = {
1585                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1586                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1587                         .modulemode   = MODULEMODE_SWCTRL,
1588                 },
1589         },
1590 };
1591
1592 /*
1593  * 'sata' class
1594  *
1595  */
1596
1597 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1598         .sysc_offs      = 0x0000,
1599         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1600         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1601                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1602                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1603         .sysc_fields    = &omap_hwmod_sysc_type2,
1604 };
1605
1606 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1607         .name   = "sata",
1608         .sysc   = &dra7xx_sata_sysc,
1609 };
1610
1611 /* sata */
1612
1613 static struct omap_hwmod dra7xx_sata_hwmod = {
1614         .name           = "sata",
1615         .class          = &dra7xx_sata_hwmod_class,
1616         .clkdm_name     = "l3init_clkdm",
1617         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1618         .main_clk       = "func_48m_fclk",
1619         .mpu_rt_idx     = 1,
1620         .prcm = {
1621                 .omap4 = {
1622                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1623                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1624                         .modulemode   = MODULEMODE_SWCTRL,
1625                 },
1626         },
1627 };
1628
1629 /*
1630  * 'smartreflex' class
1631  *
1632  */
1633
1634 /* The IP is not compliant to type1 / type2 scheme */
1635 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1636         .sidle_shift    = 24,
1637         .enwkup_shift   = 26,
1638 };
1639
1640 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1641         .sysc_offs      = 0x0038,
1642         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1643         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1644                            SIDLE_SMART_WKUP),
1645         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
1646 };
1647
1648 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1649         .name   = "smartreflex",
1650         .sysc   = &dra7xx_smartreflex_sysc,
1651         .rev    = 2,
1652 };
1653
1654 /* smartreflex_core */
1655 /* smartreflex_core dev_attr */
1656 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1657         .sensor_voltdm_name     = "core",
1658 };
1659
1660 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1661         .name           = "smartreflex_core",
1662         .class          = &dra7xx_smartreflex_hwmod_class,
1663         .clkdm_name     = "coreaon_clkdm",
1664         .main_clk       = "wkupaon_iclk_mux",
1665         .prcm = {
1666                 .omap4 = {
1667                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1668                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1669                         .modulemode   = MODULEMODE_SWCTRL,
1670                 },
1671         },
1672         .dev_attr       = &smartreflex_core_dev_attr,
1673 };
1674
1675 /* smartreflex_mpu */
1676 /* smartreflex_mpu dev_attr */
1677 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1678         .sensor_voltdm_name     = "mpu",
1679 };
1680
1681 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1682         .name           = "smartreflex_mpu",
1683         .class          = &dra7xx_smartreflex_hwmod_class,
1684         .clkdm_name     = "coreaon_clkdm",
1685         .main_clk       = "wkupaon_iclk_mux",
1686         .prcm = {
1687                 .omap4 = {
1688                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1689                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1690                         .modulemode   = MODULEMODE_SWCTRL,
1691                 },
1692         },
1693         .dev_attr       = &smartreflex_mpu_dev_attr,
1694 };
1695
1696 /*
1697  * 'spinlock' class
1698  *
1699  */
1700
1701 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1702         .rev_offs       = 0x0000,
1703         .sysc_offs      = 0x0010,
1704         .syss_offs      = 0x0014,
1705         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1706                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1707                            SYSS_HAS_RESET_STATUS),
1708         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1709         .sysc_fields    = &omap_hwmod_sysc_type1,
1710 };
1711
1712 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1713         .name   = "spinlock",
1714         .sysc   = &dra7xx_spinlock_sysc,
1715 };
1716
1717 /* spinlock */
1718 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1719         .name           = "spinlock",
1720         .class          = &dra7xx_spinlock_hwmod_class,
1721         .clkdm_name     = "l4cfg_clkdm",
1722         .main_clk       = "l3_iclk_div",
1723         .prcm = {
1724                 .omap4 = {
1725                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1726                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1727                 },
1728         },
1729 };
1730
1731 /*
1732  * 'timer' class
1733  *
1734  * This class contains several variants: ['timer_1ms', 'timer_secure',
1735  * 'timer']
1736  */
1737
1738 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1739         .rev_offs       = 0x0000,
1740         .sysc_offs      = 0x0010,
1741         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1742                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1743         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1744                            SIDLE_SMART_WKUP),
1745         .sysc_fields    = &omap_hwmod_sysc_type2,
1746 };
1747
1748 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1749         .name   = "timer",
1750         .sysc   = &dra7xx_timer_1ms_sysc,
1751 };
1752
1753 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1754         .rev_offs       = 0x0000,
1755         .sysc_offs      = 0x0010,
1756         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1757                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1758         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1759                            SIDLE_SMART_WKUP),
1760         .sysc_fields    = &omap_hwmod_sysc_type2,
1761 };
1762
1763 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1764         .name   = "timer",
1765         .sysc   = &dra7xx_timer_sysc,
1766 };
1767
1768 /* timer1 */
1769 static struct omap_hwmod dra7xx_timer1_hwmod = {
1770         .name           = "timer1",
1771         .class          = &dra7xx_timer_1ms_hwmod_class,
1772         .clkdm_name     = "wkupaon_clkdm",
1773         .main_clk       = "timer1_gfclk_mux",
1774         .prcm = {
1775                 .omap4 = {
1776                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1777                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1778                         .modulemode   = MODULEMODE_SWCTRL,
1779                 },
1780         },
1781 };
1782
1783 /* timer2 */
1784 static struct omap_hwmod dra7xx_timer2_hwmod = {
1785         .name           = "timer2",
1786         .class          = &dra7xx_timer_1ms_hwmod_class,
1787         .clkdm_name     = "l4per_clkdm",
1788         .main_clk       = "timer2_gfclk_mux",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1792                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1793                         .modulemode   = MODULEMODE_SWCTRL,
1794                 },
1795         },
1796 };
1797
1798 /* timer3 */
1799 static struct omap_hwmod dra7xx_timer3_hwmod = {
1800         .name           = "timer3",
1801         .class          = &dra7xx_timer_hwmod_class,
1802         .clkdm_name     = "l4per_clkdm",
1803         .main_clk       = "timer3_gfclk_mux",
1804         .prcm = {
1805                 .omap4 = {
1806                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1807                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1808                         .modulemode   = MODULEMODE_SWCTRL,
1809                 },
1810         },
1811 };
1812
1813 /* timer4 */
1814 static struct omap_hwmod dra7xx_timer4_hwmod = {
1815         .name           = "timer4",
1816         .class          = &dra7xx_timer_hwmod_class,
1817         .clkdm_name     = "l4per_clkdm",
1818         .main_clk       = "timer4_gfclk_mux",
1819         .prcm = {
1820                 .omap4 = {
1821                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1822                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1823                         .modulemode   = MODULEMODE_SWCTRL,
1824                 },
1825         },
1826 };
1827
1828 /* timer5 */
1829 static struct omap_hwmod dra7xx_timer5_hwmod = {
1830         .name           = "timer5",
1831         .class          = &dra7xx_timer_hwmod_class,
1832         .clkdm_name     = "ipu_clkdm",
1833         .main_clk       = "timer5_gfclk_mux",
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1837                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1838                         .modulemode   = MODULEMODE_SWCTRL,
1839                 },
1840         },
1841 };
1842
1843 /* timer6 */
1844 static struct omap_hwmod dra7xx_timer6_hwmod = {
1845         .name           = "timer6",
1846         .class          = &dra7xx_timer_hwmod_class,
1847         .clkdm_name     = "ipu_clkdm",
1848         .main_clk       = "timer6_gfclk_mux",
1849         .prcm = {
1850                 .omap4 = {
1851                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1852                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1853                         .modulemode   = MODULEMODE_SWCTRL,
1854                 },
1855         },
1856 };
1857
1858 /* timer7 */
1859 static struct omap_hwmod dra7xx_timer7_hwmod = {
1860         .name           = "timer7",
1861         .class          = &dra7xx_timer_hwmod_class,
1862         .clkdm_name     = "ipu_clkdm",
1863         .main_clk       = "timer7_gfclk_mux",
1864         .prcm = {
1865                 .omap4 = {
1866                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1867                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1868                         .modulemode   = MODULEMODE_SWCTRL,
1869                 },
1870         },
1871 };
1872
1873 /* timer8 */
1874 static struct omap_hwmod dra7xx_timer8_hwmod = {
1875         .name           = "timer8",
1876         .class          = &dra7xx_timer_hwmod_class,
1877         .clkdm_name     = "ipu_clkdm",
1878         .main_clk       = "timer8_gfclk_mux",
1879         .prcm = {
1880                 .omap4 = {
1881                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1882                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1883                         .modulemode   = MODULEMODE_SWCTRL,
1884                 },
1885         },
1886 };
1887
1888 /* timer9 */
1889 static struct omap_hwmod dra7xx_timer9_hwmod = {
1890         .name           = "timer9",
1891         .class          = &dra7xx_timer_hwmod_class,
1892         .clkdm_name     = "l4per_clkdm",
1893         .main_clk       = "timer9_gfclk_mux",
1894         .prcm = {
1895                 .omap4 = {
1896                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1897                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1898                         .modulemode   = MODULEMODE_SWCTRL,
1899                 },
1900         },
1901 };
1902
1903 /* timer10 */
1904 static struct omap_hwmod dra7xx_timer10_hwmod = {
1905         .name           = "timer10",
1906         .class          = &dra7xx_timer_1ms_hwmod_class,
1907         .clkdm_name     = "l4per_clkdm",
1908         .main_clk       = "timer10_gfclk_mux",
1909         .prcm = {
1910                 .omap4 = {
1911                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1912                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1913                         .modulemode   = MODULEMODE_SWCTRL,
1914                 },
1915         },
1916 };
1917
1918 /* timer11 */
1919 static struct omap_hwmod dra7xx_timer11_hwmod = {
1920         .name           = "timer11",
1921         .class          = &dra7xx_timer_hwmod_class,
1922         .clkdm_name     = "l4per_clkdm",
1923         .main_clk       = "timer11_gfclk_mux",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1927                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_SWCTRL,
1929                 },
1930         },
1931 };
1932
1933 /* timer13 */
1934 static struct omap_hwmod dra7xx_timer13_hwmod = {
1935         .name           = "timer13",
1936         .class          = &dra7xx_timer_hwmod_class,
1937         .clkdm_name     = "l4per3_clkdm",
1938         .main_clk       = "timer13_gfclk_mux",
1939         .prcm = {
1940                 .omap4 = {
1941                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1942                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1943                         .modulemode   = MODULEMODE_SWCTRL,
1944                 },
1945         },
1946 };
1947
1948 /* timer14 */
1949 static struct omap_hwmod dra7xx_timer14_hwmod = {
1950         .name           = "timer14",
1951         .class          = &dra7xx_timer_hwmod_class,
1952         .clkdm_name     = "l4per3_clkdm",
1953         .main_clk       = "timer14_gfclk_mux",
1954         .prcm = {
1955                 .omap4 = {
1956                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1957                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1958                         .modulemode   = MODULEMODE_SWCTRL,
1959                 },
1960         },
1961 };
1962
1963 /* timer15 */
1964 static struct omap_hwmod dra7xx_timer15_hwmod = {
1965         .name           = "timer15",
1966         .class          = &dra7xx_timer_hwmod_class,
1967         .clkdm_name     = "l4per3_clkdm",
1968         .main_clk       = "timer15_gfclk_mux",
1969         .prcm = {
1970                 .omap4 = {
1971                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1972                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1973                         .modulemode   = MODULEMODE_SWCTRL,
1974                 },
1975         },
1976 };
1977
1978 /* timer16 */
1979 static struct omap_hwmod dra7xx_timer16_hwmod = {
1980         .name           = "timer16",
1981         .class          = &dra7xx_timer_hwmod_class,
1982         .clkdm_name     = "l4per3_clkdm",
1983         .main_clk       = "timer16_gfclk_mux",
1984         .prcm = {
1985                 .omap4 = {
1986                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1987                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1988                         .modulemode   = MODULEMODE_SWCTRL,
1989                 },
1990         },
1991 };
1992
1993 /*
1994  * 'uart' class
1995  *
1996  */
1997
1998 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1999         .rev_offs       = 0x0050,
2000         .sysc_offs      = 0x0054,
2001         .syss_offs      = 0x0058,
2002         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2003                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2004                            SYSS_HAS_RESET_STATUS),
2005         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2006                            SIDLE_SMART_WKUP),
2007         .sysc_fields    = &omap_hwmod_sysc_type1,
2008 };
2009
2010 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2011         .name   = "uart",
2012         .sysc   = &dra7xx_uart_sysc,
2013 };
2014
2015 /* uart1 */
2016 static struct omap_hwmod dra7xx_uart1_hwmod = {
2017         .name           = "uart1",
2018         .class          = &dra7xx_uart_hwmod_class,
2019         .clkdm_name     = "l4per_clkdm",
2020         .main_clk       = "uart1_gfclk_mux",
2021         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2022         .prcm = {
2023                 .omap4 = {
2024                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2025                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2026                         .modulemode   = MODULEMODE_SWCTRL,
2027                 },
2028         },
2029 };
2030
2031 /* uart2 */
2032 static struct omap_hwmod dra7xx_uart2_hwmod = {
2033         .name           = "uart2",
2034         .class          = &dra7xx_uart_hwmod_class,
2035         .clkdm_name     = "l4per_clkdm",
2036         .main_clk       = "uart2_gfclk_mux",
2037         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2038         .prcm = {
2039                 .omap4 = {
2040                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2041                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2042                         .modulemode   = MODULEMODE_SWCTRL,
2043                 },
2044         },
2045 };
2046
2047 /* uart3 */
2048 static struct omap_hwmod dra7xx_uart3_hwmod = {
2049         .name           = "uart3",
2050         .class          = &dra7xx_uart_hwmod_class,
2051         .clkdm_name     = "l4per_clkdm",
2052         .main_clk       = "uart3_gfclk_mux",
2053         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2054         .prcm = {
2055                 .omap4 = {
2056                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2057                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2058                         .modulemode   = MODULEMODE_SWCTRL,
2059                 },
2060         },
2061 };
2062
2063 /* uart4 */
2064 static struct omap_hwmod dra7xx_uart4_hwmod = {
2065         .name           = "uart4",
2066         .class          = &dra7xx_uart_hwmod_class,
2067         .clkdm_name     = "l4per_clkdm",
2068         .main_clk       = "uart4_gfclk_mux",
2069         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2070         .prcm = {
2071                 .omap4 = {
2072                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2073                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2074                         .modulemode   = MODULEMODE_SWCTRL,
2075                 },
2076         },
2077 };
2078
2079 /* uart5 */
2080 static struct omap_hwmod dra7xx_uart5_hwmod = {
2081         .name           = "uart5",
2082         .class          = &dra7xx_uart_hwmod_class,
2083         .clkdm_name     = "l4per_clkdm",
2084         .main_clk       = "uart5_gfclk_mux",
2085         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2086         .prcm = {
2087                 .omap4 = {
2088                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2089                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2090                         .modulemode   = MODULEMODE_SWCTRL,
2091                 },
2092         },
2093 };
2094
2095 /* uart6 */
2096 static struct omap_hwmod dra7xx_uart6_hwmod = {
2097         .name           = "uart6",
2098         .class          = &dra7xx_uart_hwmod_class,
2099         .clkdm_name     = "ipu_clkdm",
2100         .main_clk       = "uart6_gfclk_mux",
2101         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2102         .prcm = {
2103                 .omap4 = {
2104                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2105                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2106                         .modulemode   = MODULEMODE_SWCTRL,
2107                 },
2108         },
2109 };
2110
2111 /* uart7 */
2112 static struct omap_hwmod dra7xx_uart7_hwmod = {
2113         .name           = "uart7",
2114         .class          = &dra7xx_uart_hwmod_class,
2115         .clkdm_name     = "l4per2_clkdm",
2116         .main_clk       = "uart7_gfclk_mux",
2117         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2118         .prcm = {
2119                 .omap4 = {
2120                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2121                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2122                         .modulemode   = MODULEMODE_SWCTRL,
2123                 },
2124         },
2125 };
2126
2127 /* uart8 */
2128 static struct omap_hwmod dra7xx_uart8_hwmod = {
2129         .name           = "uart8",
2130         .class          = &dra7xx_uart_hwmod_class,
2131         .clkdm_name     = "l4per2_clkdm",
2132         .main_clk       = "uart8_gfclk_mux",
2133         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2134         .prcm = {
2135                 .omap4 = {
2136                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2137                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2138                         .modulemode   = MODULEMODE_SWCTRL,
2139                 },
2140         },
2141 };
2142
2143 /* uart9 */
2144 static struct omap_hwmod dra7xx_uart9_hwmod = {
2145         .name           = "uart9",
2146         .class          = &dra7xx_uart_hwmod_class,
2147         .clkdm_name     = "l4per2_clkdm",
2148         .main_clk       = "uart9_gfclk_mux",
2149         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2150         .prcm = {
2151                 .omap4 = {
2152                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2153                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2154                         .modulemode   = MODULEMODE_SWCTRL,
2155                 },
2156         },
2157 };
2158
2159 /* uart10 */
2160 static struct omap_hwmod dra7xx_uart10_hwmod = {
2161         .name           = "uart10",
2162         .class          = &dra7xx_uart_hwmod_class,
2163         .clkdm_name     = "wkupaon_clkdm",
2164         .main_clk       = "uart10_gfclk_mux",
2165         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2166         .prcm = {
2167                 .omap4 = {
2168                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2169                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2170                         .modulemode   = MODULEMODE_SWCTRL,
2171                 },
2172         },
2173 };
2174
2175 /*
2176  * 'usb_otg_ss' class
2177  *
2178  */
2179
2180 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2181         .rev_offs       = 0x0000,
2182         .sysc_offs      = 0x0010,
2183         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2184                            SYSC_HAS_SIDLEMODE),
2185         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2186                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2187                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2188         .sysc_fields    = &omap_hwmod_sysc_type2,
2189 };
2190
2191 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2192         .name   = "usb_otg_ss",
2193         .sysc   = &dra7xx_usb_otg_ss_sysc,
2194 };
2195
2196 /* usb_otg_ss1 */
2197 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2198         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2199 };
2200
2201 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2202         .name           = "usb_otg_ss1",
2203         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2204         .clkdm_name     = "l3init_clkdm",
2205         .main_clk       = "dpll_core_h13x2_ck",
2206         .prcm = {
2207                 .omap4 = {
2208                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2209                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2210                         .modulemode   = MODULEMODE_HWCTRL,
2211                 },
2212         },
2213         .opt_clks       = usb_otg_ss1_opt_clks,
2214         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2215 };
2216
2217 /* usb_otg_ss2 */
2218 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2219         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2220 };
2221
2222 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2223         .name           = "usb_otg_ss2",
2224         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2225         .clkdm_name     = "l3init_clkdm",
2226         .main_clk       = "dpll_core_h13x2_ck",
2227         .prcm = {
2228                 .omap4 = {
2229                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2230                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2231                         .modulemode   = MODULEMODE_HWCTRL,
2232                 },
2233         },
2234         .opt_clks       = usb_otg_ss2_opt_clks,
2235         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2236 };
2237
2238 /* usb_otg_ss3 */
2239 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2240         .name           = "usb_otg_ss3",
2241         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2242         .clkdm_name     = "l3init_clkdm",
2243         .main_clk       = "dpll_core_h13x2_ck",
2244         .prcm = {
2245                 .omap4 = {
2246                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2247                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2248                         .modulemode   = MODULEMODE_HWCTRL,
2249                 },
2250         },
2251 };
2252
2253 /* usb_otg_ss4 */
2254 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2255         .name           = "usb_otg_ss4",
2256         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2257         .clkdm_name     = "l3init_clkdm",
2258         .main_clk       = "dpll_core_h13x2_ck",
2259         .prcm = {
2260                 .omap4 = {
2261                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2262                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2263                         .modulemode   = MODULEMODE_HWCTRL,
2264                 },
2265         },
2266 };
2267
2268 /*
2269  * 'vcp' class
2270  *
2271  */
2272
2273 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2274         .name   = "vcp",
2275 };
2276
2277 /* vcp1 */
2278 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2279         .name           = "vcp1",
2280         .class          = &dra7xx_vcp_hwmod_class,
2281         .clkdm_name     = "l3main1_clkdm",
2282         .main_clk       = "l3_iclk_div",
2283         .prcm = {
2284                 .omap4 = {
2285                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2286                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2287                 },
2288         },
2289 };
2290
2291 /* vcp2 */
2292 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2293         .name           = "vcp2",
2294         .class          = &dra7xx_vcp_hwmod_class,
2295         .clkdm_name     = "l3main1_clkdm",
2296         .main_clk       = "l3_iclk_div",
2297         .prcm = {
2298                 .omap4 = {
2299                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2300                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2301                 },
2302         },
2303 };
2304
2305 /*
2306  * 'wd_timer' class
2307  *
2308  */
2309
2310 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2311         .rev_offs       = 0x0000,
2312         .sysc_offs      = 0x0010,
2313         .syss_offs      = 0x0014,
2314         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2315                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2317                            SIDLE_SMART_WKUP),
2318         .sysc_fields    = &omap_hwmod_sysc_type1,
2319 };
2320
2321 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2322         .name           = "wd_timer",
2323         .sysc           = &dra7xx_wd_timer_sysc,
2324         .pre_shutdown   = &omap2_wd_timer_disable,
2325         .reset          = &omap2_wd_timer_reset,
2326 };
2327
2328 /* wd_timer2 */
2329 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2330         .name           = "wd_timer2",
2331         .class          = &dra7xx_wd_timer_hwmod_class,
2332         .clkdm_name     = "wkupaon_clkdm",
2333         .main_clk       = "sys_32k_ck",
2334         .prcm = {
2335                 .omap4 = {
2336                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2337                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2338                         .modulemode   = MODULEMODE_SWCTRL,
2339                 },
2340         },
2341 };
2342
2343
2344 /*
2345  * Interfaces
2346  */
2347
2348 /* l3_main_1 -> dmm */
2349 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2350         .master         = &dra7xx_l3_main_1_hwmod,
2351         .slave          = &dra7xx_dmm_hwmod,
2352         .clk            = "l3_iclk_div",
2353         .user           = OCP_USER_SDMA,
2354 };
2355
2356 /* l3_main_2 -> l3_instr */
2357 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2358         .master         = &dra7xx_l3_main_2_hwmod,
2359         .slave          = &dra7xx_l3_instr_hwmod,
2360         .clk            = "l3_iclk_div",
2361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2362 };
2363
2364 /* l4_cfg -> l3_main_1 */
2365 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2366         .master         = &dra7xx_l4_cfg_hwmod,
2367         .slave          = &dra7xx_l3_main_1_hwmod,
2368         .clk            = "l3_iclk_div",
2369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2370 };
2371
2372 /* mpu -> l3_main_1 */
2373 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2374         .master         = &dra7xx_mpu_hwmod,
2375         .slave          = &dra7xx_l3_main_1_hwmod,
2376         .clk            = "l3_iclk_div",
2377         .user           = OCP_USER_MPU,
2378 };
2379
2380 /* l3_main_1 -> l3_main_2 */
2381 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2382         .master         = &dra7xx_l3_main_1_hwmod,
2383         .slave          = &dra7xx_l3_main_2_hwmod,
2384         .clk            = "l3_iclk_div",
2385         .user           = OCP_USER_MPU,
2386 };
2387
2388 /* l4_cfg -> l3_main_2 */
2389 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2390         .master         = &dra7xx_l4_cfg_hwmod,
2391         .slave          = &dra7xx_l3_main_2_hwmod,
2392         .clk            = "l3_iclk_div",
2393         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2394 };
2395
2396 /* l3_main_1 -> l4_cfg */
2397 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2398         .master         = &dra7xx_l3_main_1_hwmod,
2399         .slave          = &dra7xx_l4_cfg_hwmod,
2400         .clk            = "l3_iclk_div",
2401         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2402 };
2403
2404 /* l3_main_1 -> l4_per1 */
2405 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2406         .master         = &dra7xx_l3_main_1_hwmod,
2407         .slave          = &dra7xx_l4_per1_hwmod,
2408         .clk            = "l3_iclk_div",
2409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2410 };
2411
2412 /* l3_main_1 -> l4_per2 */
2413 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2414         .master         = &dra7xx_l3_main_1_hwmod,
2415         .slave          = &dra7xx_l4_per2_hwmod,
2416         .clk            = "l3_iclk_div",
2417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2418 };
2419
2420 /* l3_main_1 -> l4_per3 */
2421 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2422         .master         = &dra7xx_l3_main_1_hwmod,
2423         .slave          = &dra7xx_l4_per3_hwmod,
2424         .clk            = "l3_iclk_div",
2425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2426 };
2427
2428 /* l3_main_1 -> l4_wkup */
2429 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2430         .master         = &dra7xx_l3_main_1_hwmod,
2431         .slave          = &dra7xx_l4_wkup_hwmod,
2432         .clk            = "wkupaon_iclk_mux",
2433         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2434 };
2435
2436 /* l4_per2 -> atl */
2437 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2438         .master         = &dra7xx_l4_per2_hwmod,
2439         .slave          = &dra7xx_atl_hwmod,
2440         .clk            = "l3_iclk_div",
2441         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2442 };
2443
2444 /* l3_main_1 -> bb2d */
2445 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2446         .master         = &dra7xx_l3_main_1_hwmod,
2447         .slave          = &dra7xx_bb2d_hwmod,
2448         .clk            = "l3_iclk_div",
2449         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2450 };
2451
2452 /* l4_wkup -> counter_32k */
2453 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2454         .master         = &dra7xx_l4_wkup_hwmod,
2455         .slave          = &dra7xx_counter_32k_hwmod,
2456         .clk            = "wkupaon_iclk_mux",
2457         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2458 };
2459
2460 /* l4_wkup -> ctrl_module_wkup */
2461 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2462         .master         = &dra7xx_l4_wkup_hwmod,
2463         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2464         .clk            = "wkupaon_iclk_mux",
2465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2466 };
2467
2468 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2469         .master         = &dra7xx_l4_per2_hwmod,
2470         .slave          = &dra7xx_gmac_hwmod,
2471         .clk            = "dpll_gmac_ck",
2472         .user           = OCP_USER_MPU,
2473 };
2474
2475 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2476         .master         = &dra7xx_gmac_hwmod,
2477         .slave          = &dra7xx_mdio_hwmod,
2478         .user           = OCP_USER_MPU,
2479 };
2480
2481 /* l4_wkup -> dcan1 */
2482 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2483         .master         = &dra7xx_l4_wkup_hwmod,
2484         .slave          = &dra7xx_dcan1_hwmod,
2485         .clk            = "wkupaon_iclk_mux",
2486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489 /* l4_per2 -> dcan2 */
2490 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2491         .master         = &dra7xx_l4_per2_hwmod,
2492         .slave          = &dra7xx_dcan2_hwmod,
2493         .clk            = "l3_iclk_div",
2494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2495 };
2496
2497 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2498         {
2499                 .pa_start       = 0x4a056000,
2500                 .pa_end         = 0x4a056fff,
2501                 .flags          = ADDR_TYPE_RT
2502         },
2503         { }
2504 };
2505
2506 /* l4_cfg -> dma_system */
2507 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2508         .master         = &dra7xx_l4_cfg_hwmod,
2509         .slave          = &dra7xx_dma_system_hwmod,
2510         .clk            = "l3_iclk_div",
2511         .addr           = dra7xx_dma_system_addrs,
2512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2513 };
2514
2515 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2516         {
2517                 .name           = "family",
2518                 .pa_start       = 0x58000000,
2519                 .pa_end         = 0x5800007f,
2520                 .flags          = ADDR_TYPE_RT
2521         },
2522 };
2523
2524 /* l3_main_1 -> dss */
2525 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2526         .master         = &dra7xx_l3_main_1_hwmod,
2527         .slave          = &dra7xx_dss_hwmod,
2528         .clk            = "l3_iclk_div",
2529         .addr           = dra7xx_dss_addrs,
2530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2531 };
2532
2533 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2534         {
2535                 .name           = "dispc",
2536                 .pa_start       = 0x58001000,
2537                 .pa_end         = 0x58001fff,
2538                 .flags          = ADDR_TYPE_RT
2539         },
2540 };
2541
2542 /* l3_main_1 -> dispc */
2543 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2544         .master         = &dra7xx_l3_main_1_hwmod,
2545         .slave          = &dra7xx_dss_dispc_hwmod,
2546         .clk            = "l3_iclk_div",
2547         .addr           = dra7xx_dss_dispc_addrs,
2548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2549 };
2550
2551 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2552         {
2553                 .name           = "hdmi_wp",
2554                 .pa_start       = 0x58040000,
2555                 .pa_end         = 0x580400ff,
2556                 .flags          = ADDR_TYPE_RT
2557         },
2558         { }
2559 };
2560
2561 /* l3_main_1 -> dispc */
2562 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2563         .master         = &dra7xx_l3_main_1_hwmod,
2564         .slave          = &dra7xx_dss_hdmi_hwmod,
2565         .clk            = "l3_iclk_div",
2566         .addr           = dra7xx_dss_hdmi_addrs,
2567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2568 };
2569
2570 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2571         {
2572                 .pa_start       = 0x48078000,
2573                 .pa_end         = 0x48078fff,
2574                 .flags          = ADDR_TYPE_RT
2575         },
2576         { }
2577 };
2578
2579 /* l4_per1 -> elm */
2580 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2581         .master         = &dra7xx_l4_per1_hwmod,
2582         .slave          = &dra7xx_elm_hwmod,
2583         .clk            = "l3_iclk_div",
2584         .addr           = dra7xx_elm_addrs,
2585         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2586 };
2587
2588 /* l4_wkup -> gpio1 */
2589 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2590         .master         = &dra7xx_l4_wkup_hwmod,
2591         .slave          = &dra7xx_gpio1_hwmod,
2592         .clk            = "wkupaon_iclk_mux",
2593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2594 };
2595
2596 /* l4_per1 -> gpio2 */
2597 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2598         .master         = &dra7xx_l4_per1_hwmod,
2599         .slave          = &dra7xx_gpio2_hwmod,
2600         .clk            = "l3_iclk_div",
2601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2602 };
2603
2604 /* l4_per1 -> gpio3 */
2605 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2606         .master         = &dra7xx_l4_per1_hwmod,
2607         .slave          = &dra7xx_gpio3_hwmod,
2608         .clk            = "l3_iclk_div",
2609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2610 };
2611
2612 /* l4_per1 -> gpio4 */
2613 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2614         .master         = &dra7xx_l4_per1_hwmod,
2615         .slave          = &dra7xx_gpio4_hwmod,
2616         .clk            = "l3_iclk_div",
2617         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2618 };
2619
2620 /* l4_per1 -> gpio5 */
2621 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2622         .master         = &dra7xx_l4_per1_hwmod,
2623         .slave          = &dra7xx_gpio5_hwmod,
2624         .clk            = "l3_iclk_div",
2625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2626 };
2627
2628 /* l4_per1 -> gpio6 */
2629 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2630         .master         = &dra7xx_l4_per1_hwmod,
2631         .slave          = &dra7xx_gpio6_hwmod,
2632         .clk            = "l3_iclk_div",
2633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2634 };
2635
2636 /* l4_per1 -> gpio7 */
2637 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2638         .master         = &dra7xx_l4_per1_hwmod,
2639         .slave          = &dra7xx_gpio7_hwmod,
2640         .clk            = "l3_iclk_div",
2641         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2642 };
2643
2644 /* l4_per1 -> gpio8 */
2645 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2646         .master         = &dra7xx_l4_per1_hwmod,
2647         .slave          = &dra7xx_gpio8_hwmod,
2648         .clk            = "l3_iclk_div",
2649         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2650 };
2651
2652 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2653         {
2654                 .pa_start       = 0x50000000,
2655                 .pa_end         = 0x500003ff,
2656                 .flags          = ADDR_TYPE_RT
2657         },
2658         { }
2659 };
2660
2661 /* l3_main_1 -> gpmc */
2662 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2663         .master         = &dra7xx_l3_main_1_hwmod,
2664         .slave          = &dra7xx_gpmc_hwmod,
2665         .clk            = "l3_iclk_div",
2666         .addr           = dra7xx_gpmc_addrs,
2667         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2668 };
2669
2670 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2671         {
2672                 .pa_start       = 0x480b2000,
2673                 .pa_end         = 0x480b201f,
2674                 .flags          = ADDR_TYPE_RT
2675         },
2676         { }
2677 };
2678
2679 /* l4_per1 -> hdq1w */
2680 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2681         .master         = &dra7xx_l4_per1_hwmod,
2682         .slave          = &dra7xx_hdq1w_hwmod,
2683         .clk            = "l3_iclk_div",
2684         .addr           = dra7xx_hdq1w_addrs,
2685         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2686 };
2687
2688 /* l4_per1 -> i2c1 */
2689 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2690         .master         = &dra7xx_l4_per1_hwmod,
2691         .slave          = &dra7xx_i2c1_hwmod,
2692         .clk            = "l3_iclk_div",
2693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2694 };
2695
2696 /* l4_per1 -> i2c2 */
2697 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2698         .master         = &dra7xx_l4_per1_hwmod,
2699         .slave          = &dra7xx_i2c2_hwmod,
2700         .clk            = "l3_iclk_div",
2701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2702 };
2703
2704 /* l4_per1 -> i2c3 */
2705 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2706         .master         = &dra7xx_l4_per1_hwmod,
2707         .slave          = &dra7xx_i2c3_hwmod,
2708         .clk            = "l3_iclk_div",
2709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2710 };
2711
2712 /* l4_per1 -> i2c4 */
2713 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2714         .master         = &dra7xx_l4_per1_hwmod,
2715         .slave          = &dra7xx_i2c4_hwmod,
2716         .clk            = "l3_iclk_div",
2717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2718 };
2719
2720 /* l4_per1 -> i2c5 */
2721 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2722         .master         = &dra7xx_l4_per1_hwmod,
2723         .slave          = &dra7xx_i2c5_hwmod,
2724         .clk            = "l3_iclk_div",
2725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2726 };
2727
2728 /* l4_cfg -> mailbox1 */
2729 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2730         .master         = &dra7xx_l4_cfg_hwmod,
2731         .slave          = &dra7xx_mailbox1_hwmod,
2732         .clk            = "l3_iclk_div",
2733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2734 };
2735
2736 /* l4_per3 -> mailbox2 */
2737 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2738         .master         = &dra7xx_l4_per3_hwmod,
2739         .slave          = &dra7xx_mailbox2_hwmod,
2740         .clk            = "l3_iclk_div",
2741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2742 };
2743
2744 /* l4_per3 -> mailbox3 */
2745 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2746         .master         = &dra7xx_l4_per3_hwmod,
2747         .slave          = &dra7xx_mailbox3_hwmod,
2748         .clk            = "l3_iclk_div",
2749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2750 };
2751
2752 /* l4_per3 -> mailbox4 */
2753 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2754         .master         = &dra7xx_l4_per3_hwmod,
2755         .slave          = &dra7xx_mailbox4_hwmod,
2756         .clk            = "l3_iclk_div",
2757         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2758 };
2759
2760 /* l4_per3 -> mailbox5 */
2761 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2762         .master         = &dra7xx_l4_per3_hwmod,
2763         .slave          = &dra7xx_mailbox5_hwmod,
2764         .clk            = "l3_iclk_div",
2765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2766 };
2767
2768 /* l4_per3 -> mailbox6 */
2769 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2770         .master         = &dra7xx_l4_per3_hwmod,
2771         .slave          = &dra7xx_mailbox6_hwmod,
2772         .clk            = "l3_iclk_div",
2773         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2774 };
2775
2776 /* l4_per3 -> mailbox7 */
2777 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2778         .master         = &dra7xx_l4_per3_hwmod,
2779         .slave          = &dra7xx_mailbox7_hwmod,
2780         .clk            = "l3_iclk_div",
2781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2782 };
2783
2784 /* l4_per3 -> mailbox8 */
2785 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2786         .master         = &dra7xx_l4_per3_hwmod,
2787         .slave          = &dra7xx_mailbox8_hwmod,
2788         .clk            = "l3_iclk_div",
2789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2790 };
2791
2792 /* l4_per3 -> mailbox9 */
2793 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2794         .master         = &dra7xx_l4_per3_hwmod,
2795         .slave          = &dra7xx_mailbox9_hwmod,
2796         .clk            = "l3_iclk_div",
2797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2798 };
2799
2800 /* l4_per3 -> mailbox10 */
2801 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2802         .master         = &dra7xx_l4_per3_hwmod,
2803         .slave          = &dra7xx_mailbox10_hwmod,
2804         .clk            = "l3_iclk_div",
2805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2806 };
2807
2808 /* l4_per3 -> mailbox11 */
2809 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2810         .master         = &dra7xx_l4_per3_hwmod,
2811         .slave          = &dra7xx_mailbox11_hwmod,
2812         .clk            = "l3_iclk_div",
2813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 /* l4_per3 -> mailbox12 */
2817 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2818         .master         = &dra7xx_l4_per3_hwmod,
2819         .slave          = &dra7xx_mailbox12_hwmod,
2820         .clk            = "l3_iclk_div",
2821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2822 };
2823
2824 /* l4_per3 -> mailbox13 */
2825 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2826         .master         = &dra7xx_l4_per3_hwmod,
2827         .slave          = &dra7xx_mailbox13_hwmod,
2828         .clk            = "l3_iclk_div",
2829         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2830 };
2831
2832 /* l4_per1 -> mcspi1 */
2833 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2834         .master         = &dra7xx_l4_per1_hwmod,
2835         .slave          = &dra7xx_mcspi1_hwmod,
2836         .clk            = "l3_iclk_div",
2837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2838 };
2839
2840 /* l4_per1 -> mcspi2 */
2841 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2842         .master         = &dra7xx_l4_per1_hwmod,
2843         .slave          = &dra7xx_mcspi2_hwmod,
2844         .clk            = "l3_iclk_div",
2845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2846 };
2847
2848 /* l4_per1 -> mcspi3 */
2849 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2850         .master         = &dra7xx_l4_per1_hwmod,
2851         .slave          = &dra7xx_mcspi3_hwmod,
2852         .clk            = "l3_iclk_div",
2853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2854 };
2855
2856 /* l4_per1 -> mcspi4 */
2857 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2858         .master         = &dra7xx_l4_per1_hwmod,
2859         .slave          = &dra7xx_mcspi4_hwmod,
2860         .clk            = "l3_iclk_div",
2861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2862 };
2863
2864 /* l4_per1 -> mmc1 */
2865 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2866         .master         = &dra7xx_l4_per1_hwmod,
2867         .slave          = &dra7xx_mmc1_hwmod,
2868         .clk            = "l3_iclk_div",
2869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2870 };
2871
2872 /* l4_per1 -> mmc2 */
2873 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2874         .master         = &dra7xx_l4_per1_hwmod,
2875         .slave          = &dra7xx_mmc2_hwmod,
2876         .clk            = "l3_iclk_div",
2877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2878 };
2879
2880 /* l4_per1 -> mmc3 */
2881 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2882         .master         = &dra7xx_l4_per1_hwmod,
2883         .slave          = &dra7xx_mmc3_hwmod,
2884         .clk            = "l3_iclk_div",
2885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2886 };
2887
2888 /* l4_per1 -> mmc4 */
2889 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2890         .master         = &dra7xx_l4_per1_hwmod,
2891         .slave          = &dra7xx_mmc4_hwmod,
2892         .clk            = "l3_iclk_div",
2893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2894 };
2895
2896 /* l4_cfg -> mpu */
2897 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2898         .master         = &dra7xx_l4_cfg_hwmod,
2899         .slave          = &dra7xx_mpu_hwmod,
2900         .clk            = "l3_iclk_div",
2901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2902 };
2903
2904 /* l4_cfg -> ocp2scp1 */
2905 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2906         .master         = &dra7xx_l4_cfg_hwmod,
2907         .slave          = &dra7xx_ocp2scp1_hwmod,
2908         .clk            = "l4_root_clk_div",
2909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2910 };
2911
2912 /* l4_cfg -> ocp2scp3 */
2913 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2914         .master         = &dra7xx_l4_cfg_hwmod,
2915         .slave          = &dra7xx_ocp2scp3_hwmod,
2916         .clk            = "l4_root_clk_div",
2917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2918 };
2919
2920 /* l3_main_1 -> pciess1 */
2921 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2922         .master         = &dra7xx_l3_main_1_hwmod,
2923         .slave          = &dra7xx_pciess1_hwmod,
2924         .clk            = "l3_iclk_div",
2925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2926 };
2927
2928 /* l4_cfg -> pciess1 */
2929 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2930         .master         = &dra7xx_l4_cfg_hwmod,
2931         .slave          = &dra7xx_pciess1_hwmod,
2932         .clk            = "l4_root_clk_div",
2933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2934 };
2935
2936 /* l3_main_1 -> pciess2 */
2937 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2938         .master         = &dra7xx_l3_main_1_hwmod,
2939         .slave          = &dra7xx_pciess2_hwmod,
2940         .clk            = "l3_iclk_div",
2941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2942 };
2943
2944 /* l4_cfg -> pciess2 */
2945 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2946         .master         = &dra7xx_l4_cfg_hwmod,
2947         .slave          = &dra7xx_pciess2_hwmod,
2948         .clk            = "l4_root_clk_div",
2949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2950 };
2951
2952 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2953         {
2954                 .pa_start       = 0x4b300000,
2955                 .pa_end         = 0x4b30007f,
2956                 .flags          = ADDR_TYPE_RT
2957         },
2958         { }
2959 };
2960
2961 /* l3_main_1 -> qspi */
2962 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2963         .master         = &dra7xx_l3_main_1_hwmod,
2964         .slave          = &dra7xx_qspi_hwmod,
2965         .clk            = "l3_iclk_div",
2966         .addr           = dra7xx_qspi_addrs,
2967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2968 };
2969
2970 /* l4_per3 -> rtcss */
2971 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2972         .master         = &dra7xx_l4_per3_hwmod,
2973         .slave          = &dra7xx_rtcss_hwmod,
2974         .clk            = "l4_root_clk_div",
2975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2976 };
2977
2978 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2979         {
2980                 .name           = "sysc",
2981                 .pa_start       = 0x4a141100,
2982                 .pa_end         = 0x4a141107,
2983                 .flags          = ADDR_TYPE_RT
2984         },
2985         { }
2986 };
2987
2988 /* l4_cfg -> sata */
2989 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2990         .master         = &dra7xx_l4_cfg_hwmod,
2991         .slave          = &dra7xx_sata_hwmod,
2992         .clk            = "l3_iclk_div",
2993         .addr           = dra7xx_sata_addrs,
2994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2995 };
2996
2997 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2998         {
2999                 .pa_start       = 0x4a0dd000,
3000                 .pa_end         = 0x4a0dd07f,
3001                 .flags          = ADDR_TYPE_RT
3002         },
3003         { }
3004 };
3005
3006 /* l4_cfg -> smartreflex_core */
3007 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3008         .master         = &dra7xx_l4_cfg_hwmod,
3009         .slave          = &dra7xx_smartreflex_core_hwmod,
3010         .clk            = "l4_root_clk_div",
3011         .addr           = dra7xx_smartreflex_core_addrs,
3012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3013 };
3014
3015 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3016         {
3017                 .pa_start       = 0x4a0d9000,
3018                 .pa_end         = 0x4a0d907f,
3019                 .flags          = ADDR_TYPE_RT
3020         },
3021         { }
3022 };
3023
3024 /* l4_cfg -> smartreflex_mpu */
3025 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3026         .master         = &dra7xx_l4_cfg_hwmod,
3027         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3028         .clk            = "l4_root_clk_div",
3029         .addr           = dra7xx_smartreflex_mpu_addrs,
3030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3031 };
3032
3033 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
3034         {
3035                 .pa_start       = 0x4a0f6000,
3036                 .pa_end         = 0x4a0f6fff,
3037                 .flags          = ADDR_TYPE_RT
3038         },
3039         { }
3040 };
3041
3042 /* l4_cfg -> spinlock */
3043 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3044         .master         = &dra7xx_l4_cfg_hwmod,
3045         .slave          = &dra7xx_spinlock_hwmod,
3046         .clk            = "l3_iclk_div",
3047         .addr           = dra7xx_spinlock_addrs,
3048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3049 };
3050
3051 /* l4_wkup -> timer1 */
3052 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3053         .master         = &dra7xx_l4_wkup_hwmod,
3054         .slave          = &dra7xx_timer1_hwmod,
3055         .clk            = "wkupaon_iclk_mux",
3056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3057 };
3058
3059 /* l4_per1 -> timer2 */
3060 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3061         .master         = &dra7xx_l4_per1_hwmod,
3062         .slave          = &dra7xx_timer2_hwmod,
3063         .clk            = "l3_iclk_div",
3064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3065 };
3066
3067 /* l4_per1 -> timer3 */
3068 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3069         .master         = &dra7xx_l4_per1_hwmod,
3070         .slave          = &dra7xx_timer3_hwmod,
3071         .clk            = "l3_iclk_div",
3072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3073 };
3074
3075 /* l4_per1 -> timer4 */
3076 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3077         .master         = &dra7xx_l4_per1_hwmod,
3078         .slave          = &dra7xx_timer4_hwmod,
3079         .clk            = "l3_iclk_div",
3080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3081 };
3082
3083 /* l4_per3 -> timer5 */
3084 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3085         .master         = &dra7xx_l4_per3_hwmod,
3086         .slave          = &dra7xx_timer5_hwmod,
3087         .clk            = "l3_iclk_div",
3088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3089 };
3090
3091 /* l4_per3 -> timer6 */
3092 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3093         .master         = &dra7xx_l4_per3_hwmod,
3094         .slave          = &dra7xx_timer6_hwmod,
3095         .clk            = "l3_iclk_div",
3096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3097 };
3098
3099 /* l4_per3 -> timer7 */
3100 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3101         .master         = &dra7xx_l4_per3_hwmod,
3102         .slave          = &dra7xx_timer7_hwmod,
3103         .clk            = "l3_iclk_div",
3104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3105 };
3106
3107 /* l4_per3 -> timer8 */
3108 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3109         .master         = &dra7xx_l4_per3_hwmod,
3110         .slave          = &dra7xx_timer8_hwmod,
3111         .clk            = "l3_iclk_div",
3112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3113 };
3114
3115 /* l4_per1 -> timer9 */
3116 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3117         .master         = &dra7xx_l4_per1_hwmod,
3118         .slave          = &dra7xx_timer9_hwmod,
3119         .clk            = "l3_iclk_div",
3120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3121 };
3122
3123 /* l4_per1 -> timer10 */
3124 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3125         .master         = &dra7xx_l4_per1_hwmod,
3126         .slave          = &dra7xx_timer10_hwmod,
3127         .clk            = "l3_iclk_div",
3128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3129 };
3130
3131 /* l4_per1 -> timer11 */
3132 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3133         .master         = &dra7xx_l4_per1_hwmod,
3134         .slave          = &dra7xx_timer11_hwmod,
3135         .clk            = "l3_iclk_div",
3136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3137 };
3138
3139 /* l4_per3 -> timer13 */
3140 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3141         .master         = &dra7xx_l4_per3_hwmod,
3142         .slave          = &dra7xx_timer13_hwmod,
3143         .clk            = "l3_iclk_div",
3144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3145 };
3146
3147 /* l4_per3 -> timer14 */
3148 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3149         .master         = &dra7xx_l4_per3_hwmod,
3150         .slave          = &dra7xx_timer14_hwmod,
3151         .clk            = "l3_iclk_div",
3152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3153 };
3154
3155 /* l4_per3 -> timer15 */
3156 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3157         .master         = &dra7xx_l4_per3_hwmod,
3158         .slave          = &dra7xx_timer15_hwmod,
3159         .clk            = "l3_iclk_div",
3160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3161 };
3162
3163 /* l4_per3 -> timer16 */
3164 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3165         .master         = &dra7xx_l4_per3_hwmod,
3166         .slave          = &dra7xx_timer16_hwmod,
3167         .clk            = "l3_iclk_div",
3168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 /* l4_per1 -> uart1 */
3172 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3173         .master         = &dra7xx_l4_per1_hwmod,
3174         .slave          = &dra7xx_uart1_hwmod,
3175         .clk            = "l3_iclk_div",
3176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3177 };
3178
3179 /* l4_per1 -> uart2 */
3180 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3181         .master         = &dra7xx_l4_per1_hwmod,
3182         .slave          = &dra7xx_uart2_hwmod,
3183         .clk            = "l3_iclk_div",
3184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3185 };
3186
3187 /* l4_per1 -> uart3 */
3188 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3189         .master         = &dra7xx_l4_per1_hwmod,
3190         .slave          = &dra7xx_uart3_hwmod,
3191         .clk            = "l3_iclk_div",
3192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3193 };
3194
3195 /* l4_per1 -> uart4 */
3196 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3197         .master         = &dra7xx_l4_per1_hwmod,
3198         .slave          = &dra7xx_uart4_hwmod,
3199         .clk            = "l3_iclk_div",
3200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 /* l4_per1 -> uart5 */
3204 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3205         .master         = &dra7xx_l4_per1_hwmod,
3206         .slave          = &dra7xx_uart5_hwmod,
3207         .clk            = "l3_iclk_div",
3208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3209 };
3210
3211 /* l4_per1 -> uart6 */
3212 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3213         .master         = &dra7xx_l4_per1_hwmod,
3214         .slave          = &dra7xx_uart6_hwmod,
3215         .clk            = "l3_iclk_div",
3216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3218
3219 /* l4_per2 -> uart7 */
3220 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3221         .master         = &dra7xx_l4_per2_hwmod,
3222         .slave          = &dra7xx_uart7_hwmod,
3223         .clk            = "l3_iclk_div",
3224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 /* l4_per2 -> uart8 */
3228 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3229         .master         = &dra7xx_l4_per2_hwmod,
3230         .slave          = &dra7xx_uart8_hwmod,
3231         .clk            = "l3_iclk_div",
3232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3233 };
3234
3235 /* l4_per2 -> uart9 */
3236 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3237         .master         = &dra7xx_l4_per2_hwmod,
3238         .slave          = &dra7xx_uart9_hwmod,
3239         .clk            = "l3_iclk_div",
3240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3241 };
3242
3243 /* l4_wkup -> uart10 */
3244 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3245         .master         = &dra7xx_l4_wkup_hwmod,
3246         .slave          = &dra7xx_uart10_hwmod,
3247         .clk            = "wkupaon_iclk_mux",
3248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3250
3251 /* l4_per3 -> usb_otg_ss1 */
3252 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3253         .master         = &dra7xx_l4_per3_hwmod,
3254         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3255         .clk            = "dpll_core_h13x2_ck",
3256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3257 };
3258
3259 /* l4_per3 -> usb_otg_ss2 */
3260 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3261         .master         = &dra7xx_l4_per3_hwmod,
3262         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3263         .clk            = "dpll_core_h13x2_ck",
3264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3265 };
3266
3267 /* l4_per3 -> usb_otg_ss3 */
3268 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3269         .master         = &dra7xx_l4_per3_hwmod,
3270         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3271         .clk            = "dpll_core_h13x2_ck",
3272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3273 };
3274
3275 /* l4_per3 -> usb_otg_ss4 */
3276 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3277         .master         = &dra7xx_l4_per3_hwmod,
3278         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3279         .clk            = "dpll_core_h13x2_ck",
3280         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3281 };
3282
3283 /* l3_main_1 -> vcp1 */
3284 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3285         .master         = &dra7xx_l3_main_1_hwmod,
3286         .slave          = &dra7xx_vcp1_hwmod,
3287         .clk            = "l3_iclk_div",
3288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3289 };
3290
3291 /* l4_per2 -> vcp1 */
3292 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3293         .master         = &dra7xx_l4_per2_hwmod,
3294         .slave          = &dra7xx_vcp1_hwmod,
3295         .clk            = "l3_iclk_div",
3296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3297 };
3298
3299 /* l3_main_1 -> vcp2 */
3300 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3301         .master         = &dra7xx_l3_main_1_hwmod,
3302         .slave          = &dra7xx_vcp2_hwmod,
3303         .clk            = "l3_iclk_div",
3304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3305 };
3306
3307 /* l4_per2 -> vcp2 */
3308 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3309         .master         = &dra7xx_l4_per2_hwmod,
3310         .slave          = &dra7xx_vcp2_hwmod,
3311         .clk            = "l3_iclk_div",
3312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3313 };
3314
3315 /* l4_wkup -> wd_timer2 */
3316 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3317         .master         = &dra7xx_l4_wkup_hwmod,
3318         .slave          = &dra7xx_wd_timer2_hwmod,
3319         .clk            = "wkupaon_iclk_mux",
3320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3324         &dra7xx_l3_main_1__dmm,
3325         &dra7xx_l3_main_2__l3_instr,
3326         &dra7xx_l4_cfg__l3_main_1,
3327         &dra7xx_mpu__l3_main_1,
3328         &dra7xx_l3_main_1__l3_main_2,
3329         &dra7xx_l4_cfg__l3_main_2,
3330         &dra7xx_l3_main_1__l4_cfg,
3331         &dra7xx_l3_main_1__l4_per1,
3332         &dra7xx_l3_main_1__l4_per2,
3333         &dra7xx_l3_main_1__l4_per3,
3334         &dra7xx_l3_main_1__l4_wkup,
3335         &dra7xx_l4_per2__atl,
3336         &dra7xx_l3_main_1__bb2d,
3337         &dra7xx_l4_wkup__counter_32k,
3338         &dra7xx_l4_wkup__ctrl_module_wkup,
3339         &dra7xx_l4_wkup__dcan1,
3340         &dra7xx_l4_per2__dcan2,
3341         &dra7xx_l4_per2__cpgmac0,
3342         &dra7xx_gmac__mdio,
3343         &dra7xx_l4_cfg__dma_system,
3344         &dra7xx_l3_main_1__dss,
3345         &dra7xx_l3_main_1__dispc,
3346         &dra7xx_l3_main_1__hdmi,
3347         &dra7xx_l4_per1__elm,
3348         &dra7xx_l4_wkup__gpio1,
3349         &dra7xx_l4_per1__gpio2,
3350         &dra7xx_l4_per1__gpio3,
3351         &dra7xx_l4_per1__gpio4,
3352         &dra7xx_l4_per1__gpio5,
3353         &dra7xx_l4_per1__gpio6,
3354         &dra7xx_l4_per1__gpio7,
3355         &dra7xx_l4_per1__gpio8,
3356         &dra7xx_l3_main_1__gpmc,
3357         &dra7xx_l4_per1__hdq1w,
3358         &dra7xx_l4_per1__i2c1,
3359         &dra7xx_l4_per1__i2c2,
3360         &dra7xx_l4_per1__i2c3,
3361         &dra7xx_l4_per1__i2c4,
3362         &dra7xx_l4_per1__i2c5,
3363         &dra7xx_l4_cfg__mailbox1,
3364         &dra7xx_l4_per3__mailbox2,
3365         &dra7xx_l4_per3__mailbox3,
3366         &dra7xx_l4_per3__mailbox4,
3367         &dra7xx_l4_per3__mailbox5,
3368         &dra7xx_l4_per3__mailbox6,
3369         &dra7xx_l4_per3__mailbox7,
3370         &dra7xx_l4_per3__mailbox8,
3371         &dra7xx_l4_per3__mailbox9,
3372         &dra7xx_l4_per3__mailbox10,
3373         &dra7xx_l4_per3__mailbox11,
3374         &dra7xx_l4_per3__mailbox12,
3375         &dra7xx_l4_per3__mailbox13,
3376         &dra7xx_l4_per1__mcspi1,
3377         &dra7xx_l4_per1__mcspi2,
3378         &dra7xx_l4_per1__mcspi3,
3379         &dra7xx_l4_per1__mcspi4,
3380         &dra7xx_l4_per1__mmc1,
3381         &dra7xx_l4_per1__mmc2,
3382         &dra7xx_l4_per1__mmc3,
3383         &dra7xx_l4_per1__mmc4,
3384         &dra7xx_l4_cfg__mpu,
3385         &dra7xx_l4_cfg__ocp2scp1,
3386         &dra7xx_l4_cfg__ocp2scp3,
3387         &dra7xx_l3_main_1__pciess1,
3388         &dra7xx_l4_cfg__pciess1,
3389         &dra7xx_l3_main_1__pciess2,
3390         &dra7xx_l4_cfg__pciess2,
3391         &dra7xx_l3_main_1__qspi,
3392         &dra7xx_l4_per3__rtcss,
3393         &dra7xx_l4_cfg__sata,
3394         &dra7xx_l4_cfg__smartreflex_core,
3395         &dra7xx_l4_cfg__smartreflex_mpu,
3396         &dra7xx_l4_cfg__spinlock,
3397         &dra7xx_l4_wkup__timer1,
3398         &dra7xx_l4_per1__timer2,
3399         &dra7xx_l4_per1__timer3,
3400         &dra7xx_l4_per1__timer4,
3401         &dra7xx_l4_per3__timer5,
3402         &dra7xx_l4_per3__timer6,
3403         &dra7xx_l4_per3__timer7,
3404         &dra7xx_l4_per3__timer8,
3405         &dra7xx_l4_per1__timer9,
3406         &dra7xx_l4_per1__timer10,
3407         &dra7xx_l4_per1__timer11,
3408         &dra7xx_l4_per3__timer13,
3409         &dra7xx_l4_per3__timer14,
3410         &dra7xx_l4_per3__timer15,
3411         &dra7xx_l4_per3__timer16,
3412         &dra7xx_l4_per1__uart1,
3413         &dra7xx_l4_per1__uart2,
3414         &dra7xx_l4_per1__uart3,
3415         &dra7xx_l4_per1__uart4,
3416         &dra7xx_l4_per1__uart5,
3417         &dra7xx_l4_per1__uart6,
3418         &dra7xx_l4_per2__uart7,
3419         &dra7xx_l4_per2__uart8,
3420         &dra7xx_l4_per2__uart9,
3421         &dra7xx_l4_wkup__uart10,
3422         &dra7xx_l4_per3__usb_otg_ss1,
3423         &dra7xx_l4_per3__usb_otg_ss2,
3424         &dra7xx_l4_per3__usb_otg_ss3,
3425         &dra7xx_l3_main_1__vcp1,
3426         &dra7xx_l4_per2__vcp1,
3427         &dra7xx_l3_main_1__vcp2,
3428         &dra7xx_l4_per2__vcp2,
3429         &dra7xx_l4_wkup__wd_timer2,
3430         NULL,
3431 };
3432
3433 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3434         &dra7xx_l4_per3__usb_otg_ss4,
3435         NULL,
3436 };
3437
3438 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3439         NULL,
3440 };
3441
3442 int __init dra7xx_hwmod_init(void)
3443 {
3444         int ret;
3445
3446         omap_hwmod_init();
3447         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3448
3449         if (!ret && soc_is_dra74x())
3450                 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3451         else if (!ret && soc_is_dra72x())
3452                 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3453
3454         return ret;
3455 }