arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'dmm' class
  53  * instance(s): dmm
  54  */
  55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  56         .name   = "dmm",
  57 };
  58
  59 /* dmm */
  60 static struct omap_hwmod dra7xx_dmm_hwmod = {
  61         .name           = "dmm",
  62         .class          = &dra7xx_dmm_hwmod_class,
  63         .clkdm_name     = "emif_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  68                 },
  69         },
  70 };
  71
  72 /*
  73  * 'l3' class
  74  * instance(s): l3_instr, l3_main_1, l3_main_2
  75  */
  76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  77         .name   = "l3",
  78 };
  79
  80 /* l3_instr */
  81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  82         .name           = "l3_instr",
  83         .class          = &dra7xx_l3_hwmod_class,
  84         .clkdm_name     = "l3instr_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  88                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  89                         .modulemode   = MODULEMODE_HWCTRL,
  90                 },
  91         },
  92 };
  93
  94 /* l3_main_1 */
  95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  96         .name           = "l3_main_1",
  97         .class          = &dra7xx_l3_hwmod_class,
  98         .clkdm_name     = "l3main1_clkdm",
  99         .prcm = {
 100                 .omap4 = {
 101                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 102                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 103                 },
 104         },
 105 };
 106
 107 /* l3_main_2 */
 108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
 109         .name           = "l3_main_2",
 110         .class          = &dra7xx_l3_hwmod_class,
 111         .clkdm_name     = "l3instr_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 115                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 116                         .modulemode   = MODULEMODE_HWCTRL,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l4' class
 123  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 124  */
 125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 126         .name   = "l4",
 127 };
 128
 129 /* l4_cfg */
 130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 131         .name           = "l4_cfg",
 132         .class          = &dra7xx_l4_hwmod_class,
 133         .clkdm_name     = "l4cfg_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 137                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /* l4_per1 */
 143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 144         .name           = "l4_per1",
 145         .class          = &dra7xx_l4_hwmod_class,
 146         .clkdm_name     = "l4per_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 150                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per2 */
 156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 157         .name           = "l4_per2",
 158         .class          = &dra7xx_l4_hwmod_class,
 159         .clkdm_name     = "l4per2_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 163                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 164                 },
 165         },
 166 };
 167
 168 /* l4_per3 */
 169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 170         .name           = "l4_per3",
 171         .class          = &dra7xx_l4_hwmod_class,
 172         .clkdm_name     = "l4per3_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 176                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 177                 },
 178         },
 179 };
 180
 181 /* l4_wkup */
 182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 183         .name           = "l4_wkup",
 184         .class          = &dra7xx_l4_hwmod_class,
 185         .clkdm_name     = "wkupaon_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 189                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'atl' class
 196  *
 197  */
 198
 199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 200         .name   = "atl",
 201 };
 202
 203 /* atl */
 204 static struct omap_hwmod dra7xx_atl_hwmod = {
 205         .name           = "atl",
 206         .class          = &dra7xx_atl_hwmod_class,
 207         .clkdm_name     = "atl_clkdm",
 208         .main_clk       = "atl_gfclk_mux",
 209         .prcm = {
 210                 .omap4 = {
 211                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 212                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 213                         .modulemode   = MODULEMODE_SWCTRL,
 214                 },
 215         },
 216 };
 217
 218 /*
 219  * 'bb2d' class
 220  *
 221  */
 222
 223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 224         .name   = "bb2d",
 225 };
 226
 227 /* bb2d */
 228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 229         .name           = "bb2d",
 230         .class          = &dra7xx_bb2d_hwmod_class,
 231         .clkdm_name     = "dss_clkdm",
 232         .main_clk       = "dpll_core_h24x2_ck",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 236                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 237                         .modulemode   = MODULEMODE_SWCTRL,
 238                 },
 239         },
 240 };
 241
 242 /*
 243  * 'counter' class
 244  *
 245  */
 246
 247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 248         .rev_offs       = 0x0000,
 249         .sysc_offs      = 0x0010,
 250         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 252                            SIDLE_SMART_WKUP),
 253         .sysc_fields    = &omap_hwmod_sysc_type1,
 254 };
 255
 256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 257         .name   = "counter",
 258         .sysc   = &dra7xx_counter_sysc,
 259 };
 260
 261 /* counter_32k */
 262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 263         .name           = "counter_32k",
 264         .class          = &dra7xx_counter_hwmod_class,
 265         .clkdm_name     = "wkupaon_clkdm",
 266         .flags          = HWMOD_SWSUP_SIDLE,
 267         .main_clk       = "wkupaon_iclk_mux",
 268         .prcm = {
 269                 .omap4 = {
 270                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 271                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'ctrl_module' class
 278  *
 279  */
 280
 281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 282         .name   = "ctrl_module",
 283 };
 284
 285 /* ctrl_module_wkup */
 286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 287         .name           = "ctrl_module_wkup",
 288         .class          = &dra7xx_ctrl_module_hwmod_class,
 289         .clkdm_name     = "wkupaon_clkdm",
 290         .prcm = {
 291                 .omap4 = {
 292                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * 'gmac' class
 299  * cpsw/gmac sub system
 300  */
 301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 302         .rev_offs       = 0x0,
 303         .sysc_offs      = 0x8,
 304         .syss_offs      = 0x4,
 305         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 306                            SYSS_HAS_RESET_STATUS),
 307         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 308                            MSTANDBY_NO),
 309         .sysc_fields    = &omap_hwmod_sysc_type3,
 310 };
 311
 312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 313         .name           = "gmac",
 314         .sysc           = &dra7xx_gmac_sysc,
 315 };
 316
 317 static struct omap_hwmod dra7xx_gmac_hwmod = {
 318         .name           = "gmac",
 319         .class          = &dra7xx_gmac_hwmod_class,
 320         .clkdm_name     = "gmac_clkdm",
 321         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 322         .main_clk       = "dpll_gmac_ck",
 323         .mpu_rt_idx     = 1,
 324         .prcm           = {
 325                 .omap4  = {
 326                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 327                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 328                         .modulemode     = MODULEMODE_SWCTRL,
 329                 },
 330         },
 331 };
 332
 333 /*
 334  * 'mdio' class
 335  */
 336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 337         .name           = "davinci_mdio",
 338 };
 339
 340 static struct omap_hwmod dra7xx_mdio_hwmod = {
 341         .name           = "davinci_mdio",
 342         .class          = &dra7xx_mdio_hwmod_class,
 343         .clkdm_name     = "gmac_clkdm",
 344         .main_clk       = "dpll_gmac_ck",
 345 };
 346
 347 /*
 348  * 'dcan' class
 349  *
 350  */
 351
 352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 353         .name   = "dcan",
 354 };
 355
 356 /* dcan1 */
 357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 358         .name           = "dcan1",
 359         .class          = &dra7xx_dcan_hwmod_class,
 360         .clkdm_name     = "wkupaon_clkdm",
 361         .main_clk       = "dcan1_sys_clk_mux",
 362         .prcm = {
 363                 .omap4 = {
 364                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 365                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 366                         .modulemode   = MODULEMODE_SWCTRL,
 367                 },
 368         },
 369 };
 370
 371 /* dcan2 */
 372 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 373         .name           = "dcan2",
 374         .class          = &dra7xx_dcan_hwmod_class,
 375         .clkdm_name     = "l4per2_clkdm",
 376         .main_clk       = "sys_clkin1",
 377         .prcm = {
 378                 .omap4 = {
 379                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 380                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 381                         .modulemode   = MODULEMODE_SWCTRL,
 382                 },
 383         },
 384 };
 385
 386 /* pwmss  */
 387 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
 388         .rev_offs       = 0x0,
 389         .sysc_offs      = 0x4,
 390         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 391         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 392         .sysc_fields    = &omap_hwmod_sysc_type2,
 393 };
 394
 395 /*
 396  * epwmss class
 397  */
 398 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
 399         .name           = "epwmss",
 400         .sysc           = &dra7xx_epwmss_sysc,
 401 };
 402
 403 /* epwmss0 */
 404 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
 405         .name           = "epwmss0",
 406         .class          = &dra7xx_epwmss_hwmod_class,
 407         .clkdm_name     = "l4per2_clkdm",
 408         .main_clk       = "l4_root_clk_div",
 409         .prcm           = {
 410                 .omap4  = {
 411                         .modulemode     = MODULEMODE_SWCTRL,
 412                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
 413                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
 414                 },
 415         },
 416 };
 417
 418 /* epwmss1 */
 419 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
 420         .name           = "epwmss1",
 421         .class          = &dra7xx_epwmss_hwmod_class,
 422         .clkdm_name     = "l4per2_clkdm",
 423         .main_clk       = "l4_root_clk_div",
 424         .prcm           = {
 425                 .omap4  = {
 426                         .modulemode     = MODULEMODE_SWCTRL,
 427                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
 428                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
 429                 },
 430         },
 431 };
 432
 433 /* epwmss2 */
 434 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
 435         .name           = "epwmss2",
 436         .class          = &dra7xx_epwmss_hwmod_class,
 437         .clkdm_name     = "l4per2_clkdm",
 438         .main_clk       = "l4_root_clk_div",
 439         .prcm           = {
 440                 .omap4  = {
 441                         .modulemode     = MODULEMODE_SWCTRL,
 442                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
 443                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
 444                 },
 445         },
 446 };
 447
 448 /*
 449  * 'dma' class
 450  *
 451  */
 452
 453 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 454         .rev_offs       = 0x0000,
 455         .sysc_offs      = 0x002c,
 456         .syss_offs      = 0x0028,
 457         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 458                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 459                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 460                            SYSS_HAS_RESET_STATUS),
 461         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 462                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 463                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 464         .sysc_fields    = &omap_hwmod_sysc_type1,
 465 };
 466
 467 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 468         .name   = "dma",
 469         .sysc   = &dra7xx_dma_sysc,
 470 };
 471
 472 /* dma dev_attr */
 473 static struct omap_dma_dev_attr dma_dev_attr = {
 474         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 475                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 476         .lch_count      = 32,
 477 };
 478
 479 /* dma_system */
 480 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 481         .name           = "dma_system",
 482         .class          = &dra7xx_dma_hwmod_class,
 483         .clkdm_name     = "dma_clkdm",
 484         .main_clk       = "l3_iclk_div",
 485         .prcm = {
 486                 .omap4 = {
 487                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 488                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 489                 },
 490         },
 491         .dev_attr       = &dma_dev_attr,
 492 };
 493
 494 /*
 495  * 'tpcc' class
 496  *
 497  */
 498 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 499         .name           = "tpcc",
 500 };
 501
 502 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 503         .name           = "tpcc",
 504         .class          = &dra7xx_tpcc_hwmod_class,
 505         .clkdm_name     = "l3main1_clkdm",
 506         .main_clk       = "l3_iclk_div",
 507         .prcm           = {
 508                 .omap4  = {
 509                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 510                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 511                 },
 512         },
 513 };
 514
 515 /*
 516  * 'tptc' class
 517  *
 518  */
 519 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 520         .name           = "tptc",
 521 };
 522
 523 /* tptc0 */
 524 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 525         .name           = "tptc0",
 526         .class          = &dra7xx_tptc_hwmod_class,
 527         .clkdm_name     = "l3main1_clkdm",
 528         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 529         .main_clk       = "l3_iclk_div",
 530         .prcm           = {
 531                 .omap4  = {
 532                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 533                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 534                         .modulemode   = MODULEMODE_HWCTRL,
 535                 },
 536         },
 537 };
 538
 539 /* tptc1 */
 540 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 541         .name           = "tptc1",
 542         .class          = &dra7xx_tptc_hwmod_class,
 543         .clkdm_name     = "l3main1_clkdm",
 544         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 545         .main_clk       = "l3_iclk_div",
 546         .prcm           = {
 547                 .omap4  = {
 548                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 549                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 550                         .modulemode   = MODULEMODE_HWCTRL,
 551                 },
 552         },
 553 };
 554
 555 /*
 556  * 'dss' class
 557  *
 558  */
 559
 560 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 561         .rev_offs       = 0x0000,
 562         .syss_offs      = 0x0014,
 563         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 564 };
 565
 566 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 567         .name   = "dss",
 568         .sysc   = &dra7xx_dss_sysc,
 569         .reset  = omap_dss_reset,
 570 };
 571
 572 /* dss */
 573 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 574         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 575         { .dma_req = -1 }
 576 };
 577
 578 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 579         { .role = "dss_clk", .clk = "dss_dss_clk" },
 580         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 581         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 582         { .role = "video2_clk", .clk = "dss_video2_clk" },
 583         { .role = "video1_clk", .clk = "dss_video1_clk" },
 584         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 585         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 586 };
 587
 588 static struct omap_hwmod dra7xx_dss_hwmod = {
 589         .name           = "dss_core",
 590         .class          = &dra7xx_dss_hwmod_class,
 591         .clkdm_name     = "dss_clkdm",
 592         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 593         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 594         .main_clk       = "dss_dss_clk",
 595         .prcm = {
 596                 .omap4 = {
 597                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 598                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 599                         .modulemode   = MODULEMODE_SWCTRL,
 600                 },
 601         },
 602         .opt_clks       = dss_opt_clks,
 603         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 604 };
 605
 606 /*
 607  * 'dispc' class
 608  * display controller
 609  */
 610
 611 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 612         .rev_offs       = 0x0000,
 613         .sysc_offs      = 0x0010,
 614         .syss_offs      = 0x0014,
 615         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 616                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 617                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 618                            SYSS_HAS_RESET_STATUS),
 619         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 620                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 621         .sysc_fields    = &omap_hwmod_sysc_type1,
 622 };
 623
 624 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 625         .name   = "dispc",
 626         .sysc   = &dra7xx_dispc_sysc,
 627 };
 628
 629 /* dss_dispc */
 630 /* dss_dispc dev_attr */
 631 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 632         .has_framedonetv_irq    = 1,
 633         .manager_count          = 4,
 634 };
 635
 636 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 637         .name           = "dss_dispc",
 638         .class          = &dra7xx_dispc_hwmod_class,
 639         .clkdm_name     = "dss_clkdm",
 640         .main_clk       = "dss_dss_clk",
 641         .prcm = {
 642                 .omap4 = {
 643                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 644                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 645                 },
 646         },
 647         .dev_attr       = &dss_dispc_dev_attr,
 648         .parent_hwmod   = &dra7xx_dss_hwmod,
 649 };
 650
 651 /*
 652  * 'hdmi' class
 653  * hdmi controller
 654  */
 655
 656 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 657         .rev_offs       = 0x0000,
 658         .sysc_offs      = 0x0010,
 659         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 660                            SYSC_HAS_SOFTRESET),
 661         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 662                            SIDLE_SMART_WKUP),
 663         .sysc_fields    = &omap_hwmod_sysc_type2,
 664 };
 665
 666 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 667         .name   = "hdmi",
 668         .sysc   = &dra7xx_hdmi_sysc,
 669 };
 670
 671 /* dss_hdmi */
 672
 673 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 674         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 675 };
 676
 677 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 678         .name           = "dss_hdmi",
 679         .class          = &dra7xx_hdmi_hwmod_class,
 680         .clkdm_name     = "dss_clkdm",
 681         .main_clk       = "dss_48mhz_clk",
 682         .prcm = {
 683                 .omap4 = {
 684                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 685                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 686                 },
 687         },
 688         .opt_clks       = dss_hdmi_opt_clks,
 689         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 690         .parent_hwmod   = &dra7xx_dss_hwmod,
 691 };
 692
 693 /* AES (the 'P' (public) device) */
 694 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
 695         .rev_offs       = 0x0080,
 696         .sysc_offs      = 0x0084,
 697         .syss_offs      = 0x0088,
 698         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 699 };
 700
 701 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
 702         .name   = "aes",
 703         .sysc   = &dra7xx_aes_sysc,
 704         .rev    = 2,
 705 };
 706
 707 /* AES1 */
 708 static struct omap_hwmod dra7xx_aes1_hwmod = {
 709         .name           = "aes1",
 710         .class          = &dra7xx_aes_hwmod_class,
 711         .clkdm_name     = "l4sec_clkdm",
 712         .main_clk       = "l3_iclk_div",
 713         .prcm = {
 714                 .omap4 = {
 715                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 716                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
 717                         .modulemode   = MODULEMODE_HWCTRL,
 718                 },
 719         },
 720 };
 721
 722 /* AES2 */
 723 static struct omap_hwmod dra7xx_aes2_hwmod = {
 724         .name           = "aes2",
 725         .class          = &dra7xx_aes_hwmod_class,
 726         .clkdm_name     = "l4sec_clkdm",
 727         .main_clk       = "l3_iclk_div",
 728         .prcm = {
 729                 .omap4 = {
 730                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 731                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
 732                         .modulemode   = MODULEMODE_HWCTRL,
 733                 },
 734         },
 735 };
 736
 737 /* sha0 HIB2 (the 'P' (public) device) */
 738 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
 739         .rev_offs       = 0x100,
 740         .sysc_offs      = 0x110,
 741         .syss_offs      = 0x114,
 742         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 743 };
 744
 745 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
 746         .name           = "sham",
 747         .sysc           = &dra7xx_sha0_sysc,
 748         .rev            = 2,
 749 };
 750
 751 struct omap_hwmod dra7xx_sha0_hwmod = {
 752         .name           = "sham",
 753         .class          = &dra7xx_sha0_hwmod_class,
 754         .clkdm_name     = "l4sec_clkdm",
 755         .main_clk       = "l3_iclk_div",
 756         .prcm           = {
 757                 .omap4 = {
 758                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 759                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 760                         .modulemode   = MODULEMODE_HWCTRL,
 761                 },
 762         },
 763 };
 764
 765 /*
 766  * 'elm' class
 767  *
 768  */
 769
 770 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 771         .rev_offs       = 0x0000,
 772         .sysc_offs      = 0x0010,
 773         .syss_offs      = 0x0014,
 774         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 775                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 776                            SYSS_HAS_RESET_STATUS),
 777         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 778                            SIDLE_SMART_WKUP),
 779         .sysc_fields    = &omap_hwmod_sysc_type1,
 780 };
 781
 782 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 783         .name   = "elm",
 784         .sysc   = &dra7xx_elm_sysc,
 785 };
 786
 787 /* elm */
 788
 789 static struct omap_hwmod dra7xx_elm_hwmod = {
 790         .name           = "elm",
 791         .class          = &dra7xx_elm_hwmod_class,
 792         .clkdm_name     = "l4per_clkdm",
 793         .main_clk       = "l3_iclk_div",
 794         .prcm = {
 795                 .omap4 = {
 796                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 797                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 798                 },
 799         },
 800 };
 801
 802 /*
 803  * 'gpio' class
 804  *
 805  */
 806
 807 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 808         .rev_offs       = 0x0000,
 809         .sysc_offs      = 0x0010,
 810         .syss_offs      = 0x0114,
 811         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 812                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 813                            SYSS_HAS_RESET_STATUS),
 814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 815                            SIDLE_SMART_WKUP),
 816         .sysc_fields    = &omap_hwmod_sysc_type1,
 817 };
 818
 819 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 820         .name   = "gpio",
 821         .sysc   = &dra7xx_gpio_sysc,
 822         .rev    = 2,
 823 };
 824
 825 /* gpio dev_attr */
 826 static struct omap_gpio_dev_attr gpio_dev_attr = {
 827         .bank_width     = 32,
 828         .dbck_flag      = true,
 829 };
 830
 831 /* gpio1 */
 832 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 833         { .role = "dbclk", .clk = "gpio1_dbclk" },
 834 };
 835
 836 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 837         .name           = "gpio1",
 838         .class          = &dra7xx_gpio_hwmod_class,
 839         .clkdm_name     = "wkupaon_clkdm",
 840         .main_clk       = "wkupaon_iclk_mux",
 841         .prcm = {
 842                 .omap4 = {
 843                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 844                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 845                         .modulemode   = MODULEMODE_HWCTRL,
 846                 },
 847         },
 848         .opt_clks       = gpio1_opt_clks,
 849         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 850         .dev_attr       = &gpio_dev_attr,
 851 };
 852
 853 /* gpio2 */
 854 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 855         { .role = "dbclk", .clk = "gpio2_dbclk" },
 856 };
 857
 858 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 859         .name           = "gpio2",
 860         .class          = &dra7xx_gpio_hwmod_class,
 861         .clkdm_name     = "l4per_clkdm",
 862         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 863         .main_clk       = "l3_iclk_div",
 864         .prcm = {
 865                 .omap4 = {
 866                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 867                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 868                         .modulemode   = MODULEMODE_HWCTRL,
 869                 },
 870         },
 871         .opt_clks       = gpio2_opt_clks,
 872         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 873         .dev_attr       = &gpio_dev_attr,
 874 };
 875
 876 /* gpio3 */
 877 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 878         { .role = "dbclk", .clk = "gpio3_dbclk" },
 879 };
 880
 881 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 882         .name           = "gpio3",
 883         .class          = &dra7xx_gpio_hwmod_class,
 884         .clkdm_name     = "l4per_clkdm",
 885         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 886         .main_clk       = "l3_iclk_div",
 887         .prcm = {
 888                 .omap4 = {
 889                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 890                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 891                         .modulemode   = MODULEMODE_HWCTRL,
 892                 },
 893         },
 894         .opt_clks       = gpio3_opt_clks,
 895         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 896         .dev_attr       = &gpio_dev_attr,
 897 };
 898
 899 /* gpio4 */
 900 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 901         { .role = "dbclk", .clk = "gpio4_dbclk" },
 902 };
 903
 904 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 905         .name           = "gpio4",
 906         .class          = &dra7xx_gpio_hwmod_class,
 907         .clkdm_name     = "l4per_clkdm",
 908         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 909         .main_clk       = "l3_iclk_div",
 910         .prcm = {
 911                 .omap4 = {
 912                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 913                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 914                         .modulemode   = MODULEMODE_HWCTRL,
 915                 },
 916         },
 917         .opt_clks       = gpio4_opt_clks,
 918         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 919         .dev_attr       = &gpio_dev_attr,
 920 };
 921
 922 /* gpio5 */
 923 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 924         { .role = "dbclk", .clk = "gpio5_dbclk" },
 925 };
 926
 927 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 928         .name           = "gpio5",
 929         .class          = &dra7xx_gpio_hwmod_class,
 930         .clkdm_name     = "l4per_clkdm",
 931         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 932         .main_clk       = "l3_iclk_div",
 933         .prcm = {
 934                 .omap4 = {
 935                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 936                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 937                         .modulemode   = MODULEMODE_HWCTRL,
 938                 },
 939         },
 940         .opt_clks       = gpio5_opt_clks,
 941         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 942         .dev_attr       = &gpio_dev_attr,
 943 };
 944
 945 /* gpio6 */
 946 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 947         { .role = "dbclk", .clk = "gpio6_dbclk" },
 948 };
 949
 950 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 951         .name           = "gpio6",
 952         .class          = &dra7xx_gpio_hwmod_class,
 953         .clkdm_name     = "l4per_clkdm",
 954         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 955         .main_clk       = "l3_iclk_div",
 956         .prcm = {
 957                 .omap4 = {
 958                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 959                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 960                         .modulemode   = MODULEMODE_HWCTRL,
 961                 },
 962         },
 963         .opt_clks       = gpio6_opt_clks,
 964         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 965         .dev_attr       = &gpio_dev_attr,
 966 };
 967
 968 /* gpio7 */
 969 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 970         { .role = "dbclk", .clk = "gpio7_dbclk" },
 971 };
 972
 973 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 974         .name           = "gpio7",
 975         .class          = &dra7xx_gpio_hwmod_class,
 976         .clkdm_name     = "l4per_clkdm",
 977         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 978         .main_clk       = "l3_iclk_div",
 979         .prcm = {
 980                 .omap4 = {
 981                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 982                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 983                         .modulemode   = MODULEMODE_HWCTRL,
 984                 },
 985         },
 986         .opt_clks       = gpio7_opt_clks,
 987         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 988         .dev_attr       = &gpio_dev_attr,
 989 };
 990
 991 /* gpio8 */
 992 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 993         { .role = "dbclk", .clk = "gpio8_dbclk" },
 994 };
 995
 996 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 997         .name           = "gpio8",
 998         .class          = &dra7xx_gpio_hwmod_class,
 999         .clkdm_name     = "l4per_clkdm",
1000         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1001         .main_clk       = "l3_iclk_div",
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1005                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1006                         .modulemode   = MODULEMODE_HWCTRL,
1007                 },
1008         },
1009         .opt_clks       = gpio8_opt_clks,
1010         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
1011         .dev_attr       = &gpio_dev_attr,
1012 };
1013
1014 /*
1015  * 'gpmc' class
1016  *
1017  */
1018
1019 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1020         .rev_offs       = 0x0000,
1021         .sysc_offs      = 0x0010,
1022         .syss_offs      = 0x0014,
1023         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1024                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1025         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1026         .sysc_fields    = &omap_hwmod_sysc_type1,
1027 };
1028
1029 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1030         .name   = "gpmc",
1031         .sysc   = &dra7xx_gpmc_sysc,
1032 };
1033
1034 /* gpmc */
1035
1036 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1037         .name           = "gpmc",
1038         .class          = &dra7xx_gpmc_hwmod_class,
1039         .clkdm_name     = "l3main1_clkdm",
1040         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1041         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1042         .main_clk       = "l3_iclk_div",
1043         .prcm = {
1044                 .omap4 = {
1045                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1046                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1047                         .modulemode   = MODULEMODE_HWCTRL,
1048                 },
1049         },
1050 };
1051
1052 /*
1053  * 'hdq1w' class
1054  *
1055  */
1056
1057 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1058         .rev_offs       = 0x0000,
1059         .sysc_offs      = 0x0014,
1060         .syss_offs      = 0x0018,
1061         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1062                            SYSS_HAS_RESET_STATUS),
1063         .sysc_fields    = &omap_hwmod_sysc_type1,
1064 };
1065
1066 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1067         .name   = "hdq1w",
1068         .sysc   = &dra7xx_hdq1w_sysc,
1069 };
1070
1071 /* hdq1w */
1072
1073 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1074         .name           = "hdq1w",
1075         .class          = &dra7xx_hdq1w_hwmod_class,
1076         .clkdm_name     = "l4per_clkdm",
1077         .flags          = HWMOD_INIT_NO_RESET,
1078         .main_clk       = "func_12m_fclk",
1079         .prcm = {
1080                 .omap4 = {
1081                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1082                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1083                         .modulemode   = MODULEMODE_SWCTRL,
1084                 },
1085         },
1086 };
1087
1088 /*
1089  * 'i2c' class
1090  *
1091  */
1092
1093 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1094         .sysc_offs      = 0x0010,
1095         .syss_offs      = 0x0090,
1096         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1097                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1098                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1099         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1100                            SIDLE_SMART_WKUP),
1101         .clockact       = CLOCKACT_TEST_ICLK,
1102         .sysc_fields    = &omap_hwmod_sysc_type1,
1103 };
1104
1105 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1106         .name   = "i2c",
1107         .sysc   = &dra7xx_i2c_sysc,
1108         .reset  = &omap_i2c_reset,
1109         .rev    = OMAP_I2C_IP_VERSION_2,
1110 };
1111
1112 /* i2c dev_attr */
1113 static struct omap_i2c_dev_attr i2c_dev_attr = {
1114         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1115 };
1116
1117 /* i2c1 */
1118 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1119         .name           = "i2c1",
1120         .class          = &dra7xx_i2c_hwmod_class,
1121         .clkdm_name     = "l4per_clkdm",
1122         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1123         .main_clk       = "func_96m_fclk",
1124         .prcm = {
1125                 .omap4 = {
1126                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1127                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1128                         .modulemode   = MODULEMODE_SWCTRL,
1129                 },
1130         },
1131         .dev_attr       = &i2c_dev_attr,
1132 };
1133
1134 /* i2c2 */
1135 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1136         .name           = "i2c2",
1137         .class          = &dra7xx_i2c_hwmod_class,
1138         .clkdm_name     = "l4per_clkdm",
1139         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1140         .main_clk       = "func_96m_fclk",
1141         .prcm = {
1142                 .omap4 = {
1143                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1144                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1145                         .modulemode   = MODULEMODE_SWCTRL,
1146                 },
1147         },
1148         .dev_attr       = &i2c_dev_attr,
1149 };
1150
1151 /* i2c3 */
1152 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1153         .name           = "i2c3",
1154         .class          = &dra7xx_i2c_hwmod_class,
1155         .clkdm_name     = "l4per_clkdm",
1156         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1157         .main_clk       = "func_96m_fclk",
1158         .prcm = {
1159                 .omap4 = {
1160                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1161                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1162                         .modulemode   = MODULEMODE_SWCTRL,
1163                 },
1164         },
1165         .dev_attr       = &i2c_dev_attr,
1166 };
1167
1168 /* i2c4 */
1169 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1170         .name           = "i2c4",
1171         .class          = &dra7xx_i2c_hwmod_class,
1172         .clkdm_name     = "l4per_clkdm",
1173         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1174         .main_clk       = "func_96m_fclk",
1175         .prcm = {
1176                 .omap4 = {
1177                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1178                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1179                         .modulemode   = MODULEMODE_SWCTRL,
1180                 },
1181         },
1182         .dev_attr       = &i2c_dev_attr,
1183 };
1184
1185 /* i2c5 */
1186 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1187         .name           = "i2c5",
1188         .class          = &dra7xx_i2c_hwmod_class,
1189         .clkdm_name     = "ipu_clkdm",
1190         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1191         .main_clk       = "func_96m_fclk",
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1195                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_SWCTRL,
1197                 },
1198         },
1199         .dev_attr       = &i2c_dev_attr,
1200 };
1201
1202 /*
1203  * 'mailbox' class
1204  *
1205  */
1206
1207 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1208         .rev_offs       = 0x0000,
1209         .sysc_offs      = 0x0010,
1210         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1211                            SYSC_HAS_SOFTRESET),
1212         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1213         .sysc_fields    = &omap_hwmod_sysc_type2,
1214 };
1215
1216 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1217         .name   = "mailbox",
1218         .sysc   = &dra7xx_mailbox_sysc,
1219 };
1220
1221 /* mailbox1 */
1222 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1223         .name           = "mailbox1",
1224         .class          = &dra7xx_mailbox_hwmod_class,
1225         .clkdm_name     = "l4cfg_clkdm",
1226         .prcm = {
1227                 .omap4 = {
1228                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1229                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1230                 },
1231         },
1232 };
1233
1234 /* mailbox2 */
1235 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1236         .name           = "mailbox2",
1237         .class          = &dra7xx_mailbox_hwmod_class,
1238         .clkdm_name     = "l4cfg_clkdm",
1239         .prcm = {
1240                 .omap4 = {
1241                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1242                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1243                 },
1244         },
1245 };
1246
1247 /* mailbox3 */
1248 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1249         .name           = "mailbox3",
1250         .class          = &dra7xx_mailbox_hwmod_class,
1251         .clkdm_name     = "l4cfg_clkdm",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1255                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1256                 },
1257         },
1258 };
1259
1260 /* mailbox4 */
1261 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1262         .name           = "mailbox4",
1263         .class          = &dra7xx_mailbox_hwmod_class,
1264         .clkdm_name     = "l4cfg_clkdm",
1265         .prcm = {
1266                 .omap4 = {
1267                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1268                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1269                 },
1270         },
1271 };
1272
1273 /* mailbox5 */
1274 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1275         .name           = "mailbox5",
1276         .class          = &dra7xx_mailbox_hwmod_class,
1277         .clkdm_name     = "l4cfg_clkdm",
1278         .prcm = {
1279                 .omap4 = {
1280                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1281                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1282                 },
1283         },
1284 };
1285
1286 /* mailbox6 */
1287 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1288         .name           = "mailbox6",
1289         .class          = &dra7xx_mailbox_hwmod_class,
1290         .clkdm_name     = "l4cfg_clkdm",
1291         .prcm = {
1292                 .omap4 = {
1293                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1294                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1295                 },
1296         },
1297 };
1298
1299 /* mailbox7 */
1300 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1301         .name           = "mailbox7",
1302         .class          = &dra7xx_mailbox_hwmod_class,
1303         .clkdm_name     = "l4cfg_clkdm",
1304         .prcm = {
1305                 .omap4 = {
1306                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1307                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1308                 },
1309         },
1310 };
1311
1312 /* mailbox8 */
1313 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1314         .name           = "mailbox8",
1315         .class          = &dra7xx_mailbox_hwmod_class,
1316         .clkdm_name     = "l4cfg_clkdm",
1317         .prcm = {
1318                 .omap4 = {
1319                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1320                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1321                 },
1322         },
1323 };
1324
1325 /* mailbox9 */
1326 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1327         .name           = "mailbox9",
1328         .class          = &dra7xx_mailbox_hwmod_class,
1329         .clkdm_name     = "l4cfg_clkdm",
1330         .prcm = {
1331                 .omap4 = {
1332                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1333                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1334                 },
1335         },
1336 };
1337
1338 /* mailbox10 */
1339 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1340         .name           = "mailbox10",
1341         .class          = &dra7xx_mailbox_hwmod_class,
1342         .clkdm_name     = "l4cfg_clkdm",
1343         .prcm = {
1344                 .omap4 = {
1345                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1346                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1347                 },
1348         },
1349 };
1350
1351 /* mailbox11 */
1352 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1353         .name           = "mailbox11",
1354         .class          = &dra7xx_mailbox_hwmod_class,
1355         .clkdm_name     = "l4cfg_clkdm",
1356         .prcm = {
1357                 .omap4 = {
1358                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1359                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1360                 },
1361         },
1362 };
1363
1364 /* mailbox12 */
1365 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1366         .name           = "mailbox12",
1367         .class          = &dra7xx_mailbox_hwmod_class,
1368         .clkdm_name     = "l4cfg_clkdm",
1369         .prcm = {
1370                 .omap4 = {
1371                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1372                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1373                 },
1374         },
1375 };
1376
1377 /* mailbox13 */
1378 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1379         .name           = "mailbox13",
1380         .class          = &dra7xx_mailbox_hwmod_class,
1381         .clkdm_name     = "l4cfg_clkdm",
1382         .prcm = {
1383                 .omap4 = {
1384                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1385                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1386                 },
1387         },
1388 };
1389
1390 /*
1391  * 'mcspi' class
1392  *
1393  */
1394
1395 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1396         .rev_offs       = 0x0000,
1397         .sysc_offs      = 0x0010,
1398         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1399                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1400         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1401                            SIDLE_SMART_WKUP),
1402         .sysc_fields    = &omap_hwmod_sysc_type2,
1403 };
1404
1405 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1406         .name   = "mcspi",
1407         .sysc   = &dra7xx_mcspi_sysc,
1408         .rev    = OMAP4_MCSPI_REV,
1409 };
1410
1411 /* mcspi1 */
1412 /* mcspi1 dev_attr */
1413 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1414         .num_chipselect = 4,
1415 };
1416
1417 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1418         .name           = "mcspi1",
1419         .class          = &dra7xx_mcspi_hwmod_class,
1420         .clkdm_name     = "l4per_clkdm",
1421         .main_clk       = "func_48m_fclk",
1422         .prcm = {
1423                 .omap4 = {
1424                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1425                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1426                         .modulemode   = MODULEMODE_SWCTRL,
1427                 },
1428         },
1429         .dev_attr       = &mcspi1_dev_attr,
1430 };
1431
1432 /* mcspi2 */
1433 /* mcspi2 dev_attr */
1434 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1435         .num_chipselect = 2,
1436 };
1437
1438 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1439         .name           = "mcspi2",
1440         .class          = &dra7xx_mcspi_hwmod_class,
1441         .clkdm_name     = "l4per_clkdm",
1442         .main_clk       = "func_48m_fclk",
1443         .prcm = {
1444                 .omap4 = {
1445                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1446                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1447                         .modulemode   = MODULEMODE_SWCTRL,
1448                 },
1449         },
1450         .dev_attr       = &mcspi2_dev_attr,
1451 };
1452
1453 /* mcspi3 */
1454 /* mcspi3 dev_attr */
1455 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1456         .num_chipselect = 2,
1457 };
1458
1459 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1460         .name           = "mcspi3",
1461         .class          = &dra7xx_mcspi_hwmod_class,
1462         .clkdm_name     = "l4per_clkdm",
1463         .main_clk       = "func_48m_fclk",
1464         .prcm = {
1465                 .omap4 = {
1466                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1467                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1468                         .modulemode   = MODULEMODE_SWCTRL,
1469                 },
1470         },
1471         .dev_attr       = &mcspi3_dev_attr,
1472 };
1473
1474 /* mcspi4 */
1475 /* mcspi4 dev_attr */
1476 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1477         .num_chipselect = 1,
1478 };
1479
1480 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1481         .name           = "mcspi4",
1482         .class          = &dra7xx_mcspi_hwmod_class,
1483         .clkdm_name     = "l4per_clkdm",
1484         .main_clk       = "func_48m_fclk",
1485         .prcm = {
1486                 .omap4 = {
1487                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1488                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1489                         .modulemode   = MODULEMODE_SWCTRL,
1490                 },
1491         },
1492         .dev_attr       = &mcspi4_dev_attr,
1493 };
1494
1495 /*
1496  * 'mcasp' class
1497  *
1498  */
1499 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1500         .sysc_offs      = 0x0004,
1501         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1503         .sysc_fields    = &omap_hwmod_sysc_type3,
1504 };
1505
1506 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1507         .name   = "mcasp",
1508         .sysc   = &dra7xx_mcasp_sysc,
1509 };
1510
1511 /* mcasp1 */
1512 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1513         { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1514         { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1515 };
1516
1517 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1518         .name           = "mcasp1",
1519         .class          = &dra7xx_mcasp_hwmod_class,
1520         .clkdm_name     = "ipu_clkdm",
1521         .main_clk       = "mcasp1_aux_gfclk_mux",
1522         .flags          = HWMOD_OPT_CLKS_NEEDED,
1523         .prcm = {
1524                 .omap4 = {
1525                         .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1526                         .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1527                         .modulemode   = MODULEMODE_SWCTRL,
1528                 },
1529         },
1530         .opt_clks       = mcasp1_opt_clks,
1531         .opt_clks_cnt   = ARRAY_SIZE(mcasp1_opt_clks),
1532 };
1533
1534 /* mcasp2 */
1535 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1536         { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1537         { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1538 };
1539
1540 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1541         .name           = "mcasp2",
1542         .class          = &dra7xx_mcasp_hwmod_class,
1543         .clkdm_name     = "l4per2_clkdm",
1544         .main_clk       = "mcasp2_aux_gfclk_mux",
1545         .flags          = HWMOD_OPT_CLKS_NEEDED,
1546         .prcm = {
1547                 .omap4 = {
1548                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1549                         .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1550                         .modulemode   = MODULEMODE_SWCTRL,
1551                 },
1552         },
1553         .opt_clks       = mcasp2_opt_clks,
1554         .opt_clks_cnt   = ARRAY_SIZE(mcasp2_opt_clks),
1555 };
1556
1557 /* mcasp3 */
1558 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1559         { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1560 };
1561
1562 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1563         .name           = "mcasp3",
1564         .class          = &dra7xx_mcasp_hwmod_class,
1565         .clkdm_name     = "l4per2_clkdm",
1566         .main_clk       = "mcasp3_aux_gfclk_mux",
1567         .flags          = HWMOD_OPT_CLKS_NEEDED,
1568         .prcm = {
1569                 .omap4 = {
1570                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1571                         .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1572                         .modulemode   = MODULEMODE_SWCTRL,
1573                 },
1574         },
1575         .opt_clks       = mcasp3_opt_clks,
1576         .opt_clks_cnt   = ARRAY_SIZE(mcasp3_opt_clks),
1577 };
1578
1579 /* mcasp4 */
1580 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1581         { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1582 };
1583
1584 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1585         .name           = "mcasp4",
1586         .class          = &dra7xx_mcasp_hwmod_class,
1587         .clkdm_name     = "l4per2_clkdm",
1588         .main_clk       = "mcasp4_aux_gfclk_mux",
1589         .flags          = HWMOD_OPT_CLKS_NEEDED,
1590         .prcm = {
1591                 .omap4 = {
1592                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1593                         .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1594                         .modulemode   = MODULEMODE_SWCTRL,
1595                 },
1596         },
1597         .opt_clks       = mcasp4_opt_clks,
1598         .opt_clks_cnt   = ARRAY_SIZE(mcasp4_opt_clks),
1599 };
1600
1601 /* mcasp5 */
1602 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1603         { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1604 };
1605
1606 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1607         .name           = "mcasp5",
1608         .class          = &dra7xx_mcasp_hwmod_class,
1609         .clkdm_name     = "l4per2_clkdm",
1610         .main_clk       = "mcasp5_aux_gfclk_mux",
1611         .flags          = HWMOD_OPT_CLKS_NEEDED,
1612         .prcm = {
1613                 .omap4 = {
1614                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1615                         .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1616                         .modulemode   = MODULEMODE_SWCTRL,
1617                 },
1618         },
1619         .opt_clks       = mcasp5_opt_clks,
1620         .opt_clks_cnt   = ARRAY_SIZE(mcasp5_opt_clks),
1621 };
1622
1623 /* mcasp6 */
1624 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1625         { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1626 };
1627
1628 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1629         .name           = "mcasp6",
1630         .class          = &dra7xx_mcasp_hwmod_class,
1631         .clkdm_name     = "l4per2_clkdm",
1632         .main_clk       = "mcasp6_aux_gfclk_mux",
1633         .flags          = HWMOD_OPT_CLKS_NEEDED,
1634         .prcm = {
1635                 .omap4 = {
1636                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1637                         .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1638                         .modulemode   = MODULEMODE_SWCTRL,
1639                 },
1640         },
1641         .opt_clks       = mcasp6_opt_clks,
1642         .opt_clks_cnt   = ARRAY_SIZE(mcasp6_opt_clks),
1643 };
1644
1645 /* mcasp7 */
1646 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1647         { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1648 };
1649
1650 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1651         .name           = "mcasp7",
1652         .class          = &dra7xx_mcasp_hwmod_class,
1653         .clkdm_name     = "l4per2_clkdm",
1654         .main_clk       = "mcasp7_aux_gfclk_mux",
1655         .flags          = HWMOD_OPT_CLKS_NEEDED,
1656         .prcm = {
1657                 .omap4 = {
1658                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1659                         .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1660                         .modulemode   = MODULEMODE_SWCTRL,
1661                 },
1662         },
1663         .opt_clks       = mcasp7_opt_clks,
1664         .opt_clks_cnt   = ARRAY_SIZE(mcasp7_opt_clks),
1665 };
1666
1667 /* mcasp8 */
1668 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1669         { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1670 };
1671
1672 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1673         .name           = "mcasp8",
1674         .class          = &dra7xx_mcasp_hwmod_class,
1675         .clkdm_name     = "l4per2_clkdm",
1676         .main_clk       = "mcasp8_aux_gfclk_mux",
1677         .flags          = HWMOD_OPT_CLKS_NEEDED,
1678         .prcm = {
1679                 .omap4 = {
1680                         .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1681                         .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1682                         .modulemode   = MODULEMODE_SWCTRL,
1683                 },
1684         },
1685         .opt_clks       = mcasp8_opt_clks,
1686         .opt_clks_cnt   = ARRAY_SIZE(mcasp8_opt_clks),
1687 };
1688
1689 /*
1690  * 'mmc' class
1691  *
1692  */
1693
1694 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1695         .rev_offs       = 0x0000,
1696         .sysc_offs      = 0x0010,
1697         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1698                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1699                            SYSC_HAS_SOFTRESET),
1700         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1701                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1702                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1703         .sysc_fields    = &omap_hwmod_sysc_type2,
1704 };
1705
1706 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1707         .name   = "mmc",
1708         .sysc   = &dra7xx_mmc_sysc,
1709 };
1710
1711 /* mmc1 */
1712 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1713         { .role = "clk32k", .clk = "mmc1_clk32k" },
1714 };
1715
1716 /* mmc1 dev_attr */
1717 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1718         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1719 };
1720
1721 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1722         .name           = "mmc1",
1723         .class          = &dra7xx_mmc_hwmod_class,
1724         .clkdm_name     = "l3init_clkdm",
1725         .main_clk       = "mmc1_fclk_div",
1726         .prcm = {
1727                 .omap4 = {
1728                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1729                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1730                         .modulemode   = MODULEMODE_SWCTRL,
1731                 },
1732         },
1733         .opt_clks       = mmc1_opt_clks,
1734         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1735         .dev_attr       = &mmc1_dev_attr,
1736 };
1737
1738 /* mmc2 */
1739 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1740         { .role = "clk32k", .clk = "mmc2_clk32k" },
1741 };
1742
1743 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1744         .name           = "mmc2",
1745         .class          = &dra7xx_mmc_hwmod_class,
1746         .clkdm_name     = "l3init_clkdm",
1747         .main_clk       = "mmc2_fclk_div",
1748         .prcm = {
1749                 .omap4 = {
1750                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1751                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1752                         .modulemode   = MODULEMODE_SWCTRL,
1753                 },
1754         },
1755         .opt_clks       = mmc2_opt_clks,
1756         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1757 };
1758
1759 /* mmc3 */
1760 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1761         { .role = "clk32k", .clk = "mmc3_clk32k" },
1762 };
1763
1764 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1765         .name           = "mmc3",
1766         .class          = &dra7xx_mmc_hwmod_class,
1767         .clkdm_name     = "l4per_clkdm",
1768         .main_clk       = "mmc3_gfclk_div",
1769         .prcm = {
1770                 .omap4 = {
1771                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1772                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1773                         .modulemode   = MODULEMODE_SWCTRL,
1774                 },
1775         },
1776         .opt_clks       = mmc3_opt_clks,
1777         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1778 };
1779
1780 /* mmc4 */
1781 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1782         { .role = "clk32k", .clk = "mmc4_clk32k" },
1783 };
1784
1785 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1786         .name           = "mmc4",
1787         .class          = &dra7xx_mmc_hwmod_class,
1788         .clkdm_name     = "l4per_clkdm",
1789         .main_clk       = "mmc4_gfclk_div",
1790         .prcm = {
1791                 .omap4 = {
1792                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1793                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1794                         .modulemode   = MODULEMODE_SWCTRL,
1795                 },
1796         },
1797         .opt_clks       = mmc4_opt_clks,
1798         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1799 };
1800
1801 /*
1802  * 'mpu' class
1803  *
1804  */
1805
1806 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1807         .name   = "mpu",
1808 };
1809
1810 /* mpu */
1811 static struct omap_hwmod dra7xx_mpu_hwmod = {
1812         .name           = "mpu",
1813         .class          = &dra7xx_mpu_hwmod_class,
1814         .clkdm_name     = "mpu_clkdm",
1815         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1816         .main_clk       = "dpll_mpu_m2_ck",
1817         .prcm = {
1818                 .omap4 = {
1819                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1820                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1821                 },
1822         },
1823 };
1824
1825 /*
1826  * 'ocp2scp' class
1827  *
1828  */
1829
1830 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1831         .rev_offs       = 0x0000,
1832         .sysc_offs      = 0x0010,
1833         .syss_offs      = 0x0014,
1834         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1835                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1836         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1837         .sysc_fields    = &omap_hwmod_sysc_type1,
1838 };
1839
1840 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1841         .name   = "ocp2scp",
1842         .sysc   = &dra7xx_ocp2scp_sysc,
1843 };
1844
1845 /* ocp2scp1 */
1846 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1847         .name           = "ocp2scp1",
1848         .class          = &dra7xx_ocp2scp_hwmod_class,
1849         .clkdm_name     = "l3init_clkdm",
1850         .main_clk       = "l4_root_clk_div",
1851         .prcm = {
1852                 .omap4 = {
1853                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1854                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1855                         .modulemode   = MODULEMODE_HWCTRL,
1856                 },
1857         },
1858 };
1859
1860 /* ocp2scp3 */
1861 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1862         .name           = "ocp2scp3",
1863         .class          = &dra7xx_ocp2scp_hwmod_class,
1864         .clkdm_name     = "l3init_clkdm",
1865         .main_clk       = "l4_root_clk_div",
1866         .prcm = {
1867                 .omap4 = {
1868                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1869                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1870                         .modulemode   = MODULEMODE_HWCTRL,
1871                 },
1872         },
1873 };
1874
1875 /*
1876  * 'PCIE' class
1877  *
1878  */
1879
1880 /*
1881  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1882  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1883  * associated with an IP automatically leaving the driver to handle that
1884  * by itself. This does not work for PCIeSS which needs the reset lines
1885  * deasserted for the driver to start accessing registers.
1886  *
1887  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1888  * lines after asserting them.
1889  */
1890 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1891 {
1892         int i;
1893
1894         for (i = 0; i < oh->rst_lines_cnt; i++) {
1895                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1896                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1897         }
1898
1899         return 0;
1900 }
1901
1902 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1903         .name   = "pcie",
1904         .reset  = dra7xx_pciess_reset,
1905 };
1906
1907 /* pcie1 */
1908 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1909         { .name = "pcie", .rst_shift = 0 },
1910 };
1911
1912 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1913         .name           = "pcie1",
1914         .class          = &dra7xx_pciess_hwmod_class,
1915         .clkdm_name     = "pcie_clkdm",
1916         .rst_lines      = dra7xx_pciess1_resets,
1917         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1918         .main_clk       = "l4_root_clk_div",
1919         .prcm = {
1920                 .omap4 = {
1921                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1922                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1923                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1924                         .modulemode   = MODULEMODE_SWCTRL,
1925                 },
1926         },
1927 };
1928
1929 /* pcie2 */
1930 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1931         { .name = "pcie", .rst_shift = 1 },
1932 };
1933
1934 /* pcie2 */
1935 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1936         .name           = "pcie2",
1937         .class          = &dra7xx_pciess_hwmod_class,
1938         .clkdm_name     = "pcie_clkdm",
1939         .rst_lines      = dra7xx_pciess2_resets,
1940         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1941         .main_clk       = "l4_root_clk_div",
1942         .prcm = {
1943                 .omap4 = {
1944                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1945                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1946                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1947                         .modulemode   = MODULEMODE_SWCTRL,
1948                 },
1949         },
1950 };
1951
1952 /*
1953  * 'qspi' class
1954  *
1955  */
1956
1957 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1958         .sysc_offs      = 0x0010,
1959         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1960         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1961                            SIDLE_SMART_WKUP),
1962         .sysc_fields    = &omap_hwmod_sysc_type2,
1963 };
1964
1965 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1966         .name   = "qspi",
1967         .sysc   = &dra7xx_qspi_sysc,
1968 };
1969
1970 /* qspi */
1971 static struct omap_hwmod dra7xx_qspi_hwmod = {
1972         .name           = "qspi",
1973         .class          = &dra7xx_qspi_hwmod_class,
1974         .clkdm_name     = "l4per2_clkdm",
1975         .main_clk       = "qspi_gfclk_div",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1979                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983 };
1984
1985 /*
1986  * 'rtcss' class
1987  *
1988  */
1989 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1990         .sysc_offs      = 0x0078,
1991         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1992         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1993                            SIDLE_SMART_WKUP),
1994         .sysc_fields    = &omap_hwmod_sysc_type3,
1995 };
1996
1997 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1998         .name   = "rtcss",
1999         .sysc   = &dra7xx_rtcss_sysc,
2000         .unlock = &omap_hwmod_rtc_unlock,
2001         .lock   = &omap_hwmod_rtc_lock,
2002 };
2003
2004 /* rtcss */
2005 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2006         .name           = "rtcss",
2007         .class          = &dra7xx_rtcss_hwmod_class,
2008         .clkdm_name     = "rtc_clkdm",
2009         .main_clk       = "sys_32k_ck",
2010         .prcm = {
2011                 .omap4 = {
2012                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2013                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2014                         .modulemode   = MODULEMODE_SWCTRL,
2015                 },
2016         },
2017 };
2018
2019 /*
2020  * 'sata' class
2021  *
2022  */
2023
2024 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2025         .sysc_offs      = 0x0000,
2026         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2028                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2029                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2030         .sysc_fields    = &omap_hwmod_sysc_type2,
2031 };
2032
2033 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2034         .name   = "sata",
2035         .sysc   = &dra7xx_sata_sysc,
2036 };
2037
2038 /* sata */
2039
2040 static struct omap_hwmod dra7xx_sata_hwmod = {
2041         .name           = "sata",
2042         .class          = &dra7xx_sata_hwmod_class,
2043         .clkdm_name     = "l3init_clkdm",
2044         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2045         .main_clk       = "func_48m_fclk",
2046         .mpu_rt_idx     = 1,
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2050                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_SWCTRL,
2052                 },
2053         },
2054 };
2055
2056 /*
2057  * 'smartreflex' class
2058  *
2059  */
2060
2061 /* The IP is not compliant to type1 / type2 scheme */
2062 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2063         .sidle_shift    = 24,
2064         .enwkup_shift   = 26,
2065 };
2066
2067 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2068         .sysc_offs      = 0x0038,
2069         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2070         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2071                            SIDLE_SMART_WKUP),
2072         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2073 };
2074
2075 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2076         .name   = "smartreflex",
2077         .sysc   = &dra7xx_smartreflex_sysc,
2078         .rev    = 2,
2079 };
2080
2081 /* smartreflex_core */
2082 /* smartreflex_core dev_attr */
2083 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2084         .sensor_voltdm_name     = "core",
2085 };
2086
2087 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2088         .name           = "smartreflex_core",
2089         .class          = &dra7xx_smartreflex_hwmod_class,
2090         .clkdm_name     = "coreaon_clkdm",
2091         .main_clk       = "wkupaon_iclk_mux",
2092         .prcm = {
2093                 .omap4 = {
2094                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2095                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2096                         .modulemode   = MODULEMODE_SWCTRL,
2097                 },
2098         },
2099         .dev_attr       = &smartreflex_core_dev_attr,
2100 };
2101
2102 /* smartreflex_mpu */
2103 /* smartreflex_mpu dev_attr */
2104 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2105         .sensor_voltdm_name     = "mpu",
2106 };
2107
2108 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2109         .name           = "smartreflex_mpu",
2110         .class          = &dra7xx_smartreflex_hwmod_class,
2111         .clkdm_name     = "coreaon_clkdm",
2112         .main_clk       = "wkupaon_iclk_mux",
2113         .prcm = {
2114                 .omap4 = {
2115                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2116                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2117                         .modulemode   = MODULEMODE_SWCTRL,
2118                 },
2119         },
2120         .dev_attr       = &smartreflex_mpu_dev_attr,
2121 };
2122
2123 /*
2124  * 'spinlock' class
2125  *
2126  */
2127
2128 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2129         .rev_offs       = 0x0000,
2130         .sysc_offs      = 0x0010,
2131         .syss_offs      = 0x0014,
2132         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2133                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2134                            SYSS_HAS_RESET_STATUS),
2135         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2136         .sysc_fields    = &omap_hwmod_sysc_type1,
2137 };
2138
2139 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2140         .name   = "spinlock",
2141         .sysc   = &dra7xx_spinlock_sysc,
2142 };
2143
2144 /* spinlock */
2145 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2146         .name           = "spinlock",
2147         .class          = &dra7xx_spinlock_hwmod_class,
2148         .clkdm_name     = "l4cfg_clkdm",
2149         .main_clk       = "l3_iclk_div",
2150         .prcm = {
2151                 .omap4 = {
2152                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2153                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2154                 },
2155         },
2156 };
2157
2158 /*
2159  * 'timer' class
2160  *
2161  * This class contains several variants: ['timer_1ms', 'timer_secure',
2162  * 'timer']
2163  */
2164
2165 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2166         .rev_offs       = 0x0000,
2167         .sysc_offs      = 0x0010,
2168         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2169                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2170         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2171                            SIDLE_SMART_WKUP),
2172         .sysc_fields    = &omap_hwmod_sysc_type2,
2173 };
2174
2175 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2176         .name   = "timer",
2177         .sysc   = &dra7xx_timer_1ms_sysc,
2178 };
2179
2180 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2181         .rev_offs       = 0x0000,
2182         .sysc_offs      = 0x0010,
2183         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2184                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2185         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2186                            SIDLE_SMART_WKUP),
2187         .sysc_fields    = &omap_hwmod_sysc_type2,
2188 };
2189
2190 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2191         .name   = "timer",
2192         .sysc   = &dra7xx_timer_sysc,
2193 };
2194
2195 /* timer1 */
2196 static struct omap_hwmod dra7xx_timer1_hwmod = {
2197         .name           = "timer1",
2198         .class          = &dra7xx_timer_1ms_hwmod_class,
2199         .clkdm_name     = "wkupaon_clkdm",
2200         .main_clk       = "timer1_gfclk_mux",
2201         .prcm = {
2202                 .omap4 = {
2203                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2204                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2205                         .modulemode   = MODULEMODE_SWCTRL,
2206                 },
2207         },
2208 };
2209
2210 /* timer2 */
2211 static struct omap_hwmod dra7xx_timer2_hwmod = {
2212         .name           = "timer2",
2213         .class          = &dra7xx_timer_1ms_hwmod_class,
2214         .clkdm_name     = "l4per_clkdm",
2215         .main_clk       = "timer2_gfclk_mux",
2216         .prcm = {
2217                 .omap4 = {
2218                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2219                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2220                         .modulemode   = MODULEMODE_SWCTRL,
2221                 },
2222         },
2223 };
2224
2225 /* timer3 */
2226 static struct omap_hwmod dra7xx_timer3_hwmod = {
2227         .name           = "timer3",
2228         .class          = &dra7xx_timer_hwmod_class,
2229         .clkdm_name     = "l4per_clkdm",
2230         .main_clk       = "timer3_gfclk_mux",
2231         .prcm = {
2232                 .omap4 = {
2233                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2234                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2235                         .modulemode   = MODULEMODE_SWCTRL,
2236                 },
2237         },
2238 };
2239
2240 /* timer4 */
2241 static struct omap_hwmod dra7xx_timer4_hwmod = {
2242         .name           = "timer4",
2243         .class          = &dra7xx_timer_hwmod_class,
2244         .clkdm_name     = "l4per_clkdm",
2245         .main_clk       = "timer4_gfclk_mux",
2246         .prcm = {
2247                 .omap4 = {
2248                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2249                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2250                         .modulemode   = MODULEMODE_SWCTRL,
2251                 },
2252         },
2253 };
2254
2255 /* timer5 */
2256 static struct omap_hwmod dra7xx_timer5_hwmod = {
2257         .name           = "timer5",
2258         .class          = &dra7xx_timer_hwmod_class,
2259         .clkdm_name     = "ipu_clkdm",
2260         .main_clk       = "timer5_gfclk_mux",
2261         .prcm = {
2262                 .omap4 = {
2263                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2264                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2265                         .modulemode   = MODULEMODE_SWCTRL,
2266                 },
2267         },
2268 };
2269
2270 /* timer6 */
2271 static struct omap_hwmod dra7xx_timer6_hwmod = {
2272         .name           = "timer6",
2273         .class          = &dra7xx_timer_hwmod_class,
2274         .clkdm_name     = "ipu_clkdm",
2275         .main_clk       = "timer6_gfclk_mux",
2276         .prcm = {
2277                 .omap4 = {
2278                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2279                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2280                         .modulemode   = MODULEMODE_SWCTRL,
2281                 },
2282         },
2283 };
2284
2285 /* timer7 */
2286 static struct omap_hwmod dra7xx_timer7_hwmod = {
2287         .name           = "timer7",
2288         .class          = &dra7xx_timer_hwmod_class,
2289         .clkdm_name     = "ipu_clkdm",
2290         .main_clk       = "timer7_gfclk_mux",
2291         .prcm = {
2292                 .omap4 = {
2293                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2294                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2295                         .modulemode   = MODULEMODE_SWCTRL,
2296                 },
2297         },
2298 };
2299
2300 /* timer8 */
2301 static struct omap_hwmod dra7xx_timer8_hwmod = {
2302         .name           = "timer8",
2303         .class          = &dra7xx_timer_hwmod_class,
2304         .clkdm_name     = "ipu_clkdm",
2305         .main_clk       = "timer8_gfclk_mux",
2306         .prcm = {
2307                 .omap4 = {
2308                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2309                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2310                         .modulemode   = MODULEMODE_SWCTRL,
2311                 },
2312         },
2313 };
2314
2315 /* timer9 */
2316 static struct omap_hwmod dra7xx_timer9_hwmod = {
2317         .name           = "timer9",
2318         .class          = &dra7xx_timer_hwmod_class,
2319         .clkdm_name     = "l4per_clkdm",
2320         .main_clk       = "timer9_gfclk_mux",
2321         .prcm = {
2322                 .omap4 = {
2323                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2324                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2325                         .modulemode   = MODULEMODE_SWCTRL,
2326                 },
2327         },
2328 };
2329
2330 /* timer10 */
2331 static struct omap_hwmod dra7xx_timer10_hwmod = {
2332         .name           = "timer10",
2333         .class          = &dra7xx_timer_1ms_hwmod_class,
2334         .clkdm_name     = "l4per_clkdm",
2335         .main_clk       = "timer10_gfclk_mux",
2336         .prcm = {
2337                 .omap4 = {
2338                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2339                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2340                         .modulemode   = MODULEMODE_SWCTRL,
2341                 },
2342         },
2343 };
2344
2345 /* timer11 */
2346 static struct omap_hwmod dra7xx_timer11_hwmod = {
2347         .name           = "timer11",
2348         .class          = &dra7xx_timer_hwmod_class,
2349         .clkdm_name     = "l4per_clkdm",
2350         .main_clk       = "timer11_gfclk_mux",
2351         .prcm = {
2352                 .omap4 = {
2353                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2354                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2355                         .modulemode   = MODULEMODE_SWCTRL,
2356                 },
2357         },
2358 };
2359
2360 /* timer12 */
2361 static struct omap_hwmod dra7xx_timer12_hwmod = {
2362         .name           = "timer12",
2363         .class          = &dra7xx_timer_hwmod_class,
2364         .clkdm_name     = "wkupaon_clkdm",
2365         .main_clk       = "secure_32k_clk_src_ck",
2366         .prcm = {
2367                 .omap4 = {
2368                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2369                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2370                 },
2371         },
2372 };
2373
2374 /* timer13 */
2375 static struct omap_hwmod dra7xx_timer13_hwmod = {
2376         .name           = "timer13",
2377         .class          = &dra7xx_timer_hwmod_class,
2378         .clkdm_name     = "l4per3_clkdm",
2379         .main_clk       = "timer13_gfclk_mux",
2380         .prcm = {
2381                 .omap4 = {
2382                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2383                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2384                         .modulemode   = MODULEMODE_SWCTRL,
2385                 },
2386         },
2387 };
2388
2389 /* timer14 */
2390 static struct omap_hwmod dra7xx_timer14_hwmod = {
2391         .name           = "timer14",
2392         .class          = &dra7xx_timer_hwmod_class,
2393         .clkdm_name     = "l4per3_clkdm",
2394         .main_clk       = "timer14_gfclk_mux",
2395         .prcm = {
2396                 .omap4 = {
2397                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2398                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2399                         .modulemode   = MODULEMODE_SWCTRL,
2400                 },
2401         },
2402 };
2403
2404 /* timer15 */
2405 static struct omap_hwmod dra7xx_timer15_hwmod = {
2406         .name           = "timer15",
2407         .class          = &dra7xx_timer_hwmod_class,
2408         .clkdm_name     = "l4per3_clkdm",
2409         .main_clk       = "timer15_gfclk_mux",
2410         .prcm = {
2411                 .omap4 = {
2412                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2413                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2414                         .modulemode   = MODULEMODE_SWCTRL,
2415                 },
2416         },
2417 };
2418
2419 /* timer16 */
2420 static struct omap_hwmod dra7xx_timer16_hwmod = {
2421         .name           = "timer16",
2422         .class          = &dra7xx_timer_hwmod_class,
2423         .clkdm_name     = "l4per3_clkdm",
2424         .main_clk       = "timer16_gfclk_mux",
2425         .prcm = {
2426                 .omap4 = {
2427                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2428                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2429                         .modulemode   = MODULEMODE_SWCTRL,
2430                 },
2431         },
2432 };
2433
2434 /*
2435  * 'uart' class
2436  *
2437  */
2438
2439 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2440         .rev_offs       = 0x0050,
2441         .sysc_offs      = 0x0054,
2442         .syss_offs      = 0x0058,
2443         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2444                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2445                            SYSS_HAS_RESET_STATUS),
2446         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2447                            SIDLE_SMART_WKUP),
2448         .sysc_fields    = &omap_hwmod_sysc_type1,
2449 };
2450
2451 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2452         .name   = "uart",
2453         .sysc   = &dra7xx_uart_sysc,
2454 };
2455
2456 /* uart1 */
2457 static struct omap_hwmod dra7xx_uart1_hwmod = {
2458         .name           = "uart1",
2459         .class          = &dra7xx_uart_hwmod_class,
2460         .clkdm_name     = "l4per_clkdm",
2461         .main_clk       = "uart1_gfclk_mux",
2462         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2463         .prcm = {
2464                 .omap4 = {
2465                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2466                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2467                         .modulemode   = MODULEMODE_SWCTRL,
2468                 },
2469         },
2470 };
2471
2472 /* uart2 */
2473 static struct omap_hwmod dra7xx_uart2_hwmod = {
2474         .name           = "uart2",
2475         .class          = &dra7xx_uart_hwmod_class,
2476         .clkdm_name     = "l4per_clkdm",
2477         .main_clk       = "uart2_gfclk_mux",
2478         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2479         .prcm = {
2480                 .omap4 = {
2481                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2482                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2483                         .modulemode   = MODULEMODE_SWCTRL,
2484                 },
2485         },
2486 };
2487
2488 /* uart3 */
2489 static struct omap_hwmod dra7xx_uart3_hwmod = {
2490         .name           = "uart3",
2491         .class          = &dra7xx_uart_hwmod_class,
2492         .clkdm_name     = "l4per_clkdm",
2493         .main_clk       = "uart3_gfclk_mux",
2494         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2495         .prcm = {
2496                 .omap4 = {
2497                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2498                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2499                         .modulemode   = MODULEMODE_SWCTRL,
2500                 },
2501         },
2502 };
2503
2504 /* uart4 */
2505 static struct omap_hwmod dra7xx_uart4_hwmod = {
2506         .name           = "uart4",
2507         .class          = &dra7xx_uart_hwmod_class,
2508         .clkdm_name     = "l4per_clkdm",
2509         .main_clk       = "uart4_gfclk_mux",
2510         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2511         .prcm = {
2512                 .omap4 = {
2513                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2514                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2515                         .modulemode   = MODULEMODE_SWCTRL,
2516                 },
2517         },
2518 };
2519
2520 /* uart5 */
2521 static struct omap_hwmod dra7xx_uart5_hwmod = {
2522         .name           = "uart5",
2523         .class          = &dra7xx_uart_hwmod_class,
2524         .clkdm_name     = "l4per_clkdm",
2525         .main_clk       = "uart5_gfclk_mux",
2526         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2527         .prcm = {
2528                 .omap4 = {
2529                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2530                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2531                         .modulemode   = MODULEMODE_SWCTRL,
2532                 },
2533         },
2534 };
2535
2536 /* uart6 */
2537 static struct omap_hwmod dra7xx_uart6_hwmod = {
2538         .name           = "uart6",
2539         .class          = &dra7xx_uart_hwmod_class,
2540         .clkdm_name     = "ipu_clkdm",
2541         .main_clk       = "uart6_gfclk_mux",
2542         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2543         .prcm = {
2544                 .omap4 = {
2545                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2546                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2547                         .modulemode   = MODULEMODE_SWCTRL,
2548                 },
2549         },
2550 };
2551
2552 /* uart7 */
2553 static struct omap_hwmod dra7xx_uart7_hwmod = {
2554         .name           = "uart7",
2555         .class          = &dra7xx_uart_hwmod_class,
2556         .clkdm_name     = "l4per2_clkdm",
2557         .main_clk       = "uart7_gfclk_mux",
2558         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2559         .prcm = {
2560                 .omap4 = {
2561                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2562                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2563                         .modulemode   = MODULEMODE_SWCTRL,
2564                 },
2565         },
2566 };
2567
2568 /* uart8 */
2569 static struct omap_hwmod dra7xx_uart8_hwmod = {
2570         .name           = "uart8",
2571         .class          = &dra7xx_uart_hwmod_class,
2572         .clkdm_name     = "l4per2_clkdm",
2573         .main_clk       = "uart8_gfclk_mux",
2574         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2575         .prcm = {
2576                 .omap4 = {
2577                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2578                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2579                         .modulemode   = MODULEMODE_SWCTRL,
2580                 },
2581         },
2582 };
2583
2584 /* uart9 */
2585 static struct omap_hwmod dra7xx_uart9_hwmod = {
2586         .name           = "uart9",
2587         .class          = &dra7xx_uart_hwmod_class,
2588         .clkdm_name     = "l4per2_clkdm",
2589         .main_clk       = "uart9_gfclk_mux",
2590         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2591         .prcm = {
2592                 .omap4 = {
2593                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2594                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2595                         .modulemode   = MODULEMODE_SWCTRL,
2596                 },
2597         },
2598 };
2599
2600 /* uart10 */
2601 static struct omap_hwmod dra7xx_uart10_hwmod = {
2602         .name           = "uart10",
2603         .class          = &dra7xx_uart_hwmod_class,
2604         .clkdm_name     = "wkupaon_clkdm",
2605         .main_clk       = "uart10_gfclk_mux",
2606         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2607         .prcm = {
2608                 .omap4 = {
2609                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2610                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2611                         .modulemode   = MODULEMODE_SWCTRL,
2612                 },
2613         },
2614 };
2615
2616 /* DES (the 'P' (public) device) */
2617 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2618         .rev_offs       = 0x0030,
2619         .sysc_offs      = 0x0034,
2620         .syss_offs      = 0x0038,
2621         .sysc_flags     = SYSS_HAS_RESET_STATUS,
2622 };
2623
2624 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2625         .name   = "des",
2626         .sysc   = &dra7xx_des_sysc,
2627 };
2628
2629 /* DES */
2630 static struct omap_hwmod dra7xx_des_hwmod = {
2631         .name           = "des",
2632         .class          = &dra7xx_des_hwmod_class,
2633         .clkdm_name     = "l4sec_clkdm",
2634         .main_clk       = "l3_iclk_div",
2635         .prcm = {
2636                 .omap4 = {
2637                         .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2638                         .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2639                         .modulemode   = MODULEMODE_HWCTRL,
2640                 },
2641         },
2642 };
2643
2644 /* rng */
2645 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2646         .rev_offs       = 0x1fe0,
2647         .sysc_offs      = 0x1fe4,
2648         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2649         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
2650         .sysc_fields    = &omap_hwmod_sysc_type1,
2651 };
2652
2653 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2654         .name           = "rng",
2655         .sysc           = &dra7xx_rng_sysc,
2656 };
2657
2658 static struct omap_hwmod dra7xx_rng_hwmod = {
2659         .name           = "rng",
2660         .class          = &dra7xx_rng_hwmod_class,
2661         .flags          = HWMOD_SWSUP_SIDLE,
2662         .clkdm_name     = "l4sec_clkdm",
2663         .prcm = {
2664                 .omap4 = {
2665                         .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2666                         .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2667                         .modulemode   = MODULEMODE_HWCTRL,
2668                 },
2669         },
2670 };
2671
2672 /*
2673  * 'usb_otg_ss' class
2674  *
2675  */
2676
2677 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2678         .rev_offs       = 0x0000,
2679         .sysc_offs      = 0x0010,
2680         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2681                            SYSC_HAS_SIDLEMODE),
2682         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2683                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2684                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2685         .sysc_fields    = &omap_hwmod_sysc_type2,
2686 };
2687
2688 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2689         .name   = "usb_otg_ss",
2690         .sysc   = &dra7xx_usb_otg_ss_sysc,
2691 };
2692
2693 /* usb_otg_ss1 */
2694 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2695         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2696 };
2697
2698 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2699         .name           = "usb_otg_ss1",
2700         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2701         .clkdm_name     = "l3init_clkdm",
2702         .main_clk       = "dpll_core_h13x2_ck",
2703         .prcm = {
2704                 .omap4 = {
2705                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2706                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2707                         .modulemode   = MODULEMODE_HWCTRL,
2708                 },
2709         },
2710         .opt_clks       = usb_otg_ss1_opt_clks,
2711         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2712 };
2713
2714 /* usb_otg_ss2 */
2715 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2716         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2717 };
2718
2719 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2720         .name           = "usb_otg_ss2",
2721         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2722         .clkdm_name     = "l3init_clkdm",
2723         .main_clk       = "dpll_core_h13x2_ck",
2724         .prcm = {
2725                 .omap4 = {
2726                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2727                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2728                         .modulemode   = MODULEMODE_HWCTRL,
2729                 },
2730         },
2731         .opt_clks       = usb_otg_ss2_opt_clks,
2732         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2733 };
2734
2735 /* usb_otg_ss3 */
2736 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2737         .name           = "usb_otg_ss3",
2738         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2739         .clkdm_name     = "l3init_clkdm",
2740         .main_clk       = "dpll_core_h13x2_ck",
2741         .prcm = {
2742                 .omap4 = {
2743                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2744                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2745                         .modulemode   = MODULEMODE_HWCTRL,
2746                 },
2747         },
2748 };
2749
2750 /* usb_otg_ss4 */
2751 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2752         .name           = "usb_otg_ss4",
2753         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2754         .clkdm_name     = "l3init_clkdm",
2755         .main_clk       = "dpll_core_h13x2_ck",
2756         .prcm = {
2757                 .omap4 = {
2758                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2759                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2760                         .modulemode   = MODULEMODE_HWCTRL,
2761                 },
2762         },
2763 };
2764
2765 /*
2766  * 'vcp' class
2767  *
2768  */
2769
2770 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2771         .name   = "vcp",
2772 };
2773
2774 /* vcp1 */
2775 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2776         .name           = "vcp1",
2777         .class          = &dra7xx_vcp_hwmod_class,
2778         .clkdm_name     = "l3main1_clkdm",
2779         .main_clk       = "l3_iclk_div",
2780         .prcm = {
2781                 .omap4 = {
2782                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2783                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2784                 },
2785         },
2786 };
2787
2788 /* vcp2 */
2789 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2790         .name           = "vcp2",
2791         .class          = &dra7xx_vcp_hwmod_class,
2792         .clkdm_name     = "l3main1_clkdm",
2793         .main_clk       = "l3_iclk_div",
2794         .prcm = {
2795                 .omap4 = {
2796                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2797                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2798                 },
2799         },
2800 };
2801
2802 /*
2803  * 'wd_timer' class
2804  *
2805  */
2806
2807 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2808         .rev_offs       = 0x0000,
2809         .sysc_offs      = 0x0010,
2810         .syss_offs      = 0x0014,
2811         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2812                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2814                            SIDLE_SMART_WKUP),
2815         .sysc_fields    = &omap_hwmod_sysc_type1,
2816 };
2817
2818 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2819         .name           = "wd_timer",
2820         .sysc           = &dra7xx_wd_timer_sysc,
2821         .pre_shutdown   = &omap2_wd_timer_disable,
2822         .reset          = &omap2_wd_timer_reset,
2823 };
2824
2825 /* wd_timer2 */
2826 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2827         .name           = "wd_timer2",
2828         .class          = &dra7xx_wd_timer_hwmod_class,
2829         .clkdm_name     = "wkupaon_clkdm",
2830         .main_clk       = "sys_32k_ck",
2831         .prcm = {
2832                 .omap4 = {
2833                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2834                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2835                         .modulemode   = MODULEMODE_SWCTRL,
2836                 },
2837         },
2838 };
2839
2840
2841 /*
2842  * Interfaces
2843  */
2844
2845 /* l3_main_1 -> dmm */
2846 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2847         .master         = &dra7xx_l3_main_1_hwmod,
2848         .slave          = &dra7xx_dmm_hwmod,
2849         .clk            = "l3_iclk_div",
2850         .user           = OCP_USER_SDMA,
2851 };
2852
2853 /* l3_main_2 -> l3_instr */
2854 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2855         .master         = &dra7xx_l3_main_2_hwmod,
2856         .slave          = &dra7xx_l3_instr_hwmod,
2857         .clk            = "l3_iclk_div",
2858         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2859 };
2860
2861 /* l4_cfg -> l3_main_1 */
2862 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2863         .master         = &dra7xx_l4_cfg_hwmod,
2864         .slave          = &dra7xx_l3_main_1_hwmod,
2865         .clk            = "l3_iclk_div",
2866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2867 };
2868
2869 /* mpu -> l3_main_1 */
2870 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2871         .master         = &dra7xx_mpu_hwmod,
2872         .slave          = &dra7xx_l3_main_1_hwmod,
2873         .clk            = "l3_iclk_div",
2874         .user           = OCP_USER_MPU,
2875 };
2876
2877 /* l3_main_1 -> l3_main_2 */
2878 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2879         .master         = &dra7xx_l3_main_1_hwmod,
2880         .slave          = &dra7xx_l3_main_2_hwmod,
2881         .clk            = "l3_iclk_div",
2882         .user           = OCP_USER_MPU,
2883 };
2884
2885 /* l4_cfg -> l3_main_2 */
2886 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2887         .master         = &dra7xx_l4_cfg_hwmod,
2888         .slave          = &dra7xx_l3_main_2_hwmod,
2889         .clk            = "l3_iclk_div",
2890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2891 };
2892
2893 /* l3_main_1 -> l4_cfg */
2894 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2895         .master         = &dra7xx_l3_main_1_hwmod,
2896         .slave          = &dra7xx_l4_cfg_hwmod,
2897         .clk            = "l3_iclk_div",
2898         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2899 };
2900
2901 /* l3_main_1 -> l4_per1 */
2902 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2903         .master         = &dra7xx_l3_main_1_hwmod,
2904         .slave          = &dra7xx_l4_per1_hwmod,
2905         .clk            = "l3_iclk_div",
2906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2907 };
2908
2909 /* l3_main_1 -> l4_per2 */
2910 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2911         .master         = &dra7xx_l3_main_1_hwmod,
2912         .slave          = &dra7xx_l4_per2_hwmod,
2913         .clk            = "l3_iclk_div",
2914         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2915 };
2916
2917 /* l3_main_1 -> l4_per3 */
2918 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2919         .master         = &dra7xx_l3_main_1_hwmod,
2920         .slave          = &dra7xx_l4_per3_hwmod,
2921         .clk            = "l3_iclk_div",
2922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2923 };
2924
2925 /* l3_main_1 -> l4_wkup */
2926 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2927         .master         = &dra7xx_l3_main_1_hwmod,
2928         .slave          = &dra7xx_l4_wkup_hwmod,
2929         .clk            = "wkupaon_iclk_mux",
2930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2931 };
2932
2933 /* l4_per2 -> atl */
2934 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2935         .master         = &dra7xx_l4_per2_hwmod,
2936         .slave          = &dra7xx_atl_hwmod,
2937         .clk            = "l3_iclk_div",
2938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2939 };
2940
2941 /* l3_main_1 -> bb2d */
2942 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2943         .master         = &dra7xx_l3_main_1_hwmod,
2944         .slave          = &dra7xx_bb2d_hwmod,
2945         .clk            = "l3_iclk_div",
2946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2947 };
2948
2949 /* l4_wkup -> counter_32k */
2950 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2951         .master         = &dra7xx_l4_wkup_hwmod,
2952         .slave          = &dra7xx_counter_32k_hwmod,
2953         .clk            = "wkupaon_iclk_mux",
2954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2955 };
2956
2957 /* l4_wkup -> ctrl_module_wkup */
2958 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2959         .master         = &dra7xx_l4_wkup_hwmod,
2960         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2961         .clk            = "wkupaon_iclk_mux",
2962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2963 };
2964
2965 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2966         .master         = &dra7xx_l4_per2_hwmod,
2967         .slave          = &dra7xx_gmac_hwmod,
2968         .clk            = "dpll_gmac_ck",
2969         .user           = OCP_USER_MPU,
2970 };
2971
2972 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2973         .master         = &dra7xx_gmac_hwmod,
2974         .slave          = &dra7xx_mdio_hwmod,
2975         .user           = OCP_USER_MPU,
2976 };
2977
2978 /* l4_wkup -> dcan1 */
2979 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2980         .master         = &dra7xx_l4_wkup_hwmod,
2981         .slave          = &dra7xx_dcan1_hwmod,
2982         .clk            = "wkupaon_iclk_mux",
2983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2984 };
2985
2986 /* l4_per2 -> dcan2 */
2987 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2988         .master         = &dra7xx_l4_per2_hwmod,
2989         .slave          = &dra7xx_dcan2_hwmod,
2990         .clk            = "l3_iclk_div",
2991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2992 };
2993
2994 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2995         {
2996                 .pa_start       = 0x4a056000,
2997                 .pa_end         = 0x4a056fff,
2998                 .flags          = ADDR_TYPE_RT
2999         },
3000         { }
3001 };
3002
3003 /* l4_cfg -> dma_system */
3004 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
3005         .master         = &dra7xx_l4_cfg_hwmod,
3006         .slave          = &dra7xx_dma_system_hwmod,
3007         .clk            = "l3_iclk_div",
3008         .addr           = dra7xx_dma_system_addrs,
3009         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3010 };
3011
3012 /* l3_main_1 -> tpcc */
3013 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
3014         .master         = &dra7xx_l3_main_1_hwmod,
3015         .slave          = &dra7xx_tpcc_hwmod,
3016         .clk            = "l3_iclk_div",
3017         .user           = OCP_USER_MPU,
3018 };
3019
3020 /* l3_main_1 -> tptc0 */
3021 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
3022         .master         = &dra7xx_l3_main_1_hwmod,
3023         .slave          = &dra7xx_tptc0_hwmod,
3024         .clk            = "l3_iclk_div",
3025         .user           = OCP_USER_MPU,
3026 };
3027
3028 /* l3_main_1 -> tptc1 */
3029 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
3030         .master         = &dra7xx_l3_main_1_hwmod,
3031         .slave          = &dra7xx_tptc1_hwmod,
3032         .clk            = "l3_iclk_div",
3033         .user           = OCP_USER_MPU,
3034 };
3035
3036 /* l3_main_1 -> dss */
3037 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3038         .master         = &dra7xx_l3_main_1_hwmod,
3039         .slave          = &dra7xx_dss_hwmod,
3040         .clk            = "l3_iclk_div",
3041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3042 };
3043
3044 /* l3_main_1 -> dispc */
3045 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3046         .master         = &dra7xx_l3_main_1_hwmod,
3047         .slave          = &dra7xx_dss_dispc_hwmod,
3048         .clk            = "l3_iclk_div",
3049         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3050 };
3051
3052 /* l3_main_1 -> dispc */
3053 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3054         .master         = &dra7xx_l3_main_1_hwmod,
3055         .slave          = &dra7xx_dss_hdmi_hwmod,
3056         .clk            = "l3_iclk_div",
3057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3058 };
3059
3060 /* l3_main_1 -> aes1 */
3061 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3062         .master         = &dra7xx_l3_main_1_hwmod,
3063         .slave          = &dra7xx_aes1_hwmod,
3064         .clk            = "l3_iclk_div",
3065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3066 };
3067
3068 /* l3_main_1 -> aes2 */
3069 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3070         .master         = &dra7xx_l3_main_1_hwmod,
3071         .slave          = &dra7xx_aes2_hwmod,
3072         .clk            = "l3_iclk_div",
3073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3074 };
3075
3076 /* l3_main_1 -> sha0 */
3077 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3078         .master         = &dra7xx_l3_main_1_hwmod,
3079         .slave          = &dra7xx_sha0_hwmod,
3080         .clk            = "l3_iclk_div",
3081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3082 };
3083
3084 /* l4_per2 -> mcasp1 */
3085 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3086         .master         = &dra7xx_l4_per2_hwmod,
3087         .slave          = &dra7xx_mcasp1_hwmod,
3088         .clk            = "l4_root_clk_div",
3089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3090 };
3091
3092 /* l3_main_1 -> mcasp1 */
3093 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3094         .master         = &dra7xx_l3_main_1_hwmod,
3095         .slave          = &dra7xx_mcasp1_hwmod,
3096         .clk            = "l3_iclk_div",
3097         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3098 };
3099
3100 /* l4_per2 -> mcasp2 */
3101 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3102         .master         = &dra7xx_l4_per2_hwmod,
3103         .slave          = &dra7xx_mcasp2_hwmod,
3104         .clk            = "l4_root_clk_div",
3105         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3106 };
3107
3108 /* l3_main_1 -> mcasp2 */
3109 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3110         .master         = &dra7xx_l3_main_1_hwmod,
3111         .slave          = &dra7xx_mcasp2_hwmod,
3112         .clk            = "l3_iclk_div",
3113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3114 };
3115
3116 /* l4_per2 -> mcasp3 */
3117 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3118         .master         = &dra7xx_l4_per2_hwmod,
3119         .slave          = &dra7xx_mcasp3_hwmod,
3120         .clk            = "l4_root_clk_div",
3121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3122 };
3123
3124 /* l3_main_1 -> mcasp3 */
3125 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3126         .master         = &dra7xx_l3_main_1_hwmod,
3127         .slave          = &dra7xx_mcasp3_hwmod,
3128         .clk            = "l3_iclk_div",
3129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3130 };
3131
3132 /* l4_per2 -> mcasp4 */
3133 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3134         .master         = &dra7xx_l4_per2_hwmod,
3135         .slave          = &dra7xx_mcasp4_hwmod,
3136         .clk            = "l4_root_clk_div",
3137         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3138 };
3139
3140 /* l4_per2 -> mcasp5 */
3141 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3142         .master         = &dra7xx_l4_per2_hwmod,
3143         .slave          = &dra7xx_mcasp5_hwmod,
3144         .clk            = "l4_root_clk_div",
3145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3146 };
3147
3148 /* l4_per2 -> mcasp6 */
3149 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3150         .master         = &dra7xx_l4_per2_hwmod,
3151         .slave          = &dra7xx_mcasp6_hwmod,
3152         .clk            = "l4_root_clk_div",
3153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3154 };
3155
3156 /* l4_per2 -> mcasp7 */
3157 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3158         .master         = &dra7xx_l4_per2_hwmod,
3159         .slave          = &dra7xx_mcasp7_hwmod,
3160         .clk            = "l4_root_clk_div",
3161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3162 };
3163
3164 /* l4_per2 -> mcasp8 */
3165 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3166         .master         = &dra7xx_l4_per2_hwmod,
3167         .slave          = &dra7xx_mcasp8_hwmod,
3168         .clk            = "l4_root_clk_div",
3169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3170 };
3171
3172 /* l4_per1 -> elm */
3173 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3174         .master         = &dra7xx_l4_per1_hwmod,
3175         .slave          = &dra7xx_elm_hwmod,
3176         .clk            = "l3_iclk_div",
3177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3178 };
3179
3180 /* l4_wkup -> gpio1 */
3181 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3182         .master         = &dra7xx_l4_wkup_hwmod,
3183         .slave          = &dra7xx_gpio1_hwmod,
3184         .clk            = "wkupaon_iclk_mux",
3185         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3186 };
3187
3188 /* l4_per1 -> gpio2 */
3189 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3190         .master         = &dra7xx_l4_per1_hwmod,
3191         .slave          = &dra7xx_gpio2_hwmod,
3192         .clk            = "l3_iclk_div",
3193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3194 };
3195
3196 /* l4_per1 -> gpio3 */
3197 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3198         .master         = &dra7xx_l4_per1_hwmod,
3199         .slave          = &dra7xx_gpio3_hwmod,
3200         .clk            = "l3_iclk_div",
3201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3202 };
3203
3204 /* l4_per1 -> gpio4 */
3205 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3206         .master         = &dra7xx_l4_per1_hwmod,
3207         .slave          = &dra7xx_gpio4_hwmod,
3208         .clk            = "l3_iclk_div",
3209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3210 };
3211
3212 /* l4_per1 -> gpio5 */
3213 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3214         .master         = &dra7xx_l4_per1_hwmod,
3215         .slave          = &dra7xx_gpio5_hwmod,
3216         .clk            = "l3_iclk_div",
3217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3218 };
3219
3220 /* l4_per1 -> gpio6 */
3221 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3222         .master         = &dra7xx_l4_per1_hwmod,
3223         .slave          = &dra7xx_gpio6_hwmod,
3224         .clk            = "l3_iclk_div",
3225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3226 };
3227
3228 /* l4_per1 -> gpio7 */
3229 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3230         .master         = &dra7xx_l4_per1_hwmod,
3231         .slave          = &dra7xx_gpio7_hwmod,
3232         .clk            = "l3_iclk_div",
3233         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3234 };
3235
3236 /* l4_per1 -> gpio8 */
3237 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3238         .master         = &dra7xx_l4_per1_hwmod,
3239         .slave          = &dra7xx_gpio8_hwmod,
3240         .clk            = "l3_iclk_div",
3241         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3242 };
3243
3244 /* l3_main_1 -> gpmc */
3245 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3246         .master         = &dra7xx_l3_main_1_hwmod,
3247         .slave          = &dra7xx_gpmc_hwmod,
3248         .clk            = "l3_iclk_div",
3249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3250 };
3251
3252 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
3253         {
3254                 .pa_start       = 0x480b2000,
3255                 .pa_end         = 0x480b201f,
3256                 .flags          = ADDR_TYPE_RT
3257         },
3258         { }
3259 };
3260
3261 /* l4_per1 -> hdq1w */
3262 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3263         .master         = &dra7xx_l4_per1_hwmod,
3264         .slave          = &dra7xx_hdq1w_hwmod,
3265         .clk            = "l3_iclk_div",
3266         .addr           = dra7xx_hdq1w_addrs,
3267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3268 };
3269
3270 /* l4_per1 -> i2c1 */
3271 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3272         .master         = &dra7xx_l4_per1_hwmod,
3273         .slave          = &dra7xx_i2c1_hwmod,
3274         .clk            = "l3_iclk_div",
3275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3276 };
3277
3278 /* l4_per1 -> i2c2 */
3279 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3280         .master         = &dra7xx_l4_per1_hwmod,
3281         .slave          = &dra7xx_i2c2_hwmod,
3282         .clk            = "l3_iclk_div",
3283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3284 };
3285
3286 /* l4_per1 -> i2c3 */
3287 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3288         .master         = &dra7xx_l4_per1_hwmod,
3289         .slave          = &dra7xx_i2c3_hwmod,
3290         .clk            = "l3_iclk_div",
3291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3292 };
3293
3294 /* l4_per1 -> i2c4 */
3295 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3296         .master         = &dra7xx_l4_per1_hwmod,
3297         .slave          = &dra7xx_i2c4_hwmod,
3298         .clk            = "l3_iclk_div",
3299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3300 };
3301
3302 /* l4_per1 -> i2c5 */
3303 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3304         .master         = &dra7xx_l4_per1_hwmod,
3305         .slave          = &dra7xx_i2c5_hwmod,
3306         .clk            = "l3_iclk_div",
3307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3308 };
3309
3310 /* l4_cfg -> mailbox1 */
3311 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3312         .master         = &dra7xx_l4_cfg_hwmod,
3313         .slave          = &dra7xx_mailbox1_hwmod,
3314         .clk            = "l3_iclk_div",
3315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3316 };
3317
3318 /* l4_per3 -> mailbox2 */
3319 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3320         .master         = &dra7xx_l4_per3_hwmod,
3321         .slave          = &dra7xx_mailbox2_hwmod,
3322         .clk            = "l3_iclk_div",
3323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3324 };
3325
3326 /* l4_per3 -> mailbox3 */
3327 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3328         .master         = &dra7xx_l4_per3_hwmod,
3329         .slave          = &dra7xx_mailbox3_hwmod,
3330         .clk            = "l3_iclk_div",
3331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3332 };
3333
3334 /* l4_per3 -> mailbox4 */
3335 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3336         .master         = &dra7xx_l4_per3_hwmod,
3337         .slave          = &dra7xx_mailbox4_hwmod,
3338         .clk            = "l3_iclk_div",
3339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3340 };
3341
3342 /* l4_per3 -> mailbox5 */
3343 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3344         .master         = &dra7xx_l4_per3_hwmod,
3345         .slave          = &dra7xx_mailbox5_hwmod,
3346         .clk            = "l3_iclk_div",
3347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3348 };
3349
3350 /* l4_per3 -> mailbox6 */
3351 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3352         .master         = &dra7xx_l4_per3_hwmod,
3353         .slave          = &dra7xx_mailbox6_hwmod,
3354         .clk            = "l3_iclk_div",
3355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3356 };
3357
3358 /* l4_per3 -> mailbox7 */
3359 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3360         .master         = &dra7xx_l4_per3_hwmod,
3361         .slave          = &dra7xx_mailbox7_hwmod,
3362         .clk            = "l3_iclk_div",
3363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3364 };
3365
3366 /* l4_per3 -> mailbox8 */
3367 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3368         .master         = &dra7xx_l4_per3_hwmod,
3369         .slave          = &dra7xx_mailbox8_hwmod,
3370         .clk            = "l3_iclk_div",
3371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3372 };
3373
3374 /* l4_per3 -> mailbox9 */
3375 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3376         .master         = &dra7xx_l4_per3_hwmod,
3377         .slave          = &dra7xx_mailbox9_hwmod,
3378         .clk            = "l3_iclk_div",
3379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3380 };
3381
3382 /* l4_per3 -> mailbox10 */
3383 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3384         .master         = &dra7xx_l4_per3_hwmod,
3385         .slave          = &dra7xx_mailbox10_hwmod,
3386         .clk            = "l3_iclk_div",
3387         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3388 };
3389
3390 /* l4_per3 -> mailbox11 */
3391 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3392         .master         = &dra7xx_l4_per3_hwmod,
3393         .slave          = &dra7xx_mailbox11_hwmod,
3394         .clk            = "l3_iclk_div",
3395         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3396 };
3397
3398 /* l4_per3 -> mailbox12 */
3399 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3400         .master         = &dra7xx_l4_per3_hwmod,
3401         .slave          = &dra7xx_mailbox12_hwmod,
3402         .clk            = "l3_iclk_div",
3403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3404 };
3405
3406 /* l4_per3 -> mailbox13 */
3407 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3408         .master         = &dra7xx_l4_per3_hwmod,
3409         .slave          = &dra7xx_mailbox13_hwmod,
3410         .clk            = "l3_iclk_div",
3411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3412 };
3413
3414 /* l4_per1 -> mcspi1 */
3415 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3416         .master         = &dra7xx_l4_per1_hwmod,
3417         .slave          = &dra7xx_mcspi1_hwmod,
3418         .clk            = "l3_iclk_div",
3419         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3420 };
3421
3422 /* l4_per1 -> mcspi2 */
3423 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3424         .master         = &dra7xx_l4_per1_hwmod,
3425         .slave          = &dra7xx_mcspi2_hwmod,
3426         .clk            = "l3_iclk_div",
3427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3428 };
3429
3430 /* l4_per1 -> mcspi3 */
3431 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3432         .master         = &dra7xx_l4_per1_hwmod,
3433         .slave          = &dra7xx_mcspi3_hwmod,
3434         .clk            = "l3_iclk_div",
3435         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3436 };
3437
3438 /* l4_per1 -> mcspi4 */
3439 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3440         .master         = &dra7xx_l4_per1_hwmod,
3441         .slave          = &dra7xx_mcspi4_hwmod,
3442         .clk            = "l3_iclk_div",
3443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3444 };
3445
3446 /* l4_per1 -> mmc1 */
3447 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3448         .master         = &dra7xx_l4_per1_hwmod,
3449         .slave          = &dra7xx_mmc1_hwmod,
3450         .clk            = "l3_iclk_div",
3451         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3452 };
3453
3454 /* l4_per1 -> mmc2 */
3455 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3456         .master         = &dra7xx_l4_per1_hwmod,
3457         .slave          = &dra7xx_mmc2_hwmod,
3458         .clk            = "l3_iclk_div",
3459         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3460 };
3461
3462 /* l4_per1 -> mmc3 */
3463 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3464         .master         = &dra7xx_l4_per1_hwmod,
3465         .slave          = &dra7xx_mmc3_hwmod,
3466         .clk            = "l3_iclk_div",
3467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3468 };
3469
3470 /* l4_per1 -> mmc4 */
3471 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3472         .master         = &dra7xx_l4_per1_hwmod,
3473         .slave          = &dra7xx_mmc4_hwmod,
3474         .clk            = "l3_iclk_div",
3475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3476 };
3477
3478 /* l4_cfg -> mpu */
3479 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3480         .master         = &dra7xx_l4_cfg_hwmod,
3481         .slave          = &dra7xx_mpu_hwmod,
3482         .clk            = "l3_iclk_div",
3483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3484 };
3485
3486 /* l4_cfg -> ocp2scp1 */
3487 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3488         .master         = &dra7xx_l4_cfg_hwmod,
3489         .slave          = &dra7xx_ocp2scp1_hwmod,
3490         .clk            = "l4_root_clk_div",
3491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3492 };
3493
3494 /* l4_cfg -> ocp2scp3 */
3495 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3496         .master         = &dra7xx_l4_cfg_hwmod,
3497         .slave          = &dra7xx_ocp2scp3_hwmod,
3498         .clk            = "l4_root_clk_div",
3499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3500 };
3501
3502 /* l3_main_1 -> pciess1 */
3503 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3504         .master         = &dra7xx_l3_main_1_hwmod,
3505         .slave          = &dra7xx_pciess1_hwmod,
3506         .clk            = "l3_iclk_div",
3507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3508 };
3509
3510 /* l4_cfg -> pciess1 */
3511 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3512         .master         = &dra7xx_l4_cfg_hwmod,
3513         .slave          = &dra7xx_pciess1_hwmod,
3514         .clk            = "l4_root_clk_div",
3515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3516 };
3517
3518 /* l3_main_1 -> pciess2 */
3519 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3520         .master         = &dra7xx_l3_main_1_hwmod,
3521         .slave          = &dra7xx_pciess2_hwmod,
3522         .clk            = "l3_iclk_div",
3523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3524 };
3525
3526 /* l4_cfg -> pciess2 */
3527 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3528         .master         = &dra7xx_l4_cfg_hwmod,
3529         .slave          = &dra7xx_pciess2_hwmod,
3530         .clk            = "l4_root_clk_div",
3531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3532 };
3533
3534 /* l3_main_1 -> qspi */
3535 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3536         .master         = &dra7xx_l3_main_1_hwmod,
3537         .slave          = &dra7xx_qspi_hwmod,
3538         .clk            = "l3_iclk_div",
3539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3540 };
3541
3542 /* l4_per3 -> rtcss */
3543 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3544         .master         = &dra7xx_l4_per3_hwmod,
3545         .slave          = &dra7xx_rtcss_hwmod,
3546         .clk            = "l4_root_clk_div",
3547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3548 };
3549
3550 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
3551         {
3552                 .name           = "sysc",
3553                 .pa_start       = 0x4a141100,
3554                 .pa_end         = 0x4a141107,
3555                 .flags          = ADDR_TYPE_RT
3556         },
3557         { }
3558 };
3559
3560 /* l4_cfg -> sata */
3561 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3562         .master         = &dra7xx_l4_cfg_hwmod,
3563         .slave          = &dra7xx_sata_hwmod,
3564         .clk            = "l3_iclk_div",
3565         .addr           = dra7xx_sata_addrs,
3566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3567 };
3568
3569 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
3570         {
3571                 .pa_start       = 0x4a0dd000,
3572                 .pa_end         = 0x4a0dd07f,
3573                 .flags          = ADDR_TYPE_RT
3574         },
3575         { }
3576 };
3577
3578 /* l4_cfg -> smartreflex_core */
3579 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3580         .master         = &dra7xx_l4_cfg_hwmod,
3581         .slave          = &dra7xx_smartreflex_core_hwmod,
3582         .clk            = "l4_root_clk_div",
3583         .addr           = dra7xx_smartreflex_core_addrs,
3584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3585 };
3586
3587 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
3588         {
3589                 .pa_start       = 0x4a0d9000,
3590                 .pa_end         = 0x4a0d907f,
3591                 .flags          = ADDR_TYPE_RT
3592         },
3593         { }
3594 };
3595
3596 /* l4_cfg -> smartreflex_mpu */
3597 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3598         .master         = &dra7xx_l4_cfg_hwmod,
3599         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3600         .clk            = "l4_root_clk_div",
3601         .addr           = dra7xx_smartreflex_mpu_addrs,
3602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3603 };
3604
3605 /* l4_cfg -> spinlock */
3606 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3607         .master         = &dra7xx_l4_cfg_hwmod,
3608         .slave          = &dra7xx_spinlock_hwmod,
3609         .clk            = "l3_iclk_div",
3610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3611 };
3612
3613 /* l4_wkup -> timer1 */
3614 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3615         .master         = &dra7xx_l4_wkup_hwmod,
3616         .slave          = &dra7xx_timer1_hwmod,
3617         .clk            = "wkupaon_iclk_mux",
3618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3619 };
3620
3621 /* l4_per1 -> timer2 */
3622 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3623         .master         = &dra7xx_l4_per1_hwmod,
3624         .slave          = &dra7xx_timer2_hwmod,
3625         .clk            = "l3_iclk_div",
3626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3627 };
3628
3629 /* l4_per1 -> timer3 */
3630 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3631         .master         = &dra7xx_l4_per1_hwmod,
3632         .slave          = &dra7xx_timer3_hwmod,
3633         .clk            = "l3_iclk_div",
3634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3635 };
3636
3637 /* l4_per1 -> timer4 */
3638 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3639         .master         = &dra7xx_l4_per1_hwmod,
3640         .slave          = &dra7xx_timer4_hwmod,
3641         .clk            = "l3_iclk_div",
3642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3643 };
3644
3645 /* l4_per3 -> timer5 */
3646 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3647         .master         = &dra7xx_l4_per3_hwmod,
3648         .slave          = &dra7xx_timer5_hwmod,
3649         .clk            = "l3_iclk_div",
3650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3651 };
3652
3653 /* l4_per3 -> timer6 */
3654 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3655         .master         = &dra7xx_l4_per3_hwmod,
3656         .slave          = &dra7xx_timer6_hwmod,
3657         .clk            = "l3_iclk_div",
3658         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3659 };
3660
3661 /* l4_per3 -> timer7 */
3662 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3663         .master         = &dra7xx_l4_per3_hwmod,
3664         .slave          = &dra7xx_timer7_hwmod,
3665         .clk            = "l3_iclk_div",
3666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3667 };
3668
3669 /* l4_per3 -> timer8 */
3670 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3671         .master         = &dra7xx_l4_per3_hwmod,
3672         .slave          = &dra7xx_timer8_hwmod,
3673         .clk            = "l3_iclk_div",
3674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3675 };
3676
3677 /* l4_per1 -> timer9 */
3678 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3679         .master         = &dra7xx_l4_per1_hwmod,
3680         .slave          = &dra7xx_timer9_hwmod,
3681         .clk            = "l3_iclk_div",
3682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3683 };
3684
3685 /* l4_per1 -> timer10 */
3686 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3687         .master         = &dra7xx_l4_per1_hwmod,
3688         .slave          = &dra7xx_timer10_hwmod,
3689         .clk            = "l3_iclk_div",
3690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3691 };
3692
3693 /* l4_per1 -> timer11 */
3694 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3695         .master         = &dra7xx_l4_per1_hwmod,
3696         .slave          = &dra7xx_timer11_hwmod,
3697         .clk            = "l3_iclk_div",
3698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3699 };
3700
3701 /* l4_wkup -> timer12 */
3702 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3703         .master         = &dra7xx_l4_wkup_hwmod,
3704         .slave          = &dra7xx_timer12_hwmod,
3705         .clk            = "wkupaon_iclk_mux",
3706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3707 };
3708
3709 /* l4_per3 -> timer13 */
3710 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3711         .master         = &dra7xx_l4_per3_hwmod,
3712         .slave          = &dra7xx_timer13_hwmod,
3713         .clk            = "l3_iclk_div",
3714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3715 };
3716
3717 /* l4_per3 -> timer14 */
3718 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3719         .master         = &dra7xx_l4_per3_hwmod,
3720         .slave          = &dra7xx_timer14_hwmod,
3721         .clk            = "l3_iclk_div",
3722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3723 };
3724
3725 /* l4_per3 -> timer15 */
3726 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3727         .master         = &dra7xx_l4_per3_hwmod,
3728         .slave          = &dra7xx_timer15_hwmod,
3729         .clk            = "l3_iclk_div",
3730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3731 };
3732
3733 /* l4_per3 -> timer16 */
3734 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3735         .master         = &dra7xx_l4_per3_hwmod,
3736         .slave          = &dra7xx_timer16_hwmod,
3737         .clk            = "l3_iclk_div",
3738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3739 };
3740
3741 /* l4_per1 -> uart1 */
3742 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3743         .master         = &dra7xx_l4_per1_hwmod,
3744         .slave          = &dra7xx_uart1_hwmod,
3745         .clk            = "l3_iclk_div",
3746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3747 };
3748
3749 /* l4_per1 -> uart2 */
3750 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3751         .master         = &dra7xx_l4_per1_hwmod,
3752         .slave          = &dra7xx_uart2_hwmod,
3753         .clk            = "l3_iclk_div",
3754         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3755 };
3756
3757 /* l4_per1 -> uart3 */
3758 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3759         .master         = &dra7xx_l4_per1_hwmod,
3760         .slave          = &dra7xx_uart3_hwmod,
3761         .clk            = "l3_iclk_div",
3762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3763 };
3764
3765 /* l4_per1 -> uart4 */
3766 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3767         .master         = &dra7xx_l4_per1_hwmod,
3768         .slave          = &dra7xx_uart4_hwmod,
3769         .clk            = "l3_iclk_div",
3770         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3771 };
3772
3773 /* l4_per1 -> uart5 */
3774 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3775         .master         = &dra7xx_l4_per1_hwmod,
3776         .slave          = &dra7xx_uart5_hwmod,
3777         .clk            = "l3_iclk_div",
3778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3779 };
3780
3781 /* l4_per1 -> uart6 */
3782 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3783         .master         = &dra7xx_l4_per1_hwmod,
3784         .slave          = &dra7xx_uart6_hwmod,
3785         .clk            = "l3_iclk_div",
3786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3787 };
3788
3789 /* l4_per2 -> uart7 */
3790 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3791         .master         = &dra7xx_l4_per2_hwmod,
3792         .slave          = &dra7xx_uart7_hwmod,
3793         .clk            = "l3_iclk_div",
3794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3795 };
3796
3797 /* l4_per1 -> des */
3798 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3799         .master         = &dra7xx_l4_per1_hwmod,
3800         .slave          = &dra7xx_des_hwmod,
3801         .clk            = "l3_iclk_div",
3802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3803 };
3804
3805 /* l4_per2 -> uart8 */
3806 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3807         .master         = &dra7xx_l4_per2_hwmod,
3808         .slave          = &dra7xx_uart8_hwmod,
3809         .clk            = "l3_iclk_div",
3810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3811 };
3812
3813 /* l4_per2 -> uart9 */
3814 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3815         .master         = &dra7xx_l4_per2_hwmod,
3816         .slave          = &dra7xx_uart9_hwmod,
3817         .clk            = "l3_iclk_div",
3818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3819 };
3820
3821 /* l4_wkup -> uart10 */
3822 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3823         .master         = &dra7xx_l4_wkup_hwmod,
3824         .slave          = &dra7xx_uart10_hwmod,
3825         .clk            = "wkupaon_iclk_mux",
3826         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3827 };
3828
3829 /* l4_per1 -> rng */
3830 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3831         .master         = &dra7xx_l4_per1_hwmod,
3832         .slave          = &dra7xx_rng_hwmod,
3833         .user           = OCP_USER_MPU,
3834 };
3835
3836 /* l4_per3 -> usb_otg_ss1 */
3837 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3838         .master         = &dra7xx_l4_per3_hwmod,
3839         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3840         .clk            = "dpll_core_h13x2_ck",
3841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3842 };
3843
3844 /* l4_per3 -> usb_otg_ss2 */
3845 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3846         .master         = &dra7xx_l4_per3_hwmod,
3847         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3848         .clk            = "dpll_core_h13x2_ck",
3849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3850 };
3851
3852 /* l4_per3 -> usb_otg_ss3 */
3853 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3854         .master         = &dra7xx_l4_per3_hwmod,
3855         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3856         .clk            = "dpll_core_h13x2_ck",
3857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3858 };
3859
3860 /* l4_per3 -> usb_otg_ss4 */
3861 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3862         .master         = &dra7xx_l4_per3_hwmod,
3863         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3864         .clk            = "dpll_core_h13x2_ck",
3865         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3866 };
3867
3868 /* l3_main_1 -> vcp1 */
3869 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3870         .master         = &dra7xx_l3_main_1_hwmod,
3871         .slave          = &dra7xx_vcp1_hwmod,
3872         .clk            = "l3_iclk_div",
3873         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3874 };
3875
3876 /* l4_per2 -> vcp1 */
3877 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3878         .master         = &dra7xx_l4_per2_hwmod,
3879         .slave          = &dra7xx_vcp1_hwmod,
3880         .clk            = "l3_iclk_div",
3881         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3882 };
3883
3884 /* l3_main_1 -> vcp2 */
3885 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3886         .master         = &dra7xx_l3_main_1_hwmod,
3887         .slave          = &dra7xx_vcp2_hwmod,
3888         .clk            = "l3_iclk_div",
3889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3890 };
3891
3892 /* l4_per2 -> vcp2 */
3893 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3894         .master         = &dra7xx_l4_per2_hwmod,
3895         .slave          = &dra7xx_vcp2_hwmod,
3896         .clk            = "l3_iclk_div",
3897         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3898 };
3899
3900 /* l4_wkup -> wd_timer2 */
3901 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3902         .master         = &dra7xx_l4_wkup_hwmod,
3903         .slave          = &dra7xx_wd_timer2_hwmod,
3904         .clk            = "wkupaon_iclk_mux",
3905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3906 };
3907
3908 /* l4_per2 -> epwmss0 */
3909 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3910         .master         = &dra7xx_l4_per2_hwmod,
3911         .slave          = &dra7xx_epwmss0_hwmod,
3912         .clk            = "l4_root_clk_div",
3913         .user           = OCP_USER_MPU,
3914 };
3915
3916 /* l4_per2 -> epwmss1 */
3917 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3918         .master         = &dra7xx_l4_per2_hwmod,
3919         .slave          = &dra7xx_epwmss1_hwmod,
3920         .clk            = "l4_root_clk_div",
3921         .user           = OCP_USER_MPU,
3922 };
3923
3924 /* l4_per2 -> epwmss2 */
3925 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3926         .master         = &dra7xx_l4_per2_hwmod,
3927         .slave          = &dra7xx_epwmss2_hwmod,
3928         .clk            = "l4_root_clk_div",
3929         .user           = OCP_USER_MPU,
3930 };
3931
3932 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3933         &dra7xx_l3_main_1__dmm,
3934         &dra7xx_l3_main_2__l3_instr,
3935         &dra7xx_l4_cfg__l3_main_1,
3936         &dra7xx_mpu__l3_main_1,
3937         &dra7xx_l3_main_1__l3_main_2,
3938         &dra7xx_l4_cfg__l3_main_2,
3939         &dra7xx_l3_main_1__l4_cfg,
3940         &dra7xx_l3_main_1__l4_per1,
3941         &dra7xx_l3_main_1__l4_per2,
3942         &dra7xx_l3_main_1__l4_per3,
3943         &dra7xx_l3_main_1__l4_wkup,
3944         &dra7xx_l4_per2__atl,
3945         &dra7xx_l3_main_1__bb2d,
3946         &dra7xx_l4_wkup__counter_32k,
3947         &dra7xx_l4_wkup__ctrl_module_wkup,
3948         &dra7xx_l4_wkup__dcan1,
3949         &dra7xx_l4_per2__dcan2,
3950         &dra7xx_l4_per2__cpgmac0,
3951         &dra7xx_l4_per2__mcasp1,
3952         &dra7xx_l3_main_1__mcasp1,
3953         &dra7xx_l4_per2__mcasp2,
3954         &dra7xx_l3_main_1__mcasp2,
3955         &dra7xx_l4_per2__mcasp3,
3956         &dra7xx_l3_main_1__mcasp3,
3957         &dra7xx_l4_per2__mcasp4,
3958         &dra7xx_l4_per2__mcasp5,
3959         &dra7xx_l4_per2__mcasp6,
3960         &dra7xx_l4_per2__mcasp7,
3961         &dra7xx_l4_per2__mcasp8,
3962         &dra7xx_gmac__mdio,
3963         &dra7xx_l4_cfg__dma_system,
3964         &dra7xx_l3_main_1__tpcc,
3965         &dra7xx_l3_main_1__tptc0,
3966         &dra7xx_l3_main_1__tptc1,
3967         &dra7xx_l3_main_1__dss,
3968         &dra7xx_l3_main_1__dispc,
3969         &dra7xx_l3_main_1__hdmi,
3970         &dra7xx_l3_main_1__aes1,
3971         &dra7xx_l3_main_1__aes2,
3972         &dra7xx_l3_main_1__sha0,
3973         &dra7xx_l4_per1__elm,
3974         &dra7xx_l4_wkup__gpio1,
3975         &dra7xx_l4_per1__gpio2,
3976         &dra7xx_l4_per1__gpio3,
3977         &dra7xx_l4_per1__gpio4,
3978         &dra7xx_l4_per1__gpio5,
3979         &dra7xx_l4_per1__gpio6,
3980         &dra7xx_l4_per1__gpio7,
3981         &dra7xx_l4_per1__gpio8,
3982         &dra7xx_l3_main_1__gpmc,
3983         &dra7xx_l4_per1__hdq1w,
3984         &dra7xx_l4_per1__i2c1,
3985         &dra7xx_l4_per1__i2c2,
3986         &dra7xx_l4_per1__i2c3,
3987         &dra7xx_l4_per1__i2c4,
3988         &dra7xx_l4_per1__i2c5,
3989         &dra7xx_l4_cfg__mailbox1,
3990         &dra7xx_l4_per3__mailbox2,
3991         &dra7xx_l4_per3__mailbox3,
3992         &dra7xx_l4_per3__mailbox4,
3993         &dra7xx_l4_per3__mailbox5,
3994         &dra7xx_l4_per3__mailbox6,
3995         &dra7xx_l4_per3__mailbox7,
3996         &dra7xx_l4_per3__mailbox8,
3997         &dra7xx_l4_per3__mailbox9,
3998         &dra7xx_l4_per3__mailbox10,
3999         &dra7xx_l4_per3__mailbox11,
4000         &dra7xx_l4_per3__mailbox12,
4001         &dra7xx_l4_per3__mailbox13,
4002         &dra7xx_l4_per1__mcspi1,
4003         &dra7xx_l4_per1__mcspi2,
4004         &dra7xx_l4_per1__mcspi3,
4005         &dra7xx_l4_per1__mcspi4,
4006         &dra7xx_l4_per1__mmc1,
4007         &dra7xx_l4_per1__mmc2,
4008         &dra7xx_l4_per1__mmc3,
4009         &dra7xx_l4_per1__mmc4,
4010         &dra7xx_l4_cfg__mpu,
4011         &dra7xx_l4_cfg__ocp2scp1,
4012         &dra7xx_l4_cfg__ocp2scp3,
4013         &dra7xx_l3_main_1__pciess1,
4014         &dra7xx_l4_cfg__pciess1,
4015         &dra7xx_l3_main_1__pciess2,
4016         &dra7xx_l4_cfg__pciess2,
4017         &dra7xx_l3_main_1__qspi,
4018         &dra7xx_l4_cfg__sata,
4019         &dra7xx_l4_cfg__smartreflex_core,
4020         &dra7xx_l4_cfg__smartreflex_mpu,
4021         &dra7xx_l4_cfg__spinlock,
4022         &dra7xx_l4_wkup__timer1,
4023         &dra7xx_l4_per1__timer2,
4024         &dra7xx_l4_per1__timer3,
4025         &dra7xx_l4_per1__timer4,
4026         &dra7xx_l4_per3__timer5,
4027         &dra7xx_l4_per3__timer6,
4028         &dra7xx_l4_per3__timer7,
4029         &dra7xx_l4_per3__timer8,
4030         &dra7xx_l4_per1__timer9,
4031         &dra7xx_l4_per1__timer10,
4032         &dra7xx_l4_per1__timer11,
4033         &dra7xx_l4_per3__timer13,
4034         &dra7xx_l4_per3__timer14,
4035         &dra7xx_l4_per3__timer15,
4036         &dra7xx_l4_per3__timer16,
4037         &dra7xx_l4_per1__uart1,
4038         &dra7xx_l4_per1__uart2,
4039         &dra7xx_l4_per1__uart3,
4040         &dra7xx_l4_per1__uart4,
4041         &dra7xx_l4_per1__uart5,
4042         &dra7xx_l4_per1__uart6,
4043         &dra7xx_l4_per2__uart7,
4044         &dra7xx_l4_per2__uart8,
4045         &dra7xx_l4_per2__uart9,
4046         &dra7xx_l4_wkup__uart10,
4047         &dra7xx_l4_per1__des,
4048         &dra7xx_l4_per3__usb_otg_ss1,
4049         &dra7xx_l4_per3__usb_otg_ss2,
4050         &dra7xx_l4_per3__usb_otg_ss3,
4051         &dra7xx_l3_main_1__vcp1,
4052         &dra7xx_l4_per2__vcp1,
4053         &dra7xx_l3_main_1__vcp2,
4054         &dra7xx_l4_per2__vcp2,
4055         &dra7xx_l4_wkup__wd_timer2,
4056         &dra7xx_l4_per2__epwmss0,
4057         &dra7xx_l4_per2__epwmss1,
4058         &dra7xx_l4_per2__epwmss2,
4059         NULL,
4060 };
4061
4062 /* GP-only hwmod links */
4063 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4064         &dra7xx_l4_wkup__timer12,
4065         &dra7xx_l4_per1__rng,
4066         NULL,
4067 };
4068
4069 /* SoC variant specific hwmod links */
4070 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4071         &dra7xx_l4_per3__usb_otg_ss4,
4072         NULL,
4073 };
4074
4075 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4076         NULL,
4077 };
4078
4079 static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = {
4080         &dra7xx_l4_per3__rtcss,
4081         NULL,
4082 };
4083
4084 int __init dra7xx_hwmod_init(void)
4085 {
4086         int ret;
4087
4088         omap_hwmod_init();
4089         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4090
4091         if (!ret && soc_is_dra74x())
4092                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4093         else if (!ret && soc_is_dra72x())
4094                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4095
4096         if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4097                 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4098
4099         /* now for the IPs *NOT* in dra71 */
4100         if (!ret && !of_machine_is_compatible("ti,dra718"))
4101                 ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);
4102
4103         return ret;
4104 }