2 * sleep mode for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/linkage.h>
10 #include <asm/ptrace.h>
11 #include <asm/assembler.h>
15 #define DENALI_CTL_22_OFF 0x58
16 #define DENALI_CTL_112_OFF 0x1c0
20 ENTRY(sirfsoc_finish_suspend)
22 ldr r0, =sirfsoc_memc_base
24 @ r6: pwrc base offset
25 ldr r0, =sirfsoc_pwrc_base
27 @ r7: rtc iobrg controller
28 ldr r0, =sirfsoc_rtciobrg_base
31 @ Read the power control register and set the
33 add r0, r6, #SIRFSOC_PWRC_PDN_CTRL
34 bl __sirfsoc_rtc_iobrg_readl
35 orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE
36 add r1, r6, #SIRFSOC_PWRC_PDN_CTRL
37 bl sirfsoc_rtc_iobrg_pre_writel
40 @ read the MEM ctl register and set the self
43 ldr r2, [r5, #DENALI_CTL_22_OFF]
46 @ Following code has to run from cache since
47 @ the RAM is going to self refresh mode
49 str r2, [r5, #DENALI_CTL_22_OFF]
52 ldr r4, [r5, #DENALI_CTL_112_OFF]
56 @ write SLEEPFORCE through rtc iobridge
59 @ wait rtc io bridge sync