arch/arm/mach-s3c64xx/common.c

   1 /*
   2  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Copyright 2008 Openmoko, Inc.
   6  * Copyright 2008 Simtec Electronics
   7  *      Ben Dooks <ben@simtec.co.uk>
   8  *      http://armlinux.simtec.co.uk/
   9  *
  10  * Common Codes for S3C64XX machines
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/reboot.h>
  26 #include <linux/io.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/irq.h>
  29 #include <linux/gpio.h>
  30 #include <linux/irqchip/arm-vic.h>
  31 #include <clocksource/samsung_pwm.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/system_misc.h>
  36
  37 #include <mach/map.h>
  38 #include <mach/hardware.h>
  39 #include <mach/regs-gpio.h>
  40
  41 #include <plat/cpu.h>
  42 #include <plat/devs.h>
  43 #include <plat/pm.h>
  44 #include <plat/gpio-cfg.h>
  45 #include <plat/irq-uart.h>
  46 #include <plat/pwm-core.h>
  47 #include <plat/regs-irqtype.h>
  48 #include <plat/regs-serial.h>
  49 #include <plat/watchdog-reset.h>
  50
  51 #include "common.h"
  52
  53 /* External clock frequency */
  54 static unsigned long xtal_f = 12000000, xusbxti_f = 48000000;
  55
  56 void __init s3c64xx_set_xtal_freq(unsigned long freq)
  57 {
  58         xtal_f = freq;
  59 }
  60
  61 void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
  62 {
  63         xusbxti_f = freq;
  64 }
  65
  66 /* uart registration process */
  67
  68 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  69 {
  70         s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
  71 }
  72
  73 /* table of supported CPUs */
  74
  75 static const char name_s3c6400[] = "S3C6400";
  76 static const char name_s3c6410[] = "S3C6410";
  77
  78 static struct cpu_table cpu_ids[] __initdata = {
  79         {
  80                 .idcode         = S3C6400_CPU_ID,
  81                 .idmask         = S3C64XX_CPU_MASK,
  82                 .map_io         = s3c6400_map_io,
  83                 .init_uarts     = s3c64xx_init_uarts,
  84                 .init           = s3c6400_init,
  85                 .name           = name_s3c6400,
  86         }, {
  87                 .idcode         = S3C6410_CPU_ID,
  88                 .idmask         = S3C64XX_CPU_MASK,
  89                 .map_io         = s3c6410_map_io,
  90                 .init_uarts     = s3c64xx_init_uarts,
  91                 .init           = s3c6410_init,
  92                 .name           = name_s3c6410,
  93         },
  94 };
  95
  96 /* minimal IO mapping */
  97
  98 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
  99 #define UART_OFFS (S3C_PA_UART & 0xfffff)
 100
 101 static struct map_desc s3c_iodesc[] __initdata = {
 102         {
 103                 .virtual        = (unsigned long)S3C_VA_SYS,
 104                 .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
 105                 .length         = SZ_4K,
 106                 .type           = MT_DEVICE,
 107         }, {
 108                 .virtual        = (unsigned long)S3C_VA_MEM,
 109                 .pfn            = __phys_to_pfn(S3C64XX_PA_SROM),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE,
 112         }, {
 113                 .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
 114                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 115                 .length         = SZ_4K,
 116                 .type           = MT_DEVICE,
 117         }, {
 118                 .virtual        = (unsigned long)VA_VIC0,
 119                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
 120                 .length         = SZ_16K,
 121                 .type           = MT_DEVICE,
 122         }, {
 123                 .virtual        = (unsigned long)VA_VIC1,
 124                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
 125                 .length         = SZ_16K,
 126                 .type           = MT_DEVICE,
 127         }, {
 128                 .virtual        = (unsigned long)S3C_VA_TIMER,
 129                 .pfn            = __phys_to_pfn(S3C_PA_TIMER),
 130                 .length         = SZ_16K,
 131                 .type           = MT_DEVICE,
 132         }, {
 133                 .virtual        = (unsigned long)S3C64XX_VA_GPIO,
 134                 .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
 135                 .length         = SZ_4K,
 136                 .type           = MT_DEVICE,
 137         }, {
 138                 .virtual        = (unsigned long)S3C64XX_VA_MODEM,
 139                 .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
 140                 .length         = SZ_4K,
 141                 .type           = MT_DEVICE,
 142         }, {
 143                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 144                 .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
 145                 .length         = SZ_4K,
 146                 .type           = MT_DEVICE,
 147         }, {
 148                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 149                 .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
 150                 .length         = SZ_1K,
 151                 .type           = MT_DEVICE,
 152         },
 153 };
 154
 155 static struct bus_type s3c64xx_subsys = {
 156         .name           = "s3c64xx-core",
 157         .dev_name       = "s3c64xx-core",
 158 };
 159
 160 static struct device s3c64xx_dev = {
 161         .bus    = &s3c64xx_subsys,
 162 };
 163
 164 static struct samsung_pwm_variant s3c64xx_pwm_variant = {
 165         .bits           = 32,
 166         .div_base       = 0,
 167         .has_tint_cstat = true,
 168         .tclk_mask      = (1 << 7) | (1 << 6) | (1 << 5),
 169 };
 170
 171 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 172 {
 173         s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 174         s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 175 }
 176
 177 void __init samsung_timer_init(void)
 178 {
 179         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 180                 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
 181                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
 182         };
 183
 184         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 185                                         timer_irqs, &s3c64xx_pwm_variant);
 186 }
 187
 188 /* read cpu identification code */
 189
 190 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
 191 {
 192         /* initialise the io descriptors we need for initialisation */
 193         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 194         iotable_init(mach_desc, size);
 195
 196         /* detect cpu id */
 197         s3c64xx_init_cpu();
 198
 199         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 200
 201         samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
 202 }
 203
 204 static __init int s3c64xx_dev_init(void)
 205 {
 206         subsys_system_register(&s3c64xx_subsys, NULL);
 207         return device_register(&s3c64xx_dev);
 208 }
 209 core_initcall(s3c64xx_dev_init);
 210
 211 /*
 212  * setup the sources the vic should advertise resume
 213  * for, even though it is not doing the wake
 214  * (set_irq_wake needs to be valid)
 215  */
 216 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
 217 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
 218                          1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
 219                          1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
 220                          1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
 221                          1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
 222
 223 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 224 {
 225         /*
 226          * FIXME: there is no better place to put this at the moment
 227          * (s3c64xx_clk_init needs ioremap and must happen before init_time
 228          * samsung_wdt_reset_init needs clocks)
 229          */
 230         s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
 231         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 232
 233         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 234
 235         /* initialise the pair of VICs */
 236         vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
 237         vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
 238 }
 239
 240 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 241 #define eint_irq_to_bit(irq)    ((u32)(1 << eint_offset(irq)))
 242
 243 static inline void s3c_irq_eint_mask(struct irq_data *data)
 244 {
 245         u32 mask;
 246
 247         mask = __raw_readl(S3C64XX_EINT0MASK);
 248         mask |= (u32)data->chip_data;
 249         __raw_writel(mask, S3C64XX_EINT0MASK);
 250 }
 251
 252 static void s3c_irq_eint_unmask(struct irq_data *data)
 253 {
 254         u32 mask;
 255
 256         mask = __raw_readl(S3C64XX_EINT0MASK);
 257         mask &= ~((u32)data->chip_data);
 258         __raw_writel(mask, S3C64XX_EINT0MASK);
 259 }
 260
 261 static inline void s3c_irq_eint_ack(struct irq_data *data)
 262 {
 263         __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
 264 }
 265
 266 static void s3c_irq_eint_maskack(struct irq_data *data)
 267 {
 268         /* compiler should in-line these */
 269         s3c_irq_eint_mask(data);
 270         s3c_irq_eint_ack(data);
 271 }
 272
 273 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
 274 {
 275         int offs = eint_offset(data->irq);
 276         int pin, pin_val;
 277         int shift;
 278         u32 ctrl, mask;
 279         u32 newvalue = 0;
 280         void __iomem *reg;
 281
 282         if (offs > 27)
 283                 return -EINVAL;
 284
 285         if (offs <= 15)
 286                 reg = S3C64XX_EINT0CON0;
 287         else
 288                 reg = S3C64XX_EINT0CON1;
 289
 290         switch (type) {
 291         case IRQ_TYPE_NONE:
 292                 printk(KERN_WARNING "No edge setting!\n");
 293                 break;
 294
 295         case IRQ_TYPE_EDGE_RISING:
 296                 newvalue = S3C2410_EXTINT_RISEEDGE;
 297                 break;
 298
 299         case IRQ_TYPE_EDGE_FALLING:
 300                 newvalue = S3C2410_EXTINT_FALLEDGE;
 301                 break;
 302
 303         case IRQ_TYPE_EDGE_BOTH:
 304                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 305                 break;
 306
 307         case IRQ_TYPE_LEVEL_LOW:
 308                 newvalue = S3C2410_EXTINT_LOWLEV;
 309                 break;
 310
 311         case IRQ_TYPE_LEVEL_HIGH:
 312                 newvalue = S3C2410_EXTINT_HILEV;
 313                 break;
 314
 315         default:
 316                 printk(KERN_ERR "No such irq type %d", type);
 317                 return -1;
 318         }
 319
 320         if (offs <= 15)
 321                 shift = (offs / 2) * 4;
 322         else
 323                 shift = ((offs - 16) / 2) * 4;
 324         mask = 0x7 << shift;
 325
 326         ctrl = __raw_readl(reg);
 327         ctrl &= ~mask;
 328         ctrl |= newvalue << shift;
 329         __raw_writel(ctrl, reg);
 330
 331         /* set the GPIO pin appropriately */
 332
 333         if (offs < 16) {
 334                 pin = S3C64XX_GPN(offs);
 335                 pin_val = S3C_GPIO_SFN(2);
 336         } else if (offs < 23) {
 337                 pin = S3C64XX_GPL(offs + 8 - 16);
 338                 pin_val = S3C_GPIO_SFN(3);
 339         } else {
 340                 pin = S3C64XX_GPM(offs - 23);
 341                 pin_val = S3C_GPIO_SFN(3);
 342         }
 343
 344         s3c_gpio_cfgpin(pin, pin_val);
 345
 346         return 0;
 347 }
 348
 349 static struct irq_chip s3c_irq_eint = {
 350         .name           = "s3c-eint",
 351         .irq_mask       = s3c_irq_eint_mask,
 352         .irq_unmask     = s3c_irq_eint_unmask,
 353         .irq_mask_ack   = s3c_irq_eint_maskack,
 354         .irq_ack        = s3c_irq_eint_ack,
 355         .irq_set_type   = s3c_irq_eint_set_type,
 356         .irq_set_wake   = s3c_irqext_wake,
 357 };
 358
 359 /* s3c_irq_demux_eint
 360  *
 361  * This function demuxes the IRQ from the group0 external interrupts,
 362  * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 363  * the specific handlers s3c_irq_demux_eintX_Y.
 364  */
 365 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
 366 {
 367         u32 status = __raw_readl(S3C64XX_EINT0PEND);
 368         u32 mask = __raw_readl(S3C64XX_EINT0MASK);
 369         unsigned int irq;
 370
 371         status &= ~mask;
 372         status >>= start;
 373         status &= (1 << (end - start + 1)) - 1;
 374
 375         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 376                 if (status & 1)
 377                         generic_handle_irq(irq);
 378
 379                 status >>= 1;
 380         }
 381 }
 382
 383 static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 384 {
 385         s3c_irq_demux_eint(0, 3);
 386 }
 387
 388 static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 389 {
 390         s3c_irq_demux_eint(4, 11);
 391 }
 392
 393 static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
 394 {
 395         s3c_irq_demux_eint(12, 19);
 396 }
 397
 398 static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
 399 {
 400         s3c_irq_demux_eint(20, 27);
 401 }
 402
 403 static int __init s3c64xx_init_irq_eint(void)
 404 {
 405         int irq;
 406
 407         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
 408                 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
 409                 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
 410                 set_irq_flags(irq, IRQF_VALID);
 411         }
 412
 413         irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
 414         irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
 415         irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
 416         irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
 417
 418         return 0;
 419 }
 420 arch_initcall(s3c64xx_init_irq_eint);
 421
 422 void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
 423 {
 424         if (mode != REBOOT_SOFT)
 425                 samsung_wdt_reset();
 426
 427         /* if all else fails, or mode was for soft, jump to 0 */
 428         soft_restart(0);
 429 }
 430
 431 void __init s3c64xx_init_late(void)
 432 {
 433         s3c64xx_pm_late_initcall();
 434 }