arch/arm/mach-s3c64xx/dev-spi.c

   1 /* linux/arch/arm/plat-s3c64xx/dev-spi.c
   2  *
   3  * Copyright (C) 2009 Samsung Electronics Ltd.
   4  *      Jaswinder Singh <jassi.brar@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/string.h>
  13 #include <linux/export.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/gpio.h>
  17
  18 #include <mach/dma.h>
  19 #include <mach/map.h>
  20 #include <mach/spi-clocks.h>
  21 #include <mach/irqs.h>
  22
  23 #include <plat/s3c64xx-spi.h>
  24 #include <plat/gpio-cfg.h>
  25 #include <plat/devs.h>
  26
  27 /* SPI Controller platform_devices */
  28
  29 /* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
  30  * The emulated CS is toggled by board specific mechanism, as it can
  31  * be either some immediate GPIO or some signal out of some other
  32  * chip in between ... or some yet another way.
  33  * We simply do not assume anything about CS.
  34  */
  35 static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
  36 {
  37         unsigned int base;
  38
  39         switch (pdev->id) {
  40         case 0:
  41                 base = S3C64XX_GPC(0);
  42                 break;
  43
  44         case 1:
  45                 base = S3C64XX_GPC(4);
  46                 break;
  47
  48         default:
  49                 dev_err(&pdev->dev, "Invalid SPI Controller number!");
  50                 return -EINVAL;
  51         }
  52
  53         s3c_gpio_cfgall_range(base, 3,
  54                               S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  55
  56         return 0;
  57 }
  58
  59 static struct resource s3c64xx_spi0_resource[] = {
  60         [0] = {
  61                 .start = S3C64XX_PA_SPI0,
  62                 .end   = S3C64XX_PA_SPI0 + 0x100 - 1,
  63                 .flags = IORESOURCE_MEM,
  64         },
  65         [1] = {
  66                 .start = DMACH_SPI0_TX,
  67                 .end   = DMACH_SPI0_TX,
  68                 .flags = IORESOURCE_DMA,
  69         },
  70         [2] = {
  71                 .start = DMACH_SPI0_RX,
  72                 .end   = DMACH_SPI0_RX,
  73                 .flags = IORESOURCE_DMA,
  74         },
  75         [3] = {
  76                 .start = IRQ_SPI0,
  77                 .end   = IRQ_SPI0,
  78                 .flags = IORESOURCE_IRQ,
  79         },
  80 };
  81
  82 static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
  83         .cfg_gpio = s3c64xx_spi_cfg_gpio,
  84         .fifo_lvl_mask = 0x7f,
  85         .rx_lvl_offset = 13,
  86         .tx_st_done = 21,
  87 };
  88
  89 static u64 spi_dmamask = DMA_BIT_MASK(32);
  90
  91 struct platform_device s3c64xx_device_spi0 = {
  92         .name             = "s3c64xx-spi",
  93         .id               = 0,
  94         .num_resources    = ARRAY_SIZE(s3c64xx_spi0_resource),
  95         .resource         = s3c64xx_spi0_resource,
  96         .dev = {
  97                 .dma_mask               = &spi_dmamask,
  98                 .coherent_dma_mask      = DMA_BIT_MASK(32),
  99                 .platform_data = &s3c64xx_spi0_pdata,
 100         },
 101 };
 102 EXPORT_SYMBOL(s3c64xx_device_spi0);
 103
 104 static struct resource s3c64xx_spi1_resource[] = {
 105         [0] = {
 106                 .start = S3C64XX_PA_SPI1,
 107                 .end   = S3C64XX_PA_SPI1 + 0x100 - 1,
 108                 .flags = IORESOURCE_MEM,
 109         },
 110         [1] = {
 111                 .start = DMACH_SPI1_TX,
 112                 .end   = DMACH_SPI1_TX,
 113                 .flags = IORESOURCE_DMA,
 114         },
 115         [2] = {
 116                 .start = DMACH_SPI1_RX,
 117                 .end   = DMACH_SPI1_RX,
 118                 .flags = IORESOURCE_DMA,
 119         },
 120         [3] = {
 121                 .start = IRQ_SPI1,
 122                 .end   = IRQ_SPI1,
 123                 .flags = IORESOURCE_IRQ,
 124         },
 125 };
 126
 127 static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
 128         .cfg_gpio = s3c64xx_spi_cfg_gpio,
 129         .fifo_lvl_mask = 0x7f,
 130         .rx_lvl_offset = 13,
 131         .tx_st_done = 21,
 132 };
 133
 134 struct platform_device s3c64xx_device_spi1 = {
 135         .name             = "s3c64xx-spi",
 136         .id               = 1,
 137         .num_resources    = ARRAY_SIZE(s3c64xx_spi1_resource),
 138         .resource         = s3c64xx_spi1_resource,
 139         .dev = {
 140                 .dma_mask               = &spi_dmamask,
 141                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 142                 .platform_data = &s3c64xx_spi1_pdata,
 143         },
 144 };
 145 EXPORT_SYMBOL(s3c64xx_device_spi1);
 146
 147 void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 148 {
 149         struct s3c64xx_spi_info *pd;
 150
 151         /* Reject invalid configuration */
 152         if (!num_cs || src_clk_nr < 0
 153                         || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
 154                 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
 155                 return;
 156         }
 157
 158         switch (cntrlr) {
 159         case 0:
 160                 pd = &s3c64xx_spi0_pdata;
 161                 break;
 162         case 1:
 163                 pd = &s3c64xx_spi1_pdata;
 164                 break;
 165         default:
 166                 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
 167                                                         __func__, cntrlr);
 168                 return;
 169         }
 170
 171         pd->num_cs = num_cs;
 172         pd->src_clk_nr = src_clk_nr;
 173 }