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1 /*
2  * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3  *              http://www.samsung.com
4  *
5  * Common Codes for S5P64X0 machines
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/device.h>
21 #include <linux/serial_core.h>
22 #include <clocksource/samsung_pwm.h>
23 #include <linux/platform_device.h>
24 #include <linux/sched.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/gpio.h>
27 #include <linux/irq.h>
28 #include <linux/reboot.h>
29
30 #include <asm/irq.h>
31 #include <asm/proc-fns.h>
32 #include <asm/system_misc.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/irq.h>
36
37 #include <mach/map.h>
38 #include <mach/hardware.h>
39 #include <mach/regs-clock.h>
40 #include <mach/regs-gpio.h>
41
42 #include <plat/cpu.h>
43 #include <plat/clock.h>
44 #include <plat/devs.h>
45 #include <plat/pm.h>
46 #include <plat/sdhci.h>
47 #include <plat/adc-core.h>
48 #include <plat/fb-core.h>
49 #include <plat/spi-core.h>
50 #include <plat/gpio-cfg.h>
51 #include <plat/pwm-core.h>
52 #include <plat/regs-irqtype.h>
53 #include <plat/regs-serial.h>
54 #include <plat/watchdog-reset.h>
55
56 #include "common.h"
57
58 static const char name_s5p6440[] = "S5P6440";
59 static const char name_s5p6450[] = "S5P6450";
60
61 static struct cpu_table cpu_ids[] __initdata = {
62         {
63                 .idcode         = S5P6440_CPU_ID,
64                 .idmask         = S5P64XX_CPU_MASK,
65                 .map_io         = s5p6440_map_io,
66                 .init_clocks    = s5p6440_init_clocks,
67                 .init_uarts     = s5p6440_init_uarts,
68                 .init           = s5p64x0_init,
69                 .name           = name_s5p6440,
70         }, {
71                 .idcode         = S5P6450_CPU_ID,
72                 .idmask         = S5P64XX_CPU_MASK,
73                 .map_io         = s5p6450_map_io,
74                 .init_clocks    = s5p6450_init_clocks,
75                 .init_uarts     = s5p6450_init_uarts,
76                 .init           = s5p64x0_init,
77                 .name           = name_s5p6450,
78         },
79 };
80
81 /* Initial IO mappings */
82
83 static struct map_desc s5p64x0_iodesc[] __initdata = {
84         {
85                 .virtual        = (unsigned long)S5P_VA_CHIPID,
86                 .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
87                 .length         = SZ_4K,
88                 .type           = MT_DEVICE,
89         }, {
90                 .virtual        = (unsigned long)S3C_VA_SYS,
91                 .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
92                 .length         = SZ_64K,
93                 .type           = MT_DEVICE,
94         }, {
95                 .virtual        = (unsigned long)S3C_VA_TIMER,
96                 .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
97                 .length         = SZ_16K,
98                 .type           = MT_DEVICE,
99         }, {
100                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
101                 .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
102                 .length         = SZ_4K,
103                 .type           = MT_DEVICE,
104         }, {
105                 .virtual        = (unsigned long)S5P_VA_SROMC,
106                 .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
107                 .length         = SZ_4K,
108                 .type           = MT_DEVICE,
109         }, {
110                 .virtual        = (unsigned long)S5P_VA_GPIO,
111                 .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
112                 .length         = SZ_4K,
113                 .type           = MT_DEVICE,
114         }, {
115                 .virtual        = (unsigned long)VA_VIC0,
116                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
117                 .length         = SZ_16K,
118                 .type           = MT_DEVICE,
119         }, {
120                 .virtual        = (unsigned long)VA_VIC1,
121                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
122                 .length         = SZ_16K,
123                 .type           = MT_DEVICE,
124         },
125 };
126
127 static struct map_desc s5p6440_iodesc[] __initdata = {
128         {
129                 .virtual        = (unsigned long)S3C_VA_UART,
130                 .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
131                 .length         = SZ_4K,
132                 .type           = MT_DEVICE,
133         },
134 };
135
136 static struct map_desc s5p6450_iodesc[] __initdata = {
137         {
138                 .virtual        = (unsigned long)S3C_VA_UART,
139                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
140                 .length         = SZ_512K,
141                 .type           = MT_DEVICE,
142         }, {
143                 .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
144                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
145                 .length         = SZ_4K,
146                 .type           = MT_DEVICE,
147         },
148 };
149
150 static void s5p64x0_idle(void)
151 {
152         unsigned long val;
153
154         val = __raw_readl(S5P64X0_PWR_CFG);
155         val &= ~(0x3 << 5);
156         val |= (0x1 << 5);
157         __raw_writel(val, S5P64X0_PWR_CFG);
158
159         cpu_do_idle();
160 }
161
162 static struct samsung_pwm_variant s5p64x0_pwm_variant = {
163         .bits           = 32,
164         .div_base       = 0,
165         .has_tint_cstat = true,
166         .tclk_mask      = 0,
167 };
168
169 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
170 {
171         s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
172         s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
173 }
174
175 void __init samsung_timer_init(void)
176 {
177         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
178                 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
179                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
180         };
181
182         samsung_pwm_clocksource_init(S3C_VA_TIMER,
183                                         timer_irqs, &s5p64x0_pwm_variant);
184 }
185
186 /*
187  * s5p64x0_map_io
188  *
189  * register the standard CPU IO areas
190  */
191
192 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
193 {
194         /* initialize the io descriptors we need for initialization */
195         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
196         if (mach_desc)
197                 iotable_init(mach_desc, size);
198
199         /* detect cpu id and rev. */
200         s5p_init_cpu(S5P64X0_SYS_ID);
201
202         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
203         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
204
205         samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
206 }
207
208 void __init s5p6440_map_io(void)
209 {
210         /* initialize any device information early */
211         s3c_adc_setname("s3c64xx-adc");
212         s3c_fb_setname("s5p64x0-fb");
213         s3c64xx_spi_setname("s5p64x0-spi");
214
215         s5p64x0_default_sdhci0();
216         s5p64x0_default_sdhci1();
217         s5p6440_default_sdhci2();
218
219         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
220 }
221
222 void __init s5p6450_map_io(void)
223 {
224         /* initialize any device information early */
225         s3c_adc_setname("s3c64xx-adc");
226         s3c_fb_setname("s5p64x0-fb");
227         s3c64xx_spi_setname("s5p64x0-spi");
228
229         s5p64x0_default_sdhci0();
230         s5p64x0_default_sdhci1();
231         s5p6450_default_sdhci2();
232
233         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
234 }
235
236 /*
237  * s5p64x0_init_clocks
238  *
239  * register and setup the CPU clocks
240  */
241
242 void __init s5p6440_init_clocks(int xtal)
243 {
244         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
245
246         s3c24xx_register_baseclocks(xtal);
247         s5p_register_clocks(xtal);
248         s5p6440_register_clocks();
249         s5p6440_setup_clocks();
250 }
251
252 void __init s5p6450_init_clocks(int xtal)
253 {
254         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
255
256         s3c24xx_register_baseclocks(xtal);
257         s5p_register_clocks(xtal);
258         s5p6450_register_clocks();
259         s5p6450_setup_clocks();
260 }
261
262 /*
263  * s5p64x0_init_irq
264  *
265  * register the CPU interrupts
266  */
267
268 void __init s5p6440_init_irq(void)
269 {
270         /* S5P6440 supports 2 VIC */
271         u32 vic[2];
272
273         /*
274          * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
275          * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
276          */
277         vic[0] = 0xff800ae7;
278         vic[1] = 0xffbf23e5;
279
280         s5p_init_irq(vic, ARRAY_SIZE(vic));
281 }
282
283 void __init s5p6450_init_irq(void)
284 {
285         /* S5P6450 supports only 2 VIC */
286         u32 vic[2];
287
288         /*
289          * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
290          * VIC1 is missing IRQ VIC1[12, 14, 23]
291          */
292         vic[0] = 0xff9f1fff;
293         vic[1] = 0xff7fafff;
294
295         s5p_init_irq(vic, ARRAY_SIZE(vic));
296 }
297
298 struct bus_type s5p64x0_subsys = {
299         .name           = "s5p64x0-core",
300         .dev_name       = "s5p64x0-core",
301 };
302
303 static struct device s5p64x0_dev = {
304         .bus    = &s5p64x0_subsys,
305 };
306
307 static int __init s5p64x0_core_init(void)
308 {
309         return subsys_system_register(&s5p64x0_subsys, NULL);
310 }
311 core_initcall(s5p64x0_core_init);
312
313 int __init s5p64x0_init(void)
314 {
315         printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
316
317         /* set idle function */
318         arm_pm_idle = s5p64x0_idle;
319
320         return device_register(&s5p64x0_dev);
321 }
322
323 /* uart registration process */
324 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
325 {
326         int uart;
327
328         for (uart = 0; uart < no; uart++) {
329                 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
330                 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
331         }
332
333         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
334 }
335
336 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
337 {
338         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
339 }
340
341 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
342
343 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
344 {
345         int offs = eint_offset(data->irq);
346         int shift;
347         u32 ctrl, mask;
348         u32 newvalue = 0;
349
350         if (offs > 15)
351                 return -EINVAL;
352
353         switch (type) {
354         case IRQ_TYPE_NONE:
355                 printk(KERN_WARNING "No edge setting!\n");
356                 break;
357         case IRQ_TYPE_EDGE_RISING:
358                 newvalue = S3C2410_EXTINT_RISEEDGE;
359                 break;
360         case IRQ_TYPE_EDGE_FALLING:
361                 newvalue = S3C2410_EXTINT_FALLEDGE;
362                 break;
363         case IRQ_TYPE_EDGE_BOTH:
364                 newvalue = S3C2410_EXTINT_BOTHEDGE;
365                 break;
366         case IRQ_TYPE_LEVEL_LOW:
367                 newvalue = S3C2410_EXTINT_LOWLEV;
368                 break;
369         case IRQ_TYPE_LEVEL_HIGH:
370                 newvalue = S3C2410_EXTINT_HILEV;
371                 break;
372         default:
373                 printk(KERN_ERR "No such irq type %d", type);
374                 return -EINVAL;
375         }
376
377         shift = (offs / 2) * 4;
378         mask = 0x7 << shift;
379
380         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
381         ctrl |= newvalue << shift;
382         __raw_writel(ctrl, S5P64X0_EINT0CON0);
383
384         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
385         if (soc_is_s5p6450())
386                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
387         else
388                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
389
390         return 0;
391 }
392
393 /*
394  * s5p64x0_irq_demux_eint
395  *
396  * This function demuxes the IRQ from the group0 external interrupts,
397  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
398  * the specific handlers s5p64x0_irq_demux_eintX_Y.
399  */
400 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
401 {
402         u32 status = __raw_readl(S5P64X0_EINT0PEND);
403         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
404         unsigned int irq;
405
406         status &= ~mask;
407         status >>= start;
408         status &= (1 << (end - start + 1)) - 1;
409
410         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
411                 if (status & 1)
412                         generic_handle_irq(irq);
413                 status >>= 1;
414         }
415 }
416
417 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
418 {
419         s5p64x0_irq_demux_eint(0, 3);
420 }
421
422 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
423 {
424         s5p64x0_irq_demux_eint(4, 11);
425 }
426
427 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
428                                         struct irq_desc *desc)
429 {
430         s5p64x0_irq_demux_eint(12, 15);
431 }
432
433 static int s5p64x0_alloc_gc(void)
434 {
435         struct irq_chip_generic *gc;
436         struct irq_chip_type *ct;
437
438         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
439                                     S5P_VA_GPIO, handle_level_irq);
440         if (!gc) {
441                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
442                         "external interrupts failed\n", __func__);
443                 return -EINVAL;
444         }
445
446         ct = gc->chip_types;
447         ct->chip.irq_ack = irq_gc_ack_set_bit;
448         ct->chip.irq_mask = irq_gc_mask_set_bit;
449         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
450         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
451         ct->chip.irq_set_wake = s3c_irqext_wake;
452         ct->regs.ack = EINT0PEND_OFFSET;
453         ct->regs.mask = EINT0MASK_OFFSET;
454         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
455                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
456         return 0;
457 }
458
459 static int __init s5p64x0_init_irq_eint(void)
460 {
461         int ret = s5p64x0_alloc_gc();
462         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
463         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
464         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
465
466         return ret;
467 }
468 arch_initcall(s5p64x0_init_irq_eint);
469
470 void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
471 {
472         if (mode != REBOOT_SOFT)
473                 samsung_wdt_reset();
474
475         soft_restart(0);
476 }