1 /* linux/arch/arm/mach-s5p64x0/dev-spi.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
20 #include <mach/irqs.h>
21 #include <mach/regs-clock.h>
22 #include <mach/spi-clocks.h>
25 #include <plat/s3c64xx-spi.h>
26 #include <plat/gpio-cfg.h>
28 /* SPI Controller platform_devices */
30 /* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
36 static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
42 base = S5P6440_GPC(0);
46 base = S5P6440_GPC(4);
50 dev_err(&pdev->dev, "Invalid SPI Controller number!");
54 s3c_gpio_cfgall_range(base, 3,
55 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
60 static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
66 base = S5P6450_GPC(0);
70 base = S5P6450_GPC(4);
74 dev_err(&pdev->dev, "Invalid SPI Controller number!");
78 s3c_gpio_cfgall_range(base, 3,
79 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
84 static struct resource s5p64x0_spi0_resource[] = {
86 .start = S5P64X0_PA_SPI0,
87 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
88 .flags = IORESOURCE_MEM,
91 .start = DMACH_SPI0_TX,
93 .flags = IORESOURCE_DMA,
96 .start = DMACH_SPI0_RX,
98 .flags = IORESOURCE_DMA,
103 .flags = IORESOURCE_IRQ,
107 static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
108 .cfg_gpio = s5p6440_spi_cfg_gpio,
109 .fifo_lvl_mask = 0x1ff,
114 static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
115 .cfg_gpio = s5p6450_spi_cfg_gpio,
116 .fifo_lvl_mask = 0x1ff,
121 static u64 spi_dmamask = DMA_BIT_MASK(32);
123 struct platform_device s5p64x0_device_spi0 = {
124 .name = "s3c64xx-spi",
126 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
127 .resource = s5p64x0_spi0_resource,
129 .dma_mask = &spi_dmamask,
130 .coherent_dma_mask = DMA_BIT_MASK(32),
134 static struct resource s5p64x0_spi1_resource[] = {
136 .start = S5P64X0_PA_SPI1,
137 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
138 .flags = IORESOURCE_MEM,
141 .start = DMACH_SPI1_TX,
142 .end = DMACH_SPI1_TX,
143 .flags = IORESOURCE_DMA,
146 .start = DMACH_SPI1_RX,
147 .end = DMACH_SPI1_RX,
148 .flags = IORESOURCE_DMA,
153 .flags = IORESOURCE_IRQ,
157 static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
158 .cfg_gpio = s5p6440_spi_cfg_gpio,
159 .fifo_lvl_mask = 0x7f,
164 static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
165 .cfg_gpio = s5p6450_spi_cfg_gpio,
166 .fifo_lvl_mask = 0x7f,
171 struct platform_device s5p64x0_device_spi1 = {
172 .name = "s3c64xx-spi",
174 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
175 .resource = s5p64x0_spi1_resource,
177 .dma_mask = &spi_dmamask,
178 .coherent_dma_mask = DMA_BIT_MASK(32),
182 void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
184 struct s3c64xx_spi_info *pd;
186 /* Reject invalid configuration */
187 if (!num_cs || src_clk_nr < 0
188 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
189 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
195 if (soc_is_s5p6450())
196 pd = &s5p6450_spi0_pdata;
198 pd = &s5p6440_spi0_pdata;
200 s5p64x0_device_spi0.dev.platform_data = pd;
203 if (soc_is_s5p6450())
204 pd = &s5p6450_spi1_pdata;
206 pd = &s5p6440_spi1_pdata;
208 s5p64x0_device_spi1.dev.platform_data = pd;
211 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
217 pd->src_clk_nr = src_clk_nr;