arch/arm/mach-socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <altera.h>
  10 #include <miiphy.h>
  11 #include <netdev.h>
  12 #include <watchdog.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <asm/arch/system_manager.h>
  15 #include <asm/arch/dwmmc.h>
  16 #include <asm/arch/nic301.h>
  17 #include <asm/arch/scu.h>
  18 #include <asm/pl310.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 static struct pl310_regs *const pl310 =
  23         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  24 static struct socfpga_system_manager *sysmgr_regs =
  25         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  26 static struct socfpga_reset_manager *reset_manager_base =
  27         (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
  28 static struct nic301_registers *nic301_regs =
  29         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  30 static struct scu_registers *scu_regs =
  31         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  32
  33 int dram_init(void)
  34 {
  35         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  36         return 0;
  37 }
  38
  39 void enable_caches(void)
  40 {
  41 #ifndef CONFIG_SYS_ICACHE_OFF
  42         icache_enable();
  43 #endif
  44 #ifndef CONFIG_SYS_DCACHE_OFF
  45         dcache_enable();
  46 #endif
  47 }
  48
  49 /*
  50  * DesignWare Ethernet initialization
  51  */
  52 #ifdef CONFIG_ETH_DESIGNWARE
  53 int cpu_eth_init(bd_t *bis)
  54 {
  55 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
  56         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  57         const u32 reset = SOCFPGA_RESET(EMAC0);
  58 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
  59         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  60         const u32 reset = SOCFPGA_RESET(EMAC1);
  61 #else
  62 #error "Incorrect CONFIG_EMAC_BASE value!"
  63 #endif
  64
  65         /* Initialize EMAC. This needs to be done at least once per boot. */
  66
  67         /*
  68          * Putting the EMAC controller to reset when configuring the PHY
  69          * interface select at System Manager
  70          */
  71         socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
  72         socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
  73
  74         /* Clearing emac0 PHY interface select to 0 */
  75         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  76                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  77
  78         /* configure to PHY interface select choosed */
  79         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
  80                      SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
  81
  82         /* Release the EMAC controller from reset */
  83         socfpga_per_reset(reset, 0);
  84
  85         /* initialize and register the emac */
  86         return designware_initialize(CONFIG_EMAC_BASE,
  87                                      CONFIG_PHY_INTERFACE_MODE);
  88 }
  89 #endif
  90
  91 #ifdef CONFIG_DWMMC
  92 /*
  93  * Initializes MMC controllers.
  94  * to override, implement board_mmc_init()
  95  */
  96 int cpu_mmc_init(bd_t *bis)
  97 {
  98         return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
  99                                   CONFIG_HPS_SDMMC_BUSWIDTH, 0);
 100 }
 101 #endif
 102
 103 #if defined(CONFIG_DISPLAY_CPUINFO)
 104 /*
 105  * Print CPU information
 106  */
 107 int print_cpuinfo(void)
 108 {
 109         puts("CPU:   Altera SoCFPGA Platform\n");
 110         return 0;
 111 }
 112 #endif
 113
 114 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 115 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 116 int overwrite_console(void)
 117 {
 118         return 0;
 119 }
 120 #endif
 121
 122 #ifdef CONFIG_FPGA
 123 /*
 124  * FPGA programming support for SoC FPGA Cyclone V
 125  */
 126 static Altera_desc altera_fpga[] = {
 127         {
 128                 /* Family */
 129                 Altera_SoCFPGA,
 130                 /* Interface type */
 131                 fast_passive_parallel,
 132                 /* No limitation as additional data will be ignored */
 133                 -1,
 134                 /* No device function table */
 135                 NULL,
 136                 /* Base interface address specified in driver */
 137                 NULL,
 138                 /* No cookie implementation */
 139                 0
 140         },
 141 };
 142
 143 /* add device descriptor to FPGA device table */
 144 static void socfpga_fpga_add(void)
 145 {
 146         int i;
 147         fpga_init();
 148         for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
 149                 fpga_add(fpga_altera, &altera_fpga[i]);
 150 }
 151 #else
 152 static inline void socfpga_fpga_add(void) {}
 153 #endif
 154
 155 int arch_cpu_init(void)
 156 {
 157 #ifdef CONFIG_HW_WATCHDOG
 158         /*
 159          * In case the watchdog is enabled, make sure to (re-)configure it
 160          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 161          * timeout value is still active which might too short for Linux
 162          * booting.
 163          */
 164         hw_watchdog_init();
 165 #else
 166         /*
 167          * If the HW watchdog is NOT enabled, make sure it is not running,
 168          * for example because it was enabled in the preloader. This might
 169          * trigger a watchdog-triggered reboot of Linux kernel later.
 170          * Toggle watchdog reset, so watchdog in not running state.
 171          */
 172         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 173         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 174 #endif
 175
 176         return 0;
 177 }
 178
 179 /*
 180  * Convert all NIC-301 AMBA slaves from secure to non-secure
 181  */
 182 static void socfpga_nic301_slave_ns(void)
 183 {
 184         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 185         writel(0x1, &nic301_regs->hps2fpgaregs);
 186         writel(0x1, &nic301_regs->acp);
 187         writel(0x1, &nic301_regs->rom);
 188         writel(0x1, &nic301_regs->ocram);
 189         writel(0x1, &nic301_regs->sdrdata);
 190 }
 191
 192 static uint32_t iswgrp_handoff[8];
 193
 194 int arch_early_init_r(void)
 195 {
 196         int i;
 197         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 198                 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 199
 200         socfpga_bridges_reset(1);
 201         socfpga_nic301_slave_ns();
 202
 203         /*
 204          * Private components security:
 205          * U-Boot : configure private timer, global timer and cpu component
 206          * access as non secure for kernel stage (as required by Linux)
 207          */
 208         setbits_le32(&scu_regs->sacr, 0xfff);
 209
 210         /* Configure the L2 controller to make SDRAM start at 0 */
 211 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 212         writel(0x2, &nic301_regs->remap);
 213 #else
 214         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 215         writel(0x1, &pl310->pl310_addr_filter_start);
 216 #endif
 217
 218         /* Add device descriptor to FPGA device table */
 219         socfpga_fpga_add();
 220
 221 #ifdef CONFIG_DESIGNWARE_SPI
 222         /* Get Designware SPI controller out of reset */
 223         socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
 224         socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 225 #endif
 226
 227         return 0;
 228 }
 229
 230 static void socfpga_sdram_apply_static_cfg(void)
 231 {
 232         const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
 233         const uint32_t applymask = 0x8;
 234         uint32_t val = readl(staticcfg) | applymask;
 235
 236         /*
 237          * SDRAM staticcfg register specific:
 238          * When applying the register setting, the CPU must not access
 239          * SDRAM. Luckily for us, we can abuse i-cache here to help us
 240          * circumvent the SDRAM access issue. The idea is to make sure
 241          * that the code is in one full i-cache line by branching past
 242          * it and back. Once it is in the i-cache, we execute the core
 243          * of the code and apply the register settings.
 244          *
 245          * The code below uses 7 instructions, while the Cortex-A9 has
 246          * 32-byte cachelines, thus the limit is 8 instructions total.
 247          */
 248         asm volatile(
 249                 ".align 5                       \n"
 250                 "       b       2f              \n"
 251                 "1:     str     %0,     [%1]    \n"
 252                 "       dsb                     \n"
 253                 "       isb                     \n"
 254                 "       b       3f              \n"
 255                 "2:     b       1b              \n"
 256                 "3:     nop                     \n"
 257         : : "r"(val), "r"(staticcfg) : "memory", "cc");
 258 }
 259
 260 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 261 {
 262         if (argc != 2)
 263                 return CMD_RET_USAGE;
 264
 265         argv++;
 266
 267         switch (*argv[0]) {
 268         case 'e':       /* Enable */
 269                 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 270                 socfpga_sdram_apply_static_cfg();
 271                 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
 272                 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 273                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 274                 break;
 275         case 'd':       /* Disable */
 276                 writel(0, &sysmgr_regs->fpgaintfgrp_module);
 277                 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
 278                 socfpga_sdram_apply_static_cfg();
 279                 writel(0, &reset_manager_base->brg_mod_reset);
 280                 writel(1, &nic301_regs->remap);
 281                 break;
 282         default:
 283                 return CMD_RET_USAGE;
 284         }
 285
 286         return 0;
 287 }
 288
 289 U_BOOT_CMD(
 290         bridge, 2, 1, do_bridge,
 291         "SoCFPGA HPS FPGA bridge control",
 292         "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 293         "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 294         ""
 295 );