arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2012 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/mmci.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/gpio.h>
  25 #include <linux/clk.h>
  26 #include <linux/err.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/fsmc.h>
  29 #include <linux/pinctrl/machine.h>
  30 #include <linux/pinctrl/consumer.h>
  31 #include <linux/pinctrl/pinconf-generic.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/platform_data/clk-u300.h>
  34 #include <linux/platform_data/pinctrl-coh901.h>
  35
  36 #include <asm/types.h>
  37 #include <asm/setup.h>
  38 #include <asm/memory.h>
  39 #include <asm/hardware/vic.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach-types.h>
  42 #include <asm/mach/arch.h>
  43
  44 #include <mach/coh901318.h>
  45 #include <mach/hardware.h>
  46 #include <mach/syscon.h>
  47 #include <mach/irqs.h>
  48
  49 #include "timer.h"
  50 #include "spi.h"
  51 #include "i2c.h"
  52 #include "u300-gpio.h"
  53 #include "dma_channels.h"
  54
  55 /*
  56  * Static I/O mappings that are needed for booting the U300 platforms. The
  57  * only things we need are the areas where we find the timer, syscon and
  58  * intcon, since the remaining device drivers will map their own memory
  59  * physical to virtual as the need arise.
  60  */
  61 static struct map_desc u300_io_desc[] __initdata = {
  62         {
  63                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  64                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  65                 .length         = SZ_64K,
  66                 .type           = MT_DEVICE,
  67         },
  68         {
  69                 .virtual        = U300_AHB_PER_VIRT_BASE,
  70                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  71                 .length         = SZ_32K,
  72                 .type           = MT_DEVICE,
  73         },
  74         {
  75                 .virtual        = U300_FAST_PER_VIRT_BASE,
  76                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  77                 .length         = SZ_32K,
  78                 .type           = MT_DEVICE,
  79         },
  80 };
  81
  82 static void __init u300_map_io(void)
  83 {
  84         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  85         /* We enable a real big DMA buffer if need be. */
  86         init_consistent_dma_size(SZ_4M);
  87 }
  88
  89 /*
  90  * Declaration of devices found on the U300 board and
  91  * their respective memory locations.
  92  */
  93
  94 static struct amba_pl011_data uart0_plat_data = {
  95 #ifdef CONFIG_COH901318
  96         .dma_filter = coh901318_filter_id,
  97         .dma_rx_param = (void *) U300_DMA_UART0_RX,
  98         .dma_tx_param = (void *) U300_DMA_UART0_TX,
  99 #endif
 100 };
 101
 102 /* Slow device at 0x3000 offset */
 103 static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
 104         { IRQ_U300_UART0 }, &uart0_plat_data);
 105
 106 /* The U335 have an additional UART1 on the APP CPU */
 107 static struct amba_pl011_data uart1_plat_data = {
 108 #ifdef CONFIG_COH901318
 109         .dma_filter = coh901318_filter_id,
 110         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 111         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 112 #endif
 113 };
 114
 115 /* Fast device at 0x7000 offset */
 116 static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
 117         { IRQ_U300_UART1 }, &uart1_plat_data);
 118
 119 /* AHB device at 0x4000 offset */
 120 static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
 121
 122 /* Fast device at 0x6000 offset */
 123 static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
 124         { IRQ_U300_SPI }, NULL);
 125
 126 /* Fast device at 0x1000 offset */
 127 #define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 128
 129 static struct mmci_platform_data mmcsd_platform_data = {
 130         /*
 131          * Do not set ocr_mask or voltage translation function,
 132          * we have a regulator we can control instead.
 133          */
 134         .f_max = 24000000,
 135         .gpio_wp = -1,
 136         .gpio_cd = U300_GPIO_PIN_MMC_CD,
 137         .cd_invert = true,
 138         .capabilities = MMC_CAP_MMC_HIGHSPEED |
 139         MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 140 #ifdef CONFIG_COH901318
 141         .dma_filter = coh901318_filter_id,
 142         .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
 143         /* Don't specify a TX channel, this RX channel is bidirectional */
 144 #endif
 145 };
 146
 147 static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
 148         U300_MMCSD_IRQS, &mmcsd_platform_data);
 149
 150 /*
 151  * The order of device declaration may be important, since some devices
 152  * have dependencies on other devices being initialized first.
 153  */
 154 static struct amba_device *amba_devs[] __initdata = {
 155         &uart0_device,
 156         &uart1_device,
 157         &pl022_device,
 158         &pl172_device,
 159         &mmcsd_device,
 160 };
 161
 162 /* Here follows a list of all hw resources that the platform devices
 163  * allocate. Note, clock dependencies are not included
 164  */
 165
 166 static struct resource gpio_resources[] = {
 167         {
 168                 .start = U300_GPIO_BASE,
 169                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 170                 .flags = IORESOURCE_MEM,
 171         },
 172         {
 173                 .name  = "gpio0",
 174                 .start = IRQ_U300_GPIO_PORT0,
 175                 .end   = IRQ_U300_GPIO_PORT0,
 176                 .flags = IORESOURCE_IRQ,
 177         },
 178         {
 179                 .name  = "gpio1",
 180                 .start = IRQ_U300_GPIO_PORT1,
 181                 .end   = IRQ_U300_GPIO_PORT1,
 182                 .flags = IORESOURCE_IRQ,
 183         },
 184         {
 185                 .name  = "gpio2",
 186                 .start = IRQ_U300_GPIO_PORT2,
 187                 .end   = IRQ_U300_GPIO_PORT2,
 188                 .flags = IORESOURCE_IRQ,
 189         },
 190         {
 191                 .name  = "gpio3",
 192                 .start = IRQ_U300_GPIO_PORT3,
 193                 .end   = IRQ_U300_GPIO_PORT3,
 194                 .flags = IORESOURCE_IRQ,
 195         },
 196         {
 197                 .name  = "gpio4",
 198                 .start = IRQ_U300_GPIO_PORT4,
 199                 .end   = IRQ_U300_GPIO_PORT4,
 200                 .flags = IORESOURCE_IRQ,
 201         },
 202         {
 203                 .name  = "gpio5",
 204                 .start = IRQ_U300_GPIO_PORT5,
 205                 .end   = IRQ_U300_GPIO_PORT5,
 206                 .flags = IORESOURCE_IRQ,
 207         },
 208         {
 209                 .name  = "gpio6",
 210                 .start = IRQ_U300_GPIO_PORT6,
 211                 .end   = IRQ_U300_GPIO_PORT6,
 212                 .flags = IORESOURCE_IRQ,
 213         },
 214 };
 215
 216 static struct resource keypad_resources[] = {
 217         {
 218                 .start = U300_KEYPAD_BASE,
 219                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 220                 .flags = IORESOURCE_MEM,
 221         },
 222         {
 223                 .name  = "coh901461-press",
 224                 .start = IRQ_U300_KEYPAD_KEYBF,
 225                 .end   = IRQ_U300_KEYPAD_KEYBF,
 226                 .flags = IORESOURCE_IRQ,
 227         },
 228         {
 229                 .name  = "coh901461-release",
 230                 .start = IRQ_U300_KEYPAD_KEYBR,
 231                 .end   = IRQ_U300_KEYPAD_KEYBR,
 232                 .flags = IORESOURCE_IRQ,
 233         },
 234 };
 235
 236 static struct resource rtc_resources[] = {
 237         {
 238                 .start = U300_RTC_BASE,
 239                 .end   = U300_RTC_BASE + SZ_4K - 1,
 240                 .flags = IORESOURCE_MEM,
 241         },
 242         {
 243                 .start = IRQ_U300_RTC,
 244                 .end   = IRQ_U300_RTC,
 245                 .flags = IORESOURCE_IRQ,
 246         },
 247 };
 248
 249 /*
 250  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 251  * but these are not yet used by the driver.
 252  */
 253 static struct resource fsmc_resources[] = {
 254         {
 255                 .name  = "nand_addr",
 256                 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
 257                 .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
 258                 .flags = IORESOURCE_MEM,
 259         },
 260         {
 261                 .name  = "nand_cmd",
 262                 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
 263                 .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
 264                 .flags = IORESOURCE_MEM,
 265         },
 266         {
 267                 .name  = "nand_data",
 268                 .start = U300_NAND_CS0_PHYS_BASE,
 269                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 270                 .flags = IORESOURCE_MEM,
 271         },
 272         {
 273                 .name  = "fsmc_regs",
 274                 .start = U300_NAND_IF_PHYS_BASE,
 275                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 276                 .flags = IORESOURCE_MEM,
 277         },
 278 };
 279
 280 static struct resource i2c0_resources[] = {
 281         {
 282                 .start = U300_I2C0_BASE,
 283                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 284                 .flags = IORESOURCE_MEM,
 285         },
 286         {
 287                 .start = IRQ_U300_I2C0,
 288                 .end   = IRQ_U300_I2C0,
 289                 .flags = IORESOURCE_IRQ,
 290         },
 291 };
 292
 293 static struct resource i2c1_resources[] = {
 294         {
 295                 .start = U300_I2C1_BASE,
 296                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 297                 .flags = IORESOURCE_MEM,
 298         },
 299         {
 300                 .start = IRQ_U300_I2C1,
 301                 .end   = IRQ_U300_I2C1,
 302                 .flags = IORESOURCE_IRQ,
 303         },
 304
 305 };
 306
 307 static struct resource wdog_resources[] = {
 308         {
 309                 .start = U300_WDOG_BASE,
 310                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 311                 .flags = IORESOURCE_MEM,
 312         },
 313         {
 314                 .start = IRQ_U300_WDOG,
 315                 .end   = IRQ_U300_WDOG,
 316                 .flags = IORESOURCE_IRQ,
 317         }
 318 };
 319
 320 static struct resource dma_resource[] = {
 321         {
 322                 .start = U300_DMAC_BASE,
 323                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 324                 .flags =  IORESOURCE_MEM,
 325         },
 326         {
 327                 .start = IRQ_U300_DMA,
 328                 .end = IRQ_U300_DMA,
 329                 .flags =  IORESOURCE_IRQ,
 330         }
 331 };
 332
 333 /* points out all dma slave channels.
 334  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 335  * Select all channels from A to B, end of list is marked with -1,-1
 336  */
 337 static int dma_slave_channels[] = {
 338         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 339         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 340
 341 /* points out all dma memcpy channels. */
 342 static int dma_memcpy_channels[] = {
 343         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 344
 345 /** register dma for memory access
 346  *
 347  * active  1 means dma intends to access memory
 348  *         0 means dma wont access memory
 349  */
 350 static void coh901318_access_memory_state(struct device *dev, bool active)
 351 {
 352 }
 353
 354 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 355                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 356                         COH901318_CX_CFG_LCR_DISABLE | \
 357                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 358                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 359 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 360                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 361                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 362                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 363                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 364                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 365                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 366                         COH901318_CX_CTRL_TCP_DISABLE | \
 367                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 368                         COH901318_CX_CTRL_HSP_DISABLE | \
 369                         COH901318_CX_CTRL_HSS_DISABLE | \
 370                         COH901318_CX_CTRL_DDMA_LEGACY | \
 371                         COH901318_CX_CTRL_PRDD_SOURCE)
 372 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 373                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 374                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 375                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 376                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 377                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 378                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 379                         COH901318_CX_CTRL_TCP_DISABLE | \
 380                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 381                         COH901318_CX_CTRL_HSP_DISABLE | \
 382                         COH901318_CX_CTRL_HSS_DISABLE | \
 383                         COH901318_CX_CTRL_DDMA_LEGACY | \
 384                         COH901318_CX_CTRL_PRDD_SOURCE)
 385 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 386                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 387                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 388                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 389                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 390                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 391                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 392                         COH901318_CX_CTRL_TCP_DISABLE | \
 393                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 394                         COH901318_CX_CTRL_HSP_DISABLE | \
 395                         COH901318_CX_CTRL_HSS_DISABLE | \
 396                         COH901318_CX_CTRL_DDMA_LEGACY | \
 397                         COH901318_CX_CTRL_PRDD_SOURCE)
 398
 399 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 400         {
 401                 .number = U300_DMA_MSL_TX_0,
 402                 .name = "MSL TX 0",
 403                 .priority_high = 0,
 404                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 405         },
 406         {
 407                 .number = U300_DMA_MSL_TX_1,
 408                 .name = "MSL TX 1",
 409                 .priority_high = 0,
 410                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 411                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 412                                 COH901318_CX_CFG_LCR_DISABLE |
 413                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 414                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 415                 .param.ctrl_lli_chained = 0 |
 416                                 COH901318_CX_CTRL_TC_ENABLE |
 417                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 418                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 419                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 420                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 421                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 422                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 423                                 COH901318_CX_CTRL_TCP_DISABLE |
 424                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 425                                 COH901318_CX_CTRL_HSP_ENABLE |
 426                                 COH901318_CX_CTRL_HSS_DISABLE |
 427                                 COH901318_CX_CTRL_DDMA_LEGACY |
 428                                 COH901318_CX_CTRL_PRDD_SOURCE,
 429                 .param.ctrl_lli = 0 |
 430                                 COH901318_CX_CTRL_TC_ENABLE |
 431                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 432                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 433                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 434                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 435                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 436                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 437                                 COH901318_CX_CTRL_TCP_ENABLE |
 438                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 439                                 COH901318_CX_CTRL_HSP_ENABLE |
 440                                 COH901318_CX_CTRL_HSS_DISABLE |
 441                                 COH901318_CX_CTRL_DDMA_LEGACY |
 442                                 COH901318_CX_CTRL_PRDD_SOURCE,
 443                 .param.ctrl_lli_last = 0 |
 444                                 COH901318_CX_CTRL_TC_ENABLE |
 445                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 446                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 447                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 448                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 449                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 450                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 451                                 COH901318_CX_CTRL_TCP_ENABLE |
 452                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 453                                 COH901318_CX_CTRL_HSP_ENABLE |
 454                                 COH901318_CX_CTRL_HSS_DISABLE |
 455                                 COH901318_CX_CTRL_DDMA_LEGACY |
 456                                 COH901318_CX_CTRL_PRDD_SOURCE,
 457         },
 458         {
 459                 .number = U300_DMA_MSL_TX_2,
 460                 .name = "MSL TX 2",
 461                 .priority_high = 0,
 462                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 463                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 464                                 COH901318_CX_CFG_LCR_DISABLE |
 465                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 466                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 467                 .param.ctrl_lli_chained = 0 |
 468                                 COH901318_CX_CTRL_TC_ENABLE |
 469                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 470                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 471                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 472                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 473                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 474                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 475                                 COH901318_CX_CTRL_TCP_DISABLE |
 476                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 477                                 COH901318_CX_CTRL_HSP_ENABLE |
 478                                 COH901318_CX_CTRL_HSS_DISABLE |
 479                                 COH901318_CX_CTRL_DDMA_LEGACY |
 480                                 COH901318_CX_CTRL_PRDD_SOURCE,
 481                 .param.ctrl_lli = 0 |
 482                                 COH901318_CX_CTRL_TC_ENABLE |
 483                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 484                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 485                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 486                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 487                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 488                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 489                                 COH901318_CX_CTRL_TCP_ENABLE |
 490                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 491                                 COH901318_CX_CTRL_HSP_ENABLE |
 492                                 COH901318_CX_CTRL_HSS_DISABLE |
 493                                 COH901318_CX_CTRL_DDMA_LEGACY |
 494                                 COH901318_CX_CTRL_PRDD_SOURCE,
 495                 .param.ctrl_lli_last = 0 |
 496                                 COH901318_CX_CTRL_TC_ENABLE |
 497                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 498                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 499                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 500                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 501                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 502                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 503                                 COH901318_CX_CTRL_TCP_ENABLE |
 504                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 505                                 COH901318_CX_CTRL_HSP_ENABLE |
 506                                 COH901318_CX_CTRL_HSS_DISABLE |
 507                                 COH901318_CX_CTRL_DDMA_LEGACY |
 508                                 COH901318_CX_CTRL_PRDD_SOURCE,
 509                 .desc_nbr_max = 10,
 510         },
 511         {
 512                 .number = U300_DMA_MSL_TX_3,
 513                 .name = "MSL TX 3",
 514                 .priority_high = 0,
 515                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 516                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 517                                 COH901318_CX_CFG_LCR_DISABLE |
 518                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 519                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 520                 .param.ctrl_lli_chained = 0 |
 521                                 COH901318_CX_CTRL_TC_ENABLE |
 522                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 523                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 524                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 525                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 526                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 527                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 528                                 COH901318_CX_CTRL_TCP_DISABLE |
 529                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 530                                 COH901318_CX_CTRL_HSP_ENABLE |
 531                                 COH901318_CX_CTRL_HSS_DISABLE |
 532                                 COH901318_CX_CTRL_DDMA_LEGACY |
 533                                 COH901318_CX_CTRL_PRDD_SOURCE,
 534                 .param.ctrl_lli = 0 |
 535                                 COH901318_CX_CTRL_TC_ENABLE |
 536                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 537                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 538                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 539                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 540                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 541                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 542                                 COH901318_CX_CTRL_TCP_ENABLE |
 543                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 544                                 COH901318_CX_CTRL_HSP_ENABLE |
 545                                 COH901318_CX_CTRL_HSS_DISABLE |
 546                                 COH901318_CX_CTRL_DDMA_LEGACY |
 547                                 COH901318_CX_CTRL_PRDD_SOURCE,
 548                 .param.ctrl_lli_last = 0 |
 549                                 COH901318_CX_CTRL_TC_ENABLE |
 550                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 551                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 552                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 553                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 554                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 555                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 556                                 COH901318_CX_CTRL_TCP_ENABLE |
 557                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 558                                 COH901318_CX_CTRL_HSP_ENABLE |
 559                                 COH901318_CX_CTRL_HSS_DISABLE |
 560                                 COH901318_CX_CTRL_DDMA_LEGACY |
 561                                 COH901318_CX_CTRL_PRDD_SOURCE,
 562         },
 563         {
 564                 .number = U300_DMA_MSL_TX_4,
 565                 .name = "MSL TX 4",
 566                 .priority_high = 0,
 567                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 568                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 569                                 COH901318_CX_CFG_LCR_DISABLE |
 570                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 571                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 572                 .param.ctrl_lli_chained = 0 |
 573                                 COH901318_CX_CTRL_TC_ENABLE |
 574                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 575                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 576                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 577                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 578                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 579                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 580                                 COH901318_CX_CTRL_TCP_DISABLE |
 581                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 582                                 COH901318_CX_CTRL_HSP_ENABLE |
 583                                 COH901318_CX_CTRL_HSS_DISABLE |
 584                                 COH901318_CX_CTRL_DDMA_LEGACY |
 585                                 COH901318_CX_CTRL_PRDD_SOURCE,
 586                 .param.ctrl_lli = 0 |
 587                                 COH901318_CX_CTRL_TC_ENABLE |
 588                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 589                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 590                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 591                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 592                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 593                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 594                                 COH901318_CX_CTRL_TCP_ENABLE |
 595                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 596                                 COH901318_CX_CTRL_HSP_ENABLE |
 597                                 COH901318_CX_CTRL_HSS_DISABLE |
 598                                 COH901318_CX_CTRL_DDMA_LEGACY |
 599                                 COH901318_CX_CTRL_PRDD_SOURCE,
 600                 .param.ctrl_lli_last = 0 |
 601                                 COH901318_CX_CTRL_TC_ENABLE |
 602                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 603                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 604                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 605                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 606                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 607                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 608                                 COH901318_CX_CTRL_TCP_ENABLE |
 609                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 610                                 COH901318_CX_CTRL_HSP_ENABLE |
 611                                 COH901318_CX_CTRL_HSS_DISABLE |
 612                                 COH901318_CX_CTRL_DDMA_LEGACY |
 613                                 COH901318_CX_CTRL_PRDD_SOURCE,
 614         },
 615         {
 616                 .number = U300_DMA_MSL_TX_5,
 617                 .name = "MSL TX 5",
 618                 .priority_high = 0,
 619                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 620         },
 621         {
 622                 .number = U300_DMA_MSL_TX_6,
 623                 .name = "MSL TX 6",
 624                 .priority_high = 0,
 625                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 626         },
 627         {
 628                 .number = U300_DMA_MSL_RX_0,
 629                 .name = "MSL RX 0",
 630                 .priority_high = 0,
 631                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 632         },
 633         {
 634                 .number = U300_DMA_MSL_RX_1,
 635                 .name = "MSL RX 1",
 636                 .priority_high = 0,
 637                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 638                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 639                                 COH901318_CX_CFG_LCR_DISABLE |
 640                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 641                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 642                 .param.ctrl_lli_chained = 0 |
 643                                 COH901318_CX_CTRL_TC_ENABLE |
 644                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 645                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 646                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 647                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 648                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 649                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 650                                 COH901318_CX_CTRL_TCP_DISABLE |
 651                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 652                                 COH901318_CX_CTRL_HSP_ENABLE |
 653                                 COH901318_CX_CTRL_HSS_DISABLE |
 654                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 655                                 COH901318_CX_CTRL_PRDD_DEST,
 656                 .param.ctrl_lli = 0,
 657                 .param.ctrl_lli_last = 0 |
 658                                 COH901318_CX_CTRL_TC_ENABLE |
 659                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 660                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 661                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 662                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 663                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 664                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 665                                 COH901318_CX_CTRL_TCP_DISABLE |
 666                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 667                                 COH901318_CX_CTRL_HSP_ENABLE |
 668                                 COH901318_CX_CTRL_HSS_DISABLE |
 669                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 670                                 COH901318_CX_CTRL_PRDD_DEST,
 671         },
 672         {
 673                 .number = U300_DMA_MSL_RX_2,
 674                 .name = "MSL RX 2",
 675                 .priority_high = 0,
 676                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 677                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 678                                 COH901318_CX_CFG_LCR_DISABLE |
 679                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 680                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 681                 .param.ctrl_lli_chained = 0 |
 682                                 COH901318_CX_CTRL_TC_ENABLE |
 683                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 684                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 685                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 686                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 687                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 688                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 689                                 COH901318_CX_CTRL_TCP_DISABLE |
 690                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 691                                 COH901318_CX_CTRL_HSP_ENABLE |
 692                                 COH901318_CX_CTRL_HSS_DISABLE |
 693                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 694                                 COH901318_CX_CTRL_PRDD_DEST,
 695                 .param.ctrl_lli = 0 |
 696                                 COH901318_CX_CTRL_TC_ENABLE |
 697                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 698                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 699                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 700                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 701                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 702                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 703                                 COH901318_CX_CTRL_TCP_DISABLE |
 704                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 705                                 COH901318_CX_CTRL_HSP_ENABLE |
 706                                 COH901318_CX_CTRL_HSS_DISABLE |
 707                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 708                                 COH901318_CX_CTRL_PRDD_DEST,
 709                 .param.ctrl_lli_last = 0 |
 710                                 COH901318_CX_CTRL_TC_ENABLE |
 711                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 712                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 713                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 714                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 715                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 716                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 717                                 COH901318_CX_CTRL_TCP_DISABLE |
 718                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 719                                 COH901318_CX_CTRL_HSP_ENABLE |
 720                                 COH901318_CX_CTRL_HSS_DISABLE |
 721                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 722                                 COH901318_CX_CTRL_PRDD_DEST,
 723         },
 724         {
 725                 .number = U300_DMA_MSL_RX_3,
 726                 .name = "MSL RX 3",
 727                 .priority_high = 0,
 728                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 729                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 730                                 COH901318_CX_CFG_LCR_DISABLE |
 731                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 732                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 733                 .param.ctrl_lli_chained = 0 |
 734                                 COH901318_CX_CTRL_TC_ENABLE |
 735                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 736                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 737                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 738                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 739                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 740                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 741                                 COH901318_CX_CTRL_TCP_DISABLE |
 742                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 743                                 COH901318_CX_CTRL_HSP_ENABLE |
 744                                 COH901318_CX_CTRL_HSS_DISABLE |
 745                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 746                                 COH901318_CX_CTRL_PRDD_DEST,
 747                 .param.ctrl_lli = 0 |
 748                                 COH901318_CX_CTRL_TC_ENABLE |
 749                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 750                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 751                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 752                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 753                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 754                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 755                                 COH901318_CX_CTRL_TCP_DISABLE |
 756                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 757                                 COH901318_CX_CTRL_HSP_ENABLE |
 758                                 COH901318_CX_CTRL_HSS_DISABLE |
 759                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 760                                 COH901318_CX_CTRL_PRDD_DEST,
 761                 .param.ctrl_lli_last = 0 |
 762                                 COH901318_CX_CTRL_TC_ENABLE |
 763                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 764                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 765                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 766                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 767                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 768                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 769                                 COH901318_CX_CTRL_TCP_DISABLE |
 770                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 771                                 COH901318_CX_CTRL_HSP_ENABLE |
 772                                 COH901318_CX_CTRL_HSS_DISABLE |
 773                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 774                                 COH901318_CX_CTRL_PRDD_DEST,
 775         },
 776         {
 777                 .number = U300_DMA_MSL_RX_4,
 778                 .name = "MSL RX 4",
 779                 .priority_high = 0,
 780                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 781                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 782                                 COH901318_CX_CFG_LCR_DISABLE |
 783                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 784                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 785                 .param.ctrl_lli_chained = 0 |
 786                                 COH901318_CX_CTRL_TC_ENABLE |
 787                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 788                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 789                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 790                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 791                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 792                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 793                                 COH901318_CX_CTRL_TCP_DISABLE |
 794                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 795                                 COH901318_CX_CTRL_HSP_ENABLE |
 796                                 COH901318_CX_CTRL_HSS_DISABLE |
 797                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 798                                 COH901318_CX_CTRL_PRDD_DEST,
 799                 .param.ctrl_lli = 0 |
 800                                 COH901318_CX_CTRL_TC_ENABLE |
 801                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 802                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 803                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 804                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 805                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 806                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 807                                 COH901318_CX_CTRL_TCP_DISABLE |
 808                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 809                                 COH901318_CX_CTRL_HSP_ENABLE |
 810                                 COH901318_CX_CTRL_HSS_DISABLE |
 811                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 812                                 COH901318_CX_CTRL_PRDD_DEST,
 813                 .param.ctrl_lli_last = 0 |
 814                                 COH901318_CX_CTRL_TC_ENABLE |
 815                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 816                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 817                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 818                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 819                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 820                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 821                                 COH901318_CX_CTRL_TCP_DISABLE |
 822                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 823                                 COH901318_CX_CTRL_HSP_ENABLE |
 824                                 COH901318_CX_CTRL_HSS_DISABLE |
 825                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 826                                 COH901318_CX_CTRL_PRDD_DEST,
 827         },
 828         {
 829                 .number = U300_DMA_MSL_RX_5,
 830                 .name = "MSL RX 5",
 831                 .priority_high = 0,
 832                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 833                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 834                                 COH901318_CX_CFG_LCR_DISABLE |
 835                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 836                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 837                 .param.ctrl_lli_chained = 0 |
 838                                 COH901318_CX_CTRL_TC_ENABLE |
 839                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 840                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 841                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 842                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 843                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 844                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 845                                 COH901318_CX_CTRL_TCP_DISABLE |
 846                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 847                                 COH901318_CX_CTRL_HSP_ENABLE |
 848                                 COH901318_CX_CTRL_HSS_DISABLE |
 849                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 850                                 COH901318_CX_CTRL_PRDD_DEST,
 851                 .param.ctrl_lli = 0 |
 852                                 COH901318_CX_CTRL_TC_ENABLE |
 853                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 854                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 855                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 856                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 857                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 858                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 859                                 COH901318_CX_CTRL_TCP_DISABLE |
 860                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 861                                 COH901318_CX_CTRL_HSP_ENABLE |
 862                                 COH901318_CX_CTRL_HSS_DISABLE |
 863                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 864                                 COH901318_CX_CTRL_PRDD_DEST,
 865                 .param.ctrl_lli_last = 0 |
 866                                 COH901318_CX_CTRL_TC_ENABLE |
 867                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 868                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 869                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 870                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 871                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 872                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 873                                 COH901318_CX_CTRL_TCP_DISABLE |
 874                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 875                                 COH901318_CX_CTRL_HSP_ENABLE |
 876                                 COH901318_CX_CTRL_HSS_DISABLE |
 877                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 878                                 COH901318_CX_CTRL_PRDD_DEST,
 879         },
 880         {
 881                 .number = U300_DMA_MSL_RX_6,
 882                 .name = "MSL RX 6",
 883                 .priority_high = 0,
 884                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 885         },
 886         /*
 887          * Don't set up device address, burst count or size of src
 888          * or dst bus for this peripheral - handled by PrimeCell
 889          * DMA extension.
 890          */
 891         {
 892                 .number = U300_DMA_MMCSD_RX_TX,
 893                 .name = "MMCSD RX TX",
 894                 .priority_high = 0,
 895                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 896                                 COH901318_CX_CFG_LCR_DISABLE |
 897                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 898                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 899                 .param.ctrl_lli_chained = 0 |
 900                                 COH901318_CX_CTRL_TC_ENABLE |
 901                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 902                                 COH901318_CX_CTRL_TCP_ENABLE |
 903                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 904                                 COH901318_CX_CTRL_HSP_ENABLE |
 905                                 COH901318_CX_CTRL_HSS_DISABLE |
 906                                 COH901318_CX_CTRL_DDMA_LEGACY,
 907                 .param.ctrl_lli = 0 |
 908                                 COH901318_CX_CTRL_TC_ENABLE |
 909                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 910                                 COH901318_CX_CTRL_TCP_ENABLE |
 911                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 912                                 COH901318_CX_CTRL_HSP_ENABLE |
 913                                 COH901318_CX_CTRL_HSS_DISABLE |
 914                                 COH901318_CX_CTRL_DDMA_LEGACY,
 915                 .param.ctrl_lli_last = 0 |
 916                                 COH901318_CX_CTRL_TC_ENABLE |
 917                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 918                                 COH901318_CX_CTRL_TCP_DISABLE |
 919                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 920                                 COH901318_CX_CTRL_HSP_ENABLE |
 921                                 COH901318_CX_CTRL_HSS_DISABLE |
 922                                 COH901318_CX_CTRL_DDMA_LEGACY,
 923
 924         },
 925         {
 926                 .number = U300_DMA_MSPRO_TX,
 927                 .name = "MSPRO TX",
 928                 .priority_high = 0,
 929         },
 930         {
 931                 .number = U300_DMA_MSPRO_RX,
 932                 .name = "MSPRO RX",
 933                 .priority_high = 0,
 934         },
 935         /*
 936          * Don't set up device address, burst count or size of src
 937          * or dst bus for this peripheral - handled by PrimeCell
 938          * DMA extension.
 939          */
 940         {
 941                 .number = U300_DMA_UART0_TX,
 942                 .name = "UART0 TX",
 943                 .priority_high = 0,
 944                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 945                                 COH901318_CX_CFG_LCR_DISABLE |
 946                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 947                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 948                 .param.ctrl_lli_chained = 0 |
 949                                 COH901318_CX_CTRL_TC_ENABLE |
 950                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 951                                 COH901318_CX_CTRL_TCP_ENABLE |
 952                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 953                                 COH901318_CX_CTRL_HSP_ENABLE |
 954                                 COH901318_CX_CTRL_HSS_DISABLE |
 955                                 COH901318_CX_CTRL_DDMA_LEGACY,
 956                 .param.ctrl_lli = 0 |
 957                                 COH901318_CX_CTRL_TC_ENABLE |
 958                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 959                                 COH901318_CX_CTRL_TCP_ENABLE |
 960                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 961                                 COH901318_CX_CTRL_HSP_ENABLE |
 962                                 COH901318_CX_CTRL_HSS_DISABLE |
 963                                 COH901318_CX_CTRL_DDMA_LEGACY,
 964                 .param.ctrl_lli_last = 0 |
 965                                 COH901318_CX_CTRL_TC_ENABLE |
 966                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 967                                 COH901318_CX_CTRL_TCP_ENABLE |
 968                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 969                                 COH901318_CX_CTRL_HSP_ENABLE |
 970                                 COH901318_CX_CTRL_HSS_DISABLE |
 971                                 COH901318_CX_CTRL_DDMA_LEGACY,
 972         },
 973         {
 974                 .number = U300_DMA_UART0_RX,
 975                 .name = "UART0 RX",
 976                 .priority_high = 0,
 977                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 978                                 COH901318_CX_CFG_LCR_DISABLE |
 979                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 980                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 981                 .param.ctrl_lli_chained = 0 |
 982                                 COH901318_CX_CTRL_TC_ENABLE |
 983                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 984                                 COH901318_CX_CTRL_TCP_ENABLE |
 985                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 986                                 COH901318_CX_CTRL_HSP_ENABLE |
 987                                 COH901318_CX_CTRL_HSS_DISABLE |
 988                                 COH901318_CX_CTRL_DDMA_LEGACY,
 989                 .param.ctrl_lli = 0 |
 990                                 COH901318_CX_CTRL_TC_ENABLE |
 991                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 992                                 COH901318_CX_CTRL_TCP_ENABLE |
 993                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 994                                 COH901318_CX_CTRL_HSP_ENABLE |
 995                                 COH901318_CX_CTRL_HSS_DISABLE |
 996                                 COH901318_CX_CTRL_DDMA_LEGACY,
 997                 .param.ctrl_lli_last = 0 |
 998                                 COH901318_CX_CTRL_TC_ENABLE |
 999                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1000                                 COH901318_CX_CTRL_TCP_ENABLE |
1001                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1002                                 COH901318_CX_CTRL_HSP_ENABLE |
1003                                 COH901318_CX_CTRL_HSS_DISABLE |
1004                                 COH901318_CX_CTRL_DDMA_LEGACY,
1005         },
1006         {
1007                 .number = U300_DMA_APEX_TX,
1008                 .name = "APEX TX",
1009                 .priority_high = 0,
1010         },
1011         {
1012                 .number = U300_DMA_APEX_RX,
1013                 .name = "APEX RX",
1014                 .priority_high = 0,
1015         },
1016         {
1017                 .number = U300_DMA_PCM_I2S0_TX,
1018                 .name = "PCM I2S0 TX",
1019                 .priority_high = 1,
1020                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1021                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1022                                 COH901318_CX_CFG_LCR_DISABLE |
1023                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1024                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1025                 .param.ctrl_lli_chained = 0 |
1026                                 COH901318_CX_CTRL_TC_ENABLE |
1027                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1028                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1029                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1030                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1031                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1032                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1033                                 COH901318_CX_CTRL_TCP_DISABLE |
1034                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1035                                 COH901318_CX_CTRL_HSP_ENABLE |
1036                                 COH901318_CX_CTRL_HSS_DISABLE |
1037                                 COH901318_CX_CTRL_DDMA_LEGACY |
1038                                 COH901318_CX_CTRL_PRDD_SOURCE,
1039                 .param.ctrl_lli = 0 |
1040                                 COH901318_CX_CTRL_TC_ENABLE |
1041                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1042                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1043                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1044                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1045                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1046                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1047                                 COH901318_CX_CTRL_TCP_ENABLE |
1048                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1049                                 COH901318_CX_CTRL_HSP_ENABLE |
1050                                 COH901318_CX_CTRL_HSS_DISABLE |
1051                                 COH901318_CX_CTRL_DDMA_LEGACY |
1052                                 COH901318_CX_CTRL_PRDD_SOURCE,
1053                 .param.ctrl_lli_last = 0 |
1054                                 COH901318_CX_CTRL_TC_ENABLE |
1055                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1056                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1057                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1058                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1059                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1060                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1061                                 COH901318_CX_CTRL_TCP_ENABLE |
1062                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1063                                 COH901318_CX_CTRL_HSP_ENABLE |
1064                                 COH901318_CX_CTRL_HSS_DISABLE |
1065                                 COH901318_CX_CTRL_DDMA_LEGACY |
1066                                 COH901318_CX_CTRL_PRDD_SOURCE,
1067         },
1068         {
1069                 .number = U300_DMA_PCM_I2S0_RX,
1070                 .name = "PCM I2S0 RX",
1071                 .priority_high = 1,
1072                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1073                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1074                                 COH901318_CX_CFG_LCR_DISABLE |
1075                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1076                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1077                 .param.ctrl_lli_chained = 0 |
1078                                 COH901318_CX_CTRL_TC_ENABLE |
1079                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1080                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1081                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1082                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1083                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1084                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1085                                 COH901318_CX_CTRL_TCP_DISABLE |
1086                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1087                                 COH901318_CX_CTRL_HSP_ENABLE |
1088                                 COH901318_CX_CTRL_HSS_DISABLE |
1089                                 COH901318_CX_CTRL_DDMA_LEGACY |
1090                                 COH901318_CX_CTRL_PRDD_DEST,
1091                 .param.ctrl_lli = 0 |
1092                                 COH901318_CX_CTRL_TC_ENABLE |
1093                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1094                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1095                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1096                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1097                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1098                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1099                                 COH901318_CX_CTRL_TCP_ENABLE |
1100                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1101                                 COH901318_CX_CTRL_HSP_ENABLE |
1102                                 COH901318_CX_CTRL_HSS_DISABLE |
1103                                 COH901318_CX_CTRL_DDMA_LEGACY |
1104                                 COH901318_CX_CTRL_PRDD_DEST,
1105                 .param.ctrl_lli_last = 0 |
1106                                 COH901318_CX_CTRL_TC_ENABLE |
1107                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1108                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1109                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1110                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1111                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1112                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1113                                 COH901318_CX_CTRL_TCP_ENABLE |
1114                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1115                                 COH901318_CX_CTRL_HSP_ENABLE |
1116                                 COH901318_CX_CTRL_HSS_DISABLE |
1117                                 COH901318_CX_CTRL_DDMA_LEGACY |
1118                                 COH901318_CX_CTRL_PRDD_DEST,
1119         },
1120         {
1121                 .number = U300_DMA_PCM_I2S1_TX,
1122                 .name = "PCM I2S1 TX",
1123                 .priority_high = 1,
1124                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1125                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1126                                 COH901318_CX_CFG_LCR_DISABLE |
1127                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1128                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1129                 .param.ctrl_lli_chained = 0 |
1130                                 COH901318_CX_CTRL_TC_ENABLE |
1131                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1132                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1133                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1134                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1135                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1136                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1137                                 COH901318_CX_CTRL_TCP_DISABLE |
1138                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1139                                 COH901318_CX_CTRL_HSP_ENABLE |
1140                                 COH901318_CX_CTRL_HSS_DISABLE |
1141                                 COH901318_CX_CTRL_DDMA_LEGACY |
1142                                 COH901318_CX_CTRL_PRDD_SOURCE,
1143                 .param.ctrl_lli = 0 |
1144                                 COH901318_CX_CTRL_TC_ENABLE |
1145                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1146                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1147                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1148                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1149                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1150                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1151                                 COH901318_CX_CTRL_TCP_ENABLE |
1152                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1153                                 COH901318_CX_CTRL_HSP_ENABLE |
1154                                 COH901318_CX_CTRL_HSS_DISABLE |
1155                                 COH901318_CX_CTRL_DDMA_LEGACY |
1156                                 COH901318_CX_CTRL_PRDD_SOURCE,
1157                 .param.ctrl_lli_last = 0 |
1158                                 COH901318_CX_CTRL_TC_ENABLE |
1159                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1160                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1161                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1162                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1163                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1164                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1165                                 COH901318_CX_CTRL_TCP_ENABLE |
1166                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1167                                 COH901318_CX_CTRL_HSP_ENABLE |
1168                                 COH901318_CX_CTRL_HSS_DISABLE |
1169                                 COH901318_CX_CTRL_DDMA_LEGACY |
1170                                 COH901318_CX_CTRL_PRDD_SOURCE,
1171         },
1172         {
1173                 .number = U300_DMA_PCM_I2S1_RX,
1174                 .name = "PCM I2S1 RX",
1175                 .priority_high = 1,
1176                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1177                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1178                                 COH901318_CX_CFG_LCR_DISABLE |
1179                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1180                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1181                 .param.ctrl_lli_chained = 0 |
1182                                 COH901318_CX_CTRL_TC_ENABLE |
1183                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1184                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1185                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1186                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1187                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1188                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1189                                 COH901318_CX_CTRL_TCP_DISABLE |
1190                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1191                                 COH901318_CX_CTRL_HSP_ENABLE |
1192                                 COH901318_CX_CTRL_HSS_DISABLE |
1193                                 COH901318_CX_CTRL_DDMA_LEGACY |
1194                                 COH901318_CX_CTRL_PRDD_DEST,
1195                 .param.ctrl_lli = 0 |
1196                                 COH901318_CX_CTRL_TC_ENABLE |
1197                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1198                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1199                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1200                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1201                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1202                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1203                                 COH901318_CX_CTRL_TCP_ENABLE |
1204                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1205                                 COH901318_CX_CTRL_HSP_ENABLE |
1206                                 COH901318_CX_CTRL_HSS_DISABLE |
1207                                 COH901318_CX_CTRL_DDMA_LEGACY |
1208                                 COH901318_CX_CTRL_PRDD_DEST,
1209                 .param.ctrl_lli_last = 0 |
1210                                 COH901318_CX_CTRL_TC_ENABLE |
1211                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1212                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1213                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1214                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1215                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1216                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1217                                 COH901318_CX_CTRL_TCP_ENABLE |
1218                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1219                                 COH901318_CX_CTRL_HSP_ENABLE |
1220                                 COH901318_CX_CTRL_HSS_DISABLE |
1221                                 COH901318_CX_CTRL_DDMA_LEGACY |
1222                                 COH901318_CX_CTRL_PRDD_DEST,
1223         },
1224         {
1225                 .number = U300_DMA_XGAM_CDI,
1226                 .name = "XGAM CDI",
1227                 .priority_high = 0,
1228         },
1229         {
1230                 .number = U300_DMA_XGAM_PDI,
1231                 .name = "XGAM PDI",
1232                 .priority_high = 0,
1233         },
1234         /*
1235          * Don't set up device address, burst count or size of src
1236          * or dst bus for this peripheral - handled by PrimeCell
1237          * DMA extension.
1238          */
1239         {
1240                 .number = U300_DMA_SPI_TX,
1241                 .name = "SPI TX",
1242                 .priority_high = 0,
1243                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1244                                 COH901318_CX_CFG_LCR_DISABLE |
1245                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1246                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1247                 .param.ctrl_lli_chained = 0 |
1248                                 COH901318_CX_CTRL_TC_ENABLE |
1249                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1250                                 COH901318_CX_CTRL_TCP_DISABLE |
1251                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1252                                 COH901318_CX_CTRL_HSP_ENABLE |
1253                                 COH901318_CX_CTRL_HSS_DISABLE |
1254                                 COH901318_CX_CTRL_DDMA_LEGACY,
1255                 .param.ctrl_lli = 0 |
1256                                 COH901318_CX_CTRL_TC_ENABLE |
1257                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1258                                 COH901318_CX_CTRL_TCP_DISABLE |
1259                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1260                                 COH901318_CX_CTRL_HSP_ENABLE |
1261                                 COH901318_CX_CTRL_HSS_DISABLE |
1262                                 COH901318_CX_CTRL_DDMA_LEGACY,
1263                 .param.ctrl_lli_last = 0 |
1264                                 COH901318_CX_CTRL_TC_ENABLE |
1265                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1266                                 COH901318_CX_CTRL_TCP_DISABLE |
1267                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1268                                 COH901318_CX_CTRL_HSP_ENABLE |
1269                                 COH901318_CX_CTRL_HSS_DISABLE |
1270                                 COH901318_CX_CTRL_DDMA_LEGACY,
1271         },
1272         {
1273                 .number = U300_DMA_SPI_RX,
1274                 .name = "SPI RX",
1275                 .priority_high = 0,
1276                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1277                                 COH901318_CX_CFG_LCR_DISABLE |
1278                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1279                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1280                 .param.ctrl_lli_chained = 0 |
1281                                 COH901318_CX_CTRL_TC_ENABLE |
1282                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1283                                 COH901318_CX_CTRL_TCP_DISABLE |
1284                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1285                                 COH901318_CX_CTRL_HSP_ENABLE |
1286                                 COH901318_CX_CTRL_HSS_DISABLE |
1287                                 COH901318_CX_CTRL_DDMA_LEGACY,
1288                 .param.ctrl_lli = 0 |
1289                                 COH901318_CX_CTRL_TC_ENABLE |
1290                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1291                                 COH901318_CX_CTRL_TCP_DISABLE |
1292                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1293                                 COH901318_CX_CTRL_HSP_ENABLE |
1294                                 COH901318_CX_CTRL_HSS_DISABLE |
1295                                 COH901318_CX_CTRL_DDMA_LEGACY,
1296                 .param.ctrl_lli_last = 0 |
1297                                 COH901318_CX_CTRL_TC_ENABLE |
1298                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1299                                 COH901318_CX_CTRL_TCP_DISABLE |
1300                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1301                                 COH901318_CX_CTRL_HSP_ENABLE |
1302                                 COH901318_CX_CTRL_HSS_DISABLE |
1303                                 COH901318_CX_CTRL_DDMA_LEGACY,
1304
1305         },
1306         {
1307                 .number = U300_DMA_GENERAL_PURPOSE_0,
1308                 .name = "GENERAL 00",
1309                 .priority_high = 0,
1310
1311                 .param.config = flags_memcpy_config,
1312                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1313                 .param.ctrl_lli = flags_memcpy_lli,
1314                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1315         },
1316         {
1317                 .number = U300_DMA_GENERAL_PURPOSE_1,
1318                 .name = "GENERAL 01",
1319                 .priority_high = 0,
1320
1321                 .param.config = flags_memcpy_config,
1322                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1323                 .param.ctrl_lli = flags_memcpy_lli,
1324                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1325         },
1326         {
1327                 .number = U300_DMA_GENERAL_PURPOSE_2,
1328                 .name = "GENERAL 02",
1329                 .priority_high = 0,
1330
1331                 .param.config = flags_memcpy_config,
1332                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1333                 .param.ctrl_lli = flags_memcpy_lli,
1334                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1335         },
1336         {
1337                 .number = U300_DMA_GENERAL_PURPOSE_3,
1338                 .name = "GENERAL 03",
1339                 .priority_high = 0,
1340
1341                 .param.config = flags_memcpy_config,
1342                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1343                 .param.ctrl_lli = flags_memcpy_lli,
1344                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1345         },
1346         {
1347                 .number = U300_DMA_GENERAL_PURPOSE_4,
1348                 .name = "GENERAL 04",
1349                 .priority_high = 0,
1350
1351                 .param.config = flags_memcpy_config,
1352                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1353                 .param.ctrl_lli = flags_memcpy_lli,
1354                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1355         },
1356         {
1357                 .number = U300_DMA_GENERAL_PURPOSE_5,
1358                 .name = "GENERAL 05",
1359                 .priority_high = 0,
1360
1361                 .param.config = flags_memcpy_config,
1362                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1363                 .param.ctrl_lli = flags_memcpy_lli,
1364                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1365         },
1366         {
1367                 .number = U300_DMA_GENERAL_PURPOSE_6,
1368                 .name = "GENERAL 06",
1369                 .priority_high = 0,
1370
1371                 .param.config = flags_memcpy_config,
1372                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1373                 .param.ctrl_lli = flags_memcpy_lli,
1374                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1375         },
1376         {
1377                 .number = U300_DMA_GENERAL_PURPOSE_7,
1378                 .name = "GENERAL 07",
1379                 .priority_high = 0,
1380
1381                 .param.config = flags_memcpy_config,
1382                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1383                 .param.ctrl_lli = flags_memcpy_lli,
1384                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1385         },
1386         {
1387                 .number = U300_DMA_GENERAL_PURPOSE_8,
1388                 .name = "GENERAL 08",
1389                 .priority_high = 0,
1390
1391                 .param.config = flags_memcpy_config,
1392                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1393                 .param.ctrl_lli = flags_memcpy_lli,
1394                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1395         },
1396         {
1397                 .number = U300_DMA_UART1_TX,
1398                 .name = "UART1 TX",
1399                 .priority_high = 0,
1400         },
1401         {
1402                 .number = U300_DMA_UART1_RX,
1403                 .name = "UART1 RX",
1404                 .priority_high = 0,
1405         }
1406 };
1407
1408
1409 static struct coh901318_platform coh901318_platform = {
1410         .chans_slave = dma_slave_channels,
1411         .chans_memcpy = dma_memcpy_channels,
1412         .access_memory_state = coh901318_access_memory_state,
1413         .chan_conf = chan_config,
1414         .max_channels = U300_DMA_CHANNELS,
1415 };
1416
1417 static struct resource pinctrl_resources[] = {
1418         {
1419                 .start = U300_SYSCON_BASE,
1420                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
1421                 .flags = IORESOURCE_MEM,
1422         },
1423 };
1424
1425 static struct platform_device wdog_device = {
1426         .name = "coh901327_wdog",
1427         .id = -1,
1428         .num_resources = ARRAY_SIZE(wdog_resources),
1429         .resource = wdog_resources,
1430 };
1431
1432 static struct platform_device i2c0_device = {
1433         .name = "stu300",
1434         .id = 0,
1435         .num_resources = ARRAY_SIZE(i2c0_resources),
1436         .resource = i2c0_resources,
1437 };
1438
1439 static struct platform_device i2c1_device = {
1440         .name = "stu300",
1441         .id = 1,
1442         .num_resources = ARRAY_SIZE(i2c1_resources),
1443         .resource = i2c1_resources,
1444 };
1445
1446 static struct platform_device pinctrl_device = {
1447         .name = "pinctrl-u300",
1448         .id = -1,
1449         .num_resources = ARRAY_SIZE(pinctrl_resources),
1450         .resource = pinctrl_resources,
1451 };
1452
1453 /*
1454  * The different variants have a few different versions of the
1455  * GPIO block, with different number of ports.
1456  */
1457 static struct u300_gpio_platform u300_gpio_plat = {
1458         .ports = 7,
1459         .gpio_base = 0,
1460         .gpio_irq_base = IRQ_U300_GPIO_BASE,
1461         .pinctrl_device = &pinctrl_device,
1462 };
1463
1464 static struct platform_device gpio_device = {
1465         .name = "u300-gpio",
1466         .id = -1,
1467         .num_resources = ARRAY_SIZE(gpio_resources),
1468         .resource = gpio_resources,
1469         .dev = {
1470                 .platform_data = &u300_gpio_plat,
1471         },
1472 };
1473
1474 static struct platform_device keypad_device = {
1475         .name = "keypad",
1476         .id = -1,
1477         .num_resources = ARRAY_SIZE(keypad_resources),
1478         .resource = keypad_resources,
1479 };
1480
1481 static struct platform_device rtc_device = {
1482         .name = "rtc-coh901331",
1483         .id = -1,
1484         .num_resources = ARRAY_SIZE(rtc_resources),
1485         .resource = rtc_resources,
1486 };
1487
1488 static struct mtd_partition u300_partitions[] = {
1489         {
1490                 .name = "bootrecords",
1491                 .offset = 0,
1492                 .size = SZ_128K,
1493         },
1494         {
1495                 .name = "free",
1496                 .offset = SZ_128K,
1497                 .size = 8064 * SZ_1K,
1498         },
1499         {
1500                 .name = "platform",
1501                 .offset = 8192 * SZ_1K,
1502                 .size = 253952 * SZ_1K,
1503         },
1504 };
1505
1506 static struct fsmc_nand_platform_data nand_platform_data = {
1507         .partitions = u300_partitions,
1508         .nr_partitions = ARRAY_SIZE(u300_partitions),
1509         .options = NAND_SKIP_BBTSCAN,
1510         .width = FSMC_NAND_BW8,
1511 };
1512
1513 static struct platform_device nand_device = {
1514         .name = "fsmc-nand",
1515         .id = -1,
1516         .resource = fsmc_resources,
1517         .num_resources = ARRAY_SIZE(fsmc_resources),
1518         .dev = {
1519                 .platform_data = &nand_platform_data,
1520         },
1521 };
1522
1523 static struct platform_device dma_device = {
1524         .name           = "coh901318",
1525         .id             = -1,
1526         .resource       = dma_resource,
1527         .num_resources  = ARRAY_SIZE(dma_resource),
1528         .dev = {
1529                 .platform_data = &coh901318_platform,
1530                 .coherent_dma_mask = ~0,
1531         },
1532 };
1533
1534 static unsigned long pin_pullup_conf[] = {
1535         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
1536 };
1537
1538 static unsigned long pin_highz_conf[] = {
1539         PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
1540 };
1541
1542 /* Pin control settings */
1543 static struct pinctrl_map __initdata u300_pinmux_map[] = {
1544         /* anonymous maps for chip power and EMIFs */
1545         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
1546         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
1547         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
1548         /* per-device maps for MMC/SD, SPI and UART */
1549         PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
1550         PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
1551         PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
1552         /* This pin is used for clock return rather than GPIO */
1553         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
1554                                     pin_pullup_conf),
1555         /* This pin is used for card detect */
1556         PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
1557                                     pin_highz_conf),
1558 };
1559
1560 struct u300_mux_hog {
1561         struct device *dev;
1562         struct pinctrl *p;
1563 };
1564
1565 static struct u300_mux_hog u300_mux_hogs[] = {
1566         {
1567                 .dev = &uart0_device.dev,
1568         },
1569         {
1570                 .dev = &mmcsd_device.dev,
1571         },
1572 };
1573
1574 static int __init u300_pinctrl_fetch(void)
1575 {
1576         int i;
1577
1578         for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1579                 struct pinctrl *p;
1580
1581                 p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
1582                 if (IS_ERR(p)) {
1583                         pr_err("u300: could not get pinmux hog for dev %s\n",
1584                                dev_name(u300_mux_hogs[i].dev));
1585                         continue;
1586                 }
1587                 u300_mux_hogs[i].p = p;
1588         }
1589         return 0;
1590 }
1591 subsys_initcall(u300_pinctrl_fetch);
1592
1593 /*
1594  * Notice that AMBA devices are initialized before platform devices.
1595  *
1596  */
1597 static struct platform_device *platform_devs[] __initdata = {
1598         &dma_device,
1599         &i2c0_device,
1600         &i2c1_device,
1601         &keypad_device,
1602         &rtc_device,
1603         &gpio_device,
1604         &nand_device,
1605         &wdog_device,
1606 };
1607
1608 /*
1609  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1610  * together so some interrupts are connected to the first one and some
1611  * to the second one.
1612  */
1613 static void __init u300_init_irq(void)
1614 {
1615         u32 mask[2] = {0, 0};
1616         struct clk *clk;
1617         int i;
1618
1619         /* initialize clocking early, we want to clock the INTCON */
1620         u300_clk_init(U300_SYSCON_VBASE);
1621
1622         /* Bootstrap EMIF and SEMI clocks */
1623         clk = clk_get_sys("pl172", NULL);
1624         BUG_ON(IS_ERR(clk));
1625         clk_prepare_enable(clk);
1626         clk = clk_get_sys("semi", NULL);
1627         BUG_ON(IS_ERR(clk));
1628         clk_prepare_enable(clk);
1629
1630         /* Clock the interrupt controller */
1631         clk = clk_get_sys("intcon", NULL);
1632         BUG_ON(IS_ERR(clk));
1633         clk_prepare_enable(clk);
1634
1635         for (i = 0; i < U300_VIC_IRQS_END; i++)
1636                 set_bit(i, (unsigned long *) &mask[0]);
1637         vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
1638                  mask[0], mask[0]);
1639         vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
1640                  mask[1], mask[1]);
1641 }
1642
1643
1644 /*
1645  * U300 platforms peripheral handling
1646  */
1647 struct db_chip {
1648         u16 chipid;
1649         const char *name;
1650 };
1651
1652 /*
1653  * This is a list of the Digital Baseband chips used in the U300 platform.
1654  */
1655 static struct db_chip db_chips[] __initdata = {
1656         {
1657                 .chipid = 0xb800,
1658                 .name = "DB3000",
1659         },
1660         {
1661                 .chipid = 0xc000,
1662                 .name = "DB3100",
1663         },
1664         {
1665                 .chipid = 0xc800,
1666                 .name = "DB3150",
1667         },
1668         {
1669                 .chipid = 0xd800,
1670                 .name = "DB3200",
1671         },
1672         {
1673                 .chipid = 0xe000,
1674                 .name = "DB3250",
1675         },
1676         {
1677                 .chipid = 0xe800,
1678                 .name = "DB3210",
1679         },
1680         {
1681                 .chipid = 0xf000,
1682                 .name = "DB3350 P1x",
1683         },
1684         {
1685                 .chipid = 0xf100,
1686                 .name = "DB3350 P2x",
1687         },
1688         {
1689                 .chipid = 0x0000, /* List terminator */
1690                 .name = NULL,
1691         }
1692 };
1693
1694 static void __init u300_init_check_chip(void)
1695 {
1696
1697         u16 val;
1698         struct db_chip *chip;
1699         const char *chipname;
1700         const char unknown[] = "UNKNOWN";
1701
1702         /* Read out and print chip ID */
1703         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1704         /* This is in funky bigendian order... */
1705         val = (val & 0xFFU) << 8 | (val >> 8);
1706         chip = db_chips;
1707         chipname = unknown;
1708
1709         for ( ; chip->chipid; chip++) {
1710                 if (chip->chipid == (val & 0xFF00U)) {
1711                         chipname = chip->name;
1712                         break;
1713                 }
1714         }
1715         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1716                "(chip ID 0x%04x)\n", chipname, val);
1717
1718         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1719                 printk(KERN_ERR "Platform configured for BS335 " \
1720                        " with DB3350 but %s detected, expect problems!",
1721                        chipname);
1722         }
1723 }
1724
1725 /*
1726  * Some devices and their resources require reserved physical memory from
1727  * the end of the available RAM. This function traverses the list of devices
1728  * and assigns actual addresses to these.
1729  */
1730 static void __init u300_assign_physmem(void)
1731 {
1732         unsigned long curr_start = __pa(high_memory);
1733         int i, j;
1734
1735         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1736                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1737                         struct resource *const res =
1738                           &platform_devs[i]->resource[j];
1739
1740                         if (IORESOURCE_MEM == res->flags &&
1741                                      0 == res->start) {
1742                                 res->start  = curr_start;
1743                                 res->end   += curr_start;
1744                                 curr_start += resource_size(res);
1745
1746                                 printk(KERN_INFO "core.c: Mapping RAM " \
1747                                        "%#x-%#x to device %s:%s\n",
1748                                         res->start, res->end,
1749                                        platform_devs[i]->name, res->name);
1750                         }
1751                 }
1752         }
1753 }
1754
1755 static void __init u300_init_machine(void)
1756 {
1757         int i;
1758         u16 val;
1759
1760         /* Check what platform we run and print some status information */
1761         u300_init_check_chip();
1762
1763         /* Initialize SPI device with some board specifics */
1764         u300_spi_init(&pl022_device);
1765
1766         /* Register the AMBA devices in the AMBA bus abstraction layer */
1767         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1768                 struct amba_device *d = amba_devs[i];
1769                 amba_device_register(d, &iomem_resource);
1770         }
1771
1772         u300_assign_physmem();
1773
1774         /* Initialize pinmuxing */
1775         pinctrl_register_mappings(u300_pinmux_map,
1776                                   ARRAY_SIZE(u300_pinmux_map));
1777
1778         /* Register subdevices on the I2C buses */
1779         u300_i2c_register_board_devices();
1780
1781         /* Register the platform devices */
1782         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1783
1784         /* Register subdevices on the SPI bus */
1785         u300_spi_register_board_devices();
1786
1787         /* Enable SEMI self refresh */
1788         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1789                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1790         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1791 }
1792
1793 /* Forward declare this function from the watchdog */
1794 void coh901327_watchdog_reset(void);
1795
1796 static void u300_restart(char mode, const char *cmd)
1797 {
1798         switch (mode) {
1799         case 's':
1800         case 'h':
1801 #ifdef CONFIG_COH901327_WATCHDOG
1802                 coh901327_watchdog_reset();
1803 #endif
1804                 break;
1805         default:
1806                 /* Do nothing */
1807                 break;
1808         }
1809         /* Wait for system do die/reset. */
1810         while (1);
1811 }
1812
1813 MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
1814         /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
1815         .atag_offset    = 0x100,
1816         .map_io         = u300_map_io,
1817         .nr_irqs        = NR_IRQS_U300,
1818         .init_irq       = u300_init_irq,
1819         .handle_irq     = vic_handle_irq,
1820         .timer          = &u300_timer,
1821         .init_machine   = u300_init_machine,
1822         .restart        = u300_restart,
1823 MACHINE_END