2 * arch/arm/mm/proc-v7-2level.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define TTB_S (1 << 1)
12 #define TTB_RGN_NC (0 << 3)
13 #define TTB_RGN_OC_WBWA (1 << 3)
14 #define TTB_RGN_OC_WT (2 << 3)
15 #define TTB_RGN_OC_WB (3 << 3)
16 #define TTB_NOS (1 << 5)
17 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
18 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
19 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
20 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
22 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
23 #define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
24 #define PMD_FLAGS_UP PMD_SECT_WB
26 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
27 #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
28 #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
31 * cpu_v7_switch_mm(pgd_phys, tsk)
33 * Set the translation table base pointer to be pgd_phys
35 * - pgd_phys - physical address of new TTB
38 * - we are not using split page tables
40 ENTRY(cpu_v7_switch_mm)
43 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
44 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
45 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
46 #ifdef CONFIG_ARM_ERRATA_430973
47 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
49 #ifdef CONFIG_PID_IN_CONTEXTIDR
50 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
51 lsr r2, r2, #8 @ extract the PID
52 bfi r1, r2, #8, #24 @ insert into new context ID
54 #ifdef CONFIG_ARM_ERRATA_754322
57 mcr p15, 0, r1, c13, c0, 1 @ set context ID
59 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
63 ENDPROC(cpu_v7_switch_mm)
66 * cpu_v7_set_pte_ext(ptep, pte)
68 * Set a level 2 translation table entry.
70 * - ptep - pointer to level 2 translation table entry
71 * (hardware version is stored at +2048 bytes)
72 * - pte - PTE value to store
73 * - ext - value for extended PTE bits
75 ENTRY(cpu_v7_set_pte_ext)
77 str r1, [r0] @ linux version
79 bic r3, r1, #0x000003f0
80 bic r3, r3, #PTE_TYPE_MASK
82 orr r3, r3, #PTE_EXT_AP0 | 2
85 orrne r3, r3, #PTE_EXT_TEX(1)
87 eor r1, r1, #L_PTE_DIRTY
88 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
89 orrne r3, r3, #PTE_EXT_APX
92 orrne r3, r3, #PTE_EXT_AP1
93 #ifdef CONFIG_CPU_USE_DOMAINS
94 @ allow kernel read/write access to read-only user pages
95 tstne r3, #PTE_EXT_APX
96 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
100 orrne r3, r3, #PTE_EXT_XN
103 tstne r1, #L_PTE_VALID
104 #ifndef CONFIG_CPU_USE_DOMAINS
105 eorne r1, r1, #L_PTE_NONE
106 tstne r1, #L_PTE_NONE
110 ARM( str r3, [r0, #2048]! )
111 THUMB( add r0, r0, #2048 )
112 THUMB( str r3, [r0] )
113 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
116 ENDPROC(cpu_v7_set_pte_ext)
119 * Memory region attributes with SCTLR.TRE=1
122 * TR = PRRR[2n+1:2n] - memory type
123 * IR = NMRR[2n+1:2n] - inner cacheable property
124 * OR = NMRR[2n+17:2n+16] - outer cacheable property
128 * BUFFERABLE 001 10 00 00
129 * WRITETHROUGH 010 10 10 10
130 * WRITEBACK 011 10 11 11
132 * WRITEALLOC 111 10 01 01
134 * DEV_NONSHARED 100 01
140 * DS0 = PRRR[16] = 0 - device shareable property
141 * DS1 = PRRR[17] = 1 - device shareable property
142 * NS0 = PRRR[18] = 0 - normal shareable property
143 * NS1 = PRRR[19] = 1 - normal shareable property
144 * NOS = PRRR[24+n] = 1 - not outer shareable
146 .equ PRRR, 0xff0a81a8
147 .equ NMRR, 0x40e040e0
150 * Macro for setting up the TTBRx and TTBCR registers.
151 * - \ttb0 and \ttb1 updated with the corresponding flags.
153 .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp
154 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
155 ALT_SMP(orr \ttbr0, \ttbr0, #TTB_FLAGS_SMP)
156 ALT_UP(orr \ttbr0, \ttbr0, #TTB_FLAGS_UP)
157 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
158 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
159 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
165 * TFR EV X F I D LR S
166 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
167 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
168 * 01 0 110 0011 1100 .111 1101 < we want
171 .type v7_crval, #object
173 crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c