2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_pci.h>
33 #include <linux/pci.h>
34 #include <linux/export.h>
36 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
41 static DEFINE_SPINLOCK(hose_spinlock);
44 /* XXX kill that some day ... */
45 static int global_phb_number; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base;
50 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
52 unsigned long isa_io_base;
53 unsigned long pci_dram_offset;
54 static int pci_bus_count;
57 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
59 pci_dma_ops = dma_ops;
62 struct dma_map_ops *get_pci_dma_ops(void)
66 EXPORT_SYMBOL(get_pci_dma_ops);
68 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
70 struct pci_controller *phb;
72 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
75 spin_lock(&hose_spinlock);
76 phb->global_number = global_phb_number++;
77 list_add_tail(&phb->list_node, &hose_list);
78 spin_unlock(&hose_spinlock);
80 phb->is_dynamic = mem_init_done;
84 void pcibios_free_controller(struct pci_controller *phb)
86 spin_lock(&hose_spinlock);
87 list_del(&phb->list_node);
88 spin_unlock(&hose_spinlock);
94 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
96 return resource_size(&hose->io_resource);
99 int pcibios_vaddr_is_ioport(void __iomem *address)
102 struct pci_controller *hose;
103 resource_size_t size;
105 spin_lock(&hose_spinlock);
106 list_for_each_entry(hose, &hose_list, list_node) {
107 size = pcibios_io_size(hose);
108 if (address >= hose->io_base_virt &&
109 address < (hose->io_base_virt + size)) {
114 spin_unlock(&hose_spinlock);
118 unsigned long pci_address_to_pio(phys_addr_t address)
120 struct pci_controller *hose;
121 resource_size_t size;
122 unsigned long ret = ~0;
124 spin_lock(&hose_spinlock);
125 list_for_each_entry(hose, &hose_list, list_node) {
126 size = pcibios_io_size(hose);
127 if (address >= hose->io_base_phys &&
128 address < (hose->io_base_phys + size)) {
130 (unsigned long)hose->io_base_virt - _IO_BASE;
131 ret = base + (address - hose->io_base_phys);
135 spin_unlock(&hose_spinlock);
139 EXPORT_SYMBOL_GPL(pci_address_to_pio);
142 * Return the domain number for this bus.
144 int pci_domain_nr(struct pci_bus *bus)
146 struct pci_controller *hose = pci_bus_to_host(bus);
148 return hose->global_number;
150 EXPORT_SYMBOL(pci_domain_nr);
152 /* This routine is meant to be used early during boot, when the
153 * PCI bus numbers have not yet been assigned, and you need to
154 * issue PCI config cycles to an OF device.
155 * It could also be used to "fix" RTAS config cycles if you want
156 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
159 struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
162 struct pci_controller *hose, *tmp;
163 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
164 if (hose->dn == node)
171 static ssize_t pci_show_devspec(struct device *dev,
172 struct device_attribute *attr, char *buf)
174 struct pci_dev *pdev;
175 struct device_node *np;
177 pdev = to_pci_dev(dev);
178 np = pci_device_to_OF_node(pdev);
179 if (np == NULL || np->full_name == NULL)
181 return sprintf(buf, "%s", np->full_name);
183 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
185 /* Add sysfs properties */
186 int pcibios_add_platform_entries(struct pci_dev *pdev)
188 return device_create_file(&pdev->dev, &dev_attr_devspec);
191 void pcibios_set_master(struct pci_dev *dev)
193 /* No special bus mastering setup handling */
197 * Reads the interrupt pin to determine if interrupt is use by card.
198 * If the interrupt is used, then gets the interrupt line from the
199 * openfirmware and sets it in the pci_dev and pci_config line.
201 int pci_read_irq_line(struct pci_dev *pci_dev)
206 /* The current device-tree that iSeries generates from the HV
207 * PCI informations doesn't contain proper interrupt routing,
208 * and all the fallback would do is print out crap, so we
209 * don't attempt to resolve the interrupts here at all, some
210 * iSeries specific fixup does it.
212 * In the long run, we will hopefully fix the generated device-tree
215 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
218 memset(&oirq, 0xff, sizeof(oirq));
220 /* Try to get a mapping from the device-tree */
221 if (of_irq_map_pci(pci_dev, &oirq)) {
224 /* If that fails, lets fallback to what is in the config
225 * space and map that through the default controller. We
226 * also set the type to level low since that's what PCI
227 * interrupts are. If your platform does differently, then
228 * either provide a proper interrupt tree or don't use this
231 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
235 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
236 line == 0xff || line == 0) {
239 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
242 virq = irq_create_mapping(NULL, line);
244 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
246 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
247 oirq.size, oirq.specifier[0], oirq.specifier[1],
248 of_node_full_name(oirq.controller));
250 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
254 pr_debug(" Failed to map !\n");
258 pr_debug(" Mapped to linux irq %d\n", virq);
264 EXPORT_SYMBOL(pci_read_irq_line);
267 * Platform support for /proc/bus/pci/X/Y mmap()s,
268 * modelled on the sparc64 implementation by Dave Miller.
273 * Adjust vm_pgoff of VMA such that it is the physical page offset
274 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
276 * Basically, the user finds the base address for his device which he wishes
277 * to mmap. They read the 32-bit value from the config space base register,
278 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
279 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
281 * Returns negative error code on failure, zero on success.
283 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
284 resource_size_t *offset,
285 enum pci_mmap_state mmap_state)
287 struct pci_controller *hose = pci_bus_to_host(dev->bus);
288 unsigned long io_offset = 0;
292 return NULL; /* should never happen */
294 /* If memory, add on the PCI bridge address offset */
295 if (mmap_state == pci_mmap_mem) {
296 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
297 *offset += hose->pci_mem_offset;
299 res_bit = IORESOURCE_MEM;
301 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
302 *offset += io_offset;
303 res_bit = IORESOURCE_IO;
307 * Check that the offset requested corresponds to one of the
308 * resources of the device.
310 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
311 struct resource *rp = &dev->resource[i];
312 int flags = rp->flags;
314 /* treat ROM as memory (should be already) */
315 if (i == PCI_ROM_RESOURCE)
316 flags |= IORESOURCE_MEM;
318 /* Active and same type? */
319 if ((flags & res_bit) == 0)
322 /* In the range of this resource? */
323 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
326 /* found it! construct the final physical address */
327 if (mmap_state == pci_mmap_io)
328 *offset += hose->io_base_phys - io_offset;
336 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
339 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
341 enum pci_mmap_state mmap_state,
344 pgprot_t prot = protection;
346 /* Write combine is always 0 on non-memory space mappings. On
347 * memory space, if the user didn't pass 1, we check for a
348 * "prefetchable" resource. This is a bit hackish, but we use
349 * this to workaround the inability of /sysfs to provide a write
352 if (mmap_state != pci_mmap_mem)
354 else if (write_combine == 0) {
355 if (rp->flags & IORESOURCE_PREFETCH)
359 return pgprot_noncached(prot);
363 * This one is used by /dev/mem and fbdev who have no clue about the
364 * PCI device, it tries to find the PCI device first and calls the
367 pgprot_t pci_phys_mem_access_prot(struct file *file,
372 struct pci_dev *pdev = NULL;
373 struct resource *found = NULL;
374 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
377 if (page_is_ram(pfn))
380 prot = pgprot_noncached(prot);
381 for_each_pci_dev(pdev) {
382 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
383 struct resource *rp = &pdev->resource[i];
384 int flags = rp->flags;
386 /* Active and same type? */
387 if ((flags & IORESOURCE_MEM) == 0)
389 /* In the range of this resource? */
390 if (offset < (rp->start & PAGE_MASK) ||
400 if (found->flags & IORESOURCE_PREFETCH)
401 prot = pgprot_noncached_wc(prot);
405 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
406 (unsigned long long)offset, pgprot_val(prot));
412 * Perform the actual remap of the pages for a PCI device mapping, as
413 * appropriate for this architecture. The region in the process to map
414 * is described by vm_start and vm_end members of VMA, the base physical
415 * address is found in vm_pgoff.
416 * The pci device structure is provided so that architectures may make mapping
417 * decisions on a per-device or per-bus basis.
419 * Returns a negative error code on failure, zero on success.
421 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
422 enum pci_mmap_state mmap_state, int write_combine)
424 resource_size_t offset =
425 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
429 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
433 vma->vm_pgoff = offset >> PAGE_SHIFT;
434 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
436 mmap_state, write_combine);
438 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
439 vma->vm_end - vma->vm_start, vma->vm_page_prot);
444 /* This provides legacy IO read access on a bus */
445 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
447 unsigned long offset;
448 struct pci_controller *hose = pci_bus_to_host(bus);
449 struct resource *rp = &hose->io_resource;
452 /* Check if port can be supported by that bus. We only check
453 * the ranges of the PHB though, not the bus itself as the rules
454 * for forwarding legacy cycles down bridges are not our problem
455 * here. So if the host bridge supports it, we do it.
457 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
460 if (!(rp->flags & IORESOURCE_IO))
462 if (offset < rp->start || (offset + size) > rp->end)
464 addr = hose->io_base_virt + port;
468 *((u8 *)val) = in_8(addr);
473 *((u16 *)val) = in_le16(addr);
478 *((u32 *)val) = in_le32(addr);
484 /* This provides legacy IO write access on a bus */
485 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
487 unsigned long offset;
488 struct pci_controller *hose = pci_bus_to_host(bus);
489 struct resource *rp = &hose->io_resource;
492 /* Check if port can be supported by that bus. We only check
493 * the ranges of the PHB though, not the bus itself as the rules
494 * for forwarding legacy cycles down bridges are not our problem
495 * here. So if the host bridge supports it, we do it.
497 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
500 if (!(rp->flags & IORESOURCE_IO))
502 if (offset < rp->start || (offset + size) > rp->end)
504 addr = hose->io_base_virt + port;
506 /* WARNING: The generic code is idiotic. It gets passed a pointer
507 * to what can be a 1, 2 or 4 byte quantity and always reads that
508 * as a u32, which means that we have to correct the location of
509 * the data read within those 32 bits for size 1 and 2
513 out_8(addr, val >> 24);
518 out_le16(addr, val >> 16);
529 /* This provides legacy IO or memory mmap access on a bus */
530 int pci_mmap_legacy_page_range(struct pci_bus *bus,
531 struct vm_area_struct *vma,
532 enum pci_mmap_state mmap_state)
534 struct pci_controller *hose = pci_bus_to_host(bus);
535 resource_size_t offset =
536 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
537 resource_size_t size = vma->vm_end - vma->vm_start;
540 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
541 pci_domain_nr(bus), bus->number,
542 mmap_state == pci_mmap_mem ? "MEM" : "IO",
543 (unsigned long long)offset,
544 (unsigned long long)(offset + size - 1));
546 if (mmap_state == pci_mmap_mem) {
549 * Because X is lame and can fail starting if it gets an error
550 * trying to mmap legacy_mem (instead of just moving on without
551 * legacy memory access) we fake it here by giving it anonymous
552 * memory, effectively behaving just like /dev/zero
554 if ((offset + size) > hose->isa_mem_size) {
556 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
557 current->comm, current->pid);
558 pr_debug("legacy memory for 0%04x:%02x\n",
559 pci_domain_nr(bus), bus->number);
561 if (vma->vm_flags & VM_SHARED)
562 return shmem_zero_setup(vma);
565 offset += hose->isa_mem_phys;
567 unsigned long io_offset = (unsigned long)hose->io_base_virt -
569 unsigned long roffset = offset + io_offset;
570 rp = &hose->io_resource;
571 if (!(rp->flags & IORESOURCE_IO))
573 if (roffset < rp->start || (roffset + size) > rp->end)
575 offset += hose->io_base_phys;
577 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
579 vma->vm_pgoff = offset >> PAGE_SHIFT;
580 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
581 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
582 vma->vm_end - vma->vm_start,
586 void pci_resource_to_user(const struct pci_dev *dev, int bar,
587 const struct resource *rsrc,
588 resource_size_t *start, resource_size_t *end)
590 struct pci_controller *hose = pci_bus_to_host(dev->bus);
591 resource_size_t offset = 0;
596 if (rsrc->flags & IORESOURCE_IO)
597 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
599 /* We pass a fully fixed up address to userland for MMIO instead of
600 * a BAR value because X is lame and expects to be able to use that
601 * to pass to /dev/mem !
603 * That means that we'll have potentially 64 bits values where some
604 * userland apps only expect 32 (like X itself since it thinks only
605 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
608 * Hopefully, the sysfs insterface is immune to that gunk. Once X
609 * has been fixed (and the fix spread enough), we can re-enable the
610 * 2 lines below and pass down a BAR value to userland. In that case
611 * we'll also have to re-enable the matching code in
612 * __pci_mmap_make_offset().
617 else if (rsrc->flags & IORESOURCE_MEM)
618 offset = hose->pci_mem_offset;
621 *start = rsrc->start - offset;
622 *end = rsrc->end - offset;
626 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
627 * @hose: newly allocated pci_controller to be setup
628 * @dev: device node of the host bridge
629 * @primary: set if primary bus (32 bits only, soon to be deprecated)
631 * This function will parse the "ranges" property of a PCI host bridge device
632 * node and setup the resource mapping of a pci controller based on its
635 * Life would be boring if it wasn't for a few issues that we have to deal
638 * - We can only cope with one IO space range and up to 3 Memory space
639 * ranges. However, some machines (thanks Apple !) tend to split their
640 * space into lots of small contiguous ranges. So we have to coalesce.
642 * - We can only cope with all memory ranges having the same offset
643 * between CPU addresses and PCI addresses. Unfortunately, some bridges
644 * are setup for a large 1:1 mapping along with a small "window" which
645 * maps PCI address 0 to some arbitrary high address of the CPU space in
646 * order to give access to the ISA memory hole.
647 * The way out of here that I've chosen for now is to always set the
648 * offset based on the first resource found, then override it if we
649 * have a different offset and the previous was set by an ISA hole.
651 * - Some busses have IO space not starting at 0, which causes trouble with
652 * the way we do our IO resource renumbering. The code somewhat deals with
653 * it for 64 bits but I would expect problems on 32 bits.
655 * - Some 32 bits platforms such as 4xx can have physical space larger than
656 * 32 bits so we need to use 64 bits values for the parsing
658 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
659 struct device_node *dev, int primary)
663 int pna = of_n_addr_cells(dev);
665 int memno = 0, isa_hole = -1;
667 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
668 unsigned long long isa_mb = 0;
669 struct resource *res;
671 pr_info("PCI host bridge %s %s ranges:\n",
672 dev->full_name, primary ? "(primary)" : "");
674 /* Get ranges property */
675 ranges = of_get_property(dev, "ranges", &rlen);
680 pr_debug("Parsing ranges property...\n");
681 while ((rlen -= np * 4) >= 0) {
682 /* Read next ranges element */
683 pci_space = ranges[0];
684 pci_addr = of_read_number(ranges + 1, 2);
685 cpu_addr = of_translate_address(dev, ranges + 3);
686 size = of_read_number(ranges + pna + 3, 2);
688 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
689 pci_space, pci_addr);
690 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
695 /* If we failed translation or got a zero-sized region
696 * (some FW try to feed us with non sensical zero sized regions
697 * such as power3 which look like some kind of attempt
698 * at exposing the VGA memory hole)
700 if (cpu_addr == OF_BAD_ADDR || size == 0)
703 /* Now consume following elements while they are contiguous */
704 for (; rlen >= np * sizeof(u32);
705 ranges += np, rlen -= np * 4) {
706 if (ranges[0] != pci_space)
708 pci_next = of_read_number(ranges + 1, 2);
709 cpu_next = of_translate_address(dev, ranges + 3);
710 if (pci_next != pci_addr + size ||
711 cpu_next != cpu_addr + size)
713 size += of_read_number(ranges + pna + 3, 2);
716 /* Act based on address space type */
718 switch ((pci_space >> 24) & 0x3) {
719 case 1: /* PCI IO space */
720 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
721 cpu_addr, cpu_addr + size - 1, pci_addr);
723 /* We support only one IO range */
724 if (hose->pci_io_size) {
725 pr_info(" \\--> Skipped (too many) !\n");
728 /* On 32 bits, limit I/O space to 16MB */
729 if (size > 0x01000000)
732 /* 32 bits needs to map IOs here */
733 hose->io_base_virt = ioremap(cpu_addr, size);
735 /* Expect trouble if pci_addr is not 0 */
738 (unsigned long)hose->io_base_virt;
739 /* pci_io_size and io_base_phys always represent IO
740 * space starting at 0 so we factor in pci_addr
742 hose->pci_io_size = pci_addr + size;
743 hose->io_base_phys = cpu_addr - pci_addr;
746 res = &hose->io_resource;
747 res->flags = IORESOURCE_IO;
748 res->start = pci_addr;
750 case 2: /* PCI Memory space */
751 case 3: /* PCI 64 bits Memory space */
752 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
753 cpu_addr, cpu_addr + size - 1, pci_addr,
754 (pci_space & 0x40000000) ? "Prefetch" : "");
756 /* We support only 3 memory ranges */
758 pr_info(" \\--> Skipped (too many) !\n");
761 /* Handles ISA memory hole space here */
765 if (primary || isa_mem_base == 0)
766 isa_mem_base = cpu_addr;
767 hose->isa_mem_phys = cpu_addr;
768 hose->isa_mem_size = size;
771 /* We get the PCI/Mem offset from the first range or
772 * the, current one if the offset came from an ISA
773 * hole. If they don't match, bugger.
776 (isa_hole >= 0 && pci_addr != 0 &&
777 hose->pci_mem_offset == isa_mb))
778 hose->pci_mem_offset = cpu_addr - pci_addr;
779 else if (pci_addr != 0 &&
780 hose->pci_mem_offset != cpu_addr - pci_addr) {
781 pr_info(" \\--> Skipped (offset mismatch) !\n");
786 res = &hose->mem_resources[memno++];
787 res->flags = IORESOURCE_MEM;
788 if (pci_space & 0x40000000)
789 res->flags |= IORESOURCE_PREFETCH;
790 res->start = cpu_addr;
794 res->name = dev->full_name;
795 res->end = res->start + size - 1;
802 /* If there's an ISA hole and the pci_mem_offset is -not- matching
803 * the ISA hole offset, then we need to remove the ISA hole from
804 * the resource list for that brige
806 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
807 unsigned int next = isa_hole + 1;
808 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
810 memmove(&hose->mem_resources[isa_hole],
811 &hose->mem_resources[next],
812 sizeof(struct resource) * (memno - next));
813 hose->mem_resources[--memno].flags = 0;
817 /* Decide whether to display the domain number in /proc */
818 int pci_proc_domain(struct pci_bus *bus)
823 /* This header fixup will do the resource fixup for all devices as they are
824 * probed, but not for bridge ranges
826 static void pcibios_fixup_resources(struct pci_dev *dev)
828 struct pci_controller *hose = pci_bus_to_host(dev->bus);
832 pr_err("No host bridge for PCI dev %s !\n",
836 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
837 struct resource *res = dev->resource + i;
840 if (res->start == 0) {
841 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
843 (unsigned long long)res->start,
844 (unsigned long long)res->end,
845 (unsigned int)res->flags);
846 pr_debug("is unassigned\n");
847 res->end -= res->start;
849 res->flags |= IORESOURCE_UNSET;
853 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
855 (unsigned long long)res->start,
856 (unsigned long long)res->end,
857 (unsigned int)res->flags);
860 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
862 /* This function tries to figure out if a bridge resource has been initialized
863 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
864 * things go more smoothly when it gets it right. It should covers cases such
865 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
867 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
868 struct resource *res)
870 struct pci_controller *hose = pci_bus_to_host(bus);
871 struct pci_dev *dev = bus->self;
872 resource_size_t offset;
876 /* Job is a bit different between memory and IO */
877 if (res->flags & IORESOURCE_MEM) {
878 /* If the BAR is non-0 (res != pci_mem_offset) then it's
879 * probably been initialized by somebody
881 if (res->start != hose->pci_mem_offset)
884 /* The BAR is 0, let's check if memory decoding is enabled on
885 * the bridge. If not, we consider it unassigned
887 pci_read_config_word(dev, PCI_COMMAND, &command);
888 if ((command & PCI_COMMAND_MEMORY) == 0)
891 /* Memory decoding is enabled and the BAR is 0. If any of
892 * the bridge resources covers that starting address (0 then
893 * it's good enough for us for memory
895 for (i = 0; i < 3; i++) {
896 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
897 hose->mem_resources[i].start == hose->pci_mem_offset)
901 /* Well, it starts at 0 and we know it will collide so we may as
902 * well consider it as unassigned. That covers the Apple case.
906 /* If the BAR is non-0, then we consider it assigned */
907 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
908 if (((res->start - offset) & 0xfffffffful) != 0)
911 /* Here, we are a bit different than memory as typically IO
912 * space starting at low addresses -is- valid. What we do
913 * instead if that we consider as unassigned anything that
914 * doesn't have IO enabled in the PCI command register,
917 pci_read_config_word(dev, PCI_COMMAND, &command);
918 if (command & PCI_COMMAND_IO)
921 /* It's starting at 0 and IO is disabled in the bridge, consider
928 /* Fixup resources of a PCI<->PCI bridge */
929 static void pcibios_fixup_bridge(struct pci_bus *bus)
931 struct resource *res;
934 struct pci_dev *dev = bus->self;
936 pci_bus_for_each_resource(bus, res, i) {
941 if (i >= 3 && bus->self->transparent)
944 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
946 (unsigned long long)res->start,
947 (unsigned long long)res->end,
948 (unsigned int)res->flags);
950 /* Try to detect uninitialized P2P bridge resources,
951 * and clear them out so they get re-assigned later
953 if (pcibios_uninitialized_bridge_resource(bus, res)) {
955 pr_debug("PCI:%s (unassigned)\n",
958 pr_debug("PCI:%s %016llx-%016llx\n",
960 (unsigned long long)res->start,
961 (unsigned long long)res->end);
966 void pcibios_setup_bus_self(struct pci_bus *bus)
968 /* Fix up the bus resources for P2P bridges */
969 if (bus->self != NULL)
970 pcibios_fixup_bridge(bus);
973 void pcibios_setup_bus_devices(struct pci_bus *bus)
977 pr_debug("PCI: Fixup bus devices %d (%s)\n",
978 bus->number, bus->self ? pci_name(bus->self) : "PHB");
980 list_for_each_entry(dev, &bus->devices, bus_list) {
981 /* Setup OF node pointer in archdata */
982 dev->dev.of_node = pci_device_to_OF_node(dev);
984 /* Fixup NUMA node as it may not be setup yet by the generic
985 * code and is needed by the DMA init
987 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
989 /* Hook up default DMA ops */
990 set_dma_ops(&dev->dev, pci_dma_ops);
991 dev->dev.archdata.dma_data = (void *)PCI_DRAM_OFFSET;
993 /* Read default IRQs and fixup if necessary */
994 pci_read_irq_line(dev);
998 void pcibios_fixup_bus(struct pci_bus *bus)
1000 /* When called from the generic PCI probe, read PCI<->PCI bridge
1001 * bases. This is -not- called when generating the PCI tree from
1002 * the OF device-tree.
1004 if (bus->self != NULL)
1005 pci_read_bridge_bases(bus);
1007 /* Now fixup the bus bus */
1008 pcibios_setup_bus_self(bus);
1010 /* Now fixup devices on that bus */
1011 pcibios_setup_bus_devices(bus);
1013 EXPORT_SYMBOL(pcibios_fixup_bus);
1015 static int skip_isa_ioresource_align(struct pci_dev *dev)
1021 * We need to avoid collisions with `mirrored' VGA ports
1022 * and other strange ISA hardware, so we always want the
1023 * addresses to be allocated in the 0x000-0x0ff region
1026 * Why? Because some silly external IO cards only decode
1027 * the low 10 bits of the IO address. The 0x00-0xff region
1028 * is reserved for motherboard devices that decode all 16
1029 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1030 * but we want to try to avoid allocating at 0x2900-0x2bff
1031 * which might have be mirrored at 0x0100-0x03ff..
1033 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1034 resource_size_t size, resource_size_t align)
1036 struct pci_dev *dev = data;
1037 resource_size_t start = res->start;
1039 if (res->flags & IORESOURCE_IO) {
1040 if (skip_isa_ioresource_align(dev))
1043 start = (start + 0x3ff) & ~0x3ff;
1048 EXPORT_SYMBOL(pcibios_align_resource);
1051 * Reparent resource children of pr that conflict with res
1052 * under res, and make res replace those children.
1054 static int __init reparent_resources(struct resource *parent,
1055 struct resource *res)
1057 struct resource *p, **pp;
1058 struct resource **firstpp = NULL;
1060 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1061 if (p->end < res->start)
1063 if (res->end < p->start)
1065 if (p->start < res->start || p->end > res->end)
1066 return -1; /* not completely contained */
1067 if (firstpp == NULL)
1070 if (firstpp == NULL)
1071 return -1; /* didn't find any conflicting entries? */
1072 res->parent = parent;
1073 res->child = *firstpp;
1077 for (p = res->child; p != NULL; p = p->sibling) {
1079 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1081 (unsigned long long)p->start,
1082 (unsigned long long)p->end, res->name);
1088 * Handle resources of PCI devices. If the world were perfect, we could
1089 * just allocate all the resource regions and do nothing more. It isn't.
1090 * On the other hand, we cannot just re-allocate all devices, as it would
1091 * require us to know lots of host bridge internals. So we attempt to
1092 * keep as much of the original configuration as possible, but tweak it
1093 * when it's found to be wrong.
1095 * Known BIOS problems we have to work around:
1096 * - I/O or memory regions not configured
1097 * - regions configured, but not enabled in the command register
1098 * - bogus I/O addresses above 64K used
1099 * - expansion ROMs left enabled (this may sound harmless, but given
1100 * the fact the PCI specs explicitly allow address decoders to be
1101 * shared between expansion ROMs and other resource regions, it's
1102 * at least dangerous)
1105 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1106 * This gives us fixed barriers on where we can allocate.
1107 * (2) Allocate resources for all enabled devices. If there is
1108 * a collision, just mark the resource as unallocated. Also
1109 * disable expansion ROMs during this step.
1110 * (3) Try to allocate resources for disabled devices. If the
1111 * resources were assigned correctly, everything goes well,
1112 * if they weren't, they won't disturb allocation of other
1114 * (4) Assign new addresses to resources which were either
1115 * not configured at all or misconfigured. If explicitly
1116 * requested by the user, configure expansion ROM address
1120 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1124 struct resource *res, *pr;
1126 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1127 pci_domain_nr(bus), bus->number);
1129 pci_bus_for_each_resource(bus, res, i) {
1130 if (!res || !res->flags
1131 || res->start > res->end || res->parent)
1133 if (bus->parent == NULL)
1134 pr = (res->flags & IORESOURCE_IO) ?
1135 &ioport_resource : &iomem_resource;
1137 /* Don't bother with non-root busses when
1138 * re-assigning all resources. We clear the
1139 * resource flags as if they were colliding
1140 * and as such ensure proper re-allocation
1143 pr = pci_find_parent_resource(bus->self, res);
1145 /* this happens when the generic PCI
1146 * code (wrongly) decides that this
1147 * bridge is transparent -- paulus
1153 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
1154 bus->self ? pci_name(bus->self) : "PHB",
1156 (unsigned long long)res->start,
1157 (unsigned long long)res->end);
1158 pr_debug("[0x%x], parent %p (%s)\n",
1159 (unsigned int)res->flags,
1160 pr, (pr && pr->name) ? pr->name : "nil");
1162 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1163 if (request_resource(pr, res) == 0)
1166 * Must be a conflict with an existing entry.
1167 * Move that entry (or entries) under the
1168 * bridge resource and try again.
1170 if (reparent_resources(pr, res) == 0)
1173 pr_warn("PCI: Cannot allocate resource region ");
1174 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
1175 res->start = res->end = 0;
1179 list_for_each_entry(b, &bus->children, node)
1180 pcibios_allocate_bus_resources(b);
1183 static inline void alloc_resource(struct pci_dev *dev, int idx)
1185 struct resource *pr, *r = &dev->resource[idx];
1187 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1189 (unsigned long long)r->start,
1190 (unsigned long long)r->end,
1191 (unsigned int)r->flags);
1193 pr = pci_find_parent_resource(dev, r);
1194 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1195 request_resource(pr, r) < 0) {
1196 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1197 pr_cont("of device %s, will remap\n", pci_name(dev));
1199 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1201 (unsigned long long)pr->start,
1202 (unsigned long long)pr->end,
1203 (unsigned int)pr->flags);
1204 /* We'll assign a new address later */
1205 r->flags |= IORESOURCE_UNSET;
1211 static void __init pcibios_allocate_resources(int pass)
1213 struct pci_dev *dev = NULL;
1218 for_each_pci_dev(dev) {
1219 pci_read_config_word(dev, PCI_COMMAND, &command);
1220 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1221 r = &dev->resource[idx];
1222 if (r->parent) /* Already allocated */
1224 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1225 continue; /* Not assigned at all */
1226 /* We only allocate ROMs on pass 1 just in case they
1227 * have been screwed up by firmware
1229 if (idx == PCI_ROM_RESOURCE)
1231 if (r->flags & IORESOURCE_IO)
1232 disabled = !(command & PCI_COMMAND_IO);
1234 disabled = !(command & PCI_COMMAND_MEMORY);
1235 if (pass == disabled)
1236 alloc_resource(dev, idx);
1240 r = &dev->resource[PCI_ROM_RESOURCE];
1242 /* Turn the ROM off, leave the resource region,
1243 * but keep it unregistered.
1246 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1247 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1248 pr_debug("PCI: Switching off ROM of %s\n",
1250 r->flags &= ~IORESOURCE_ROM_ENABLE;
1251 pci_write_config_dword(dev, dev->rom_base_reg,
1252 reg & ~PCI_ROM_ADDRESS_ENABLE);
1258 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1260 struct pci_controller *hose = pci_bus_to_host(bus);
1261 resource_size_t offset;
1262 struct resource *res, *pres;
1265 pr_debug("Reserving legacy ranges for domain %04x\n",
1266 pci_domain_nr(bus));
1269 if (!(hose->io_resource.flags & IORESOURCE_IO))
1271 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1272 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1273 BUG_ON(res == NULL);
1274 res->name = "Legacy IO";
1275 res->flags = IORESOURCE_IO;
1276 res->start = offset;
1277 res->end = (offset + 0xfff) & 0xfffffffful;
1278 pr_debug("Candidate legacy IO: %pR\n", res);
1279 if (request_resource(&hose->io_resource, res)) {
1280 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1281 pci_domain_nr(bus), bus->number, res);
1286 /* Check for memory */
1287 offset = hose->pci_mem_offset;
1288 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1289 for (i = 0; i < 3; i++) {
1290 pres = &hose->mem_resources[i];
1291 if (!(pres->flags & IORESOURCE_MEM))
1293 pr_debug("hose mem res: %pR\n", pres);
1294 if ((pres->start - offset) <= 0xa0000 &&
1295 (pres->end - offset) >= 0xbffff)
1300 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1301 BUG_ON(res == NULL);
1302 res->name = "Legacy VGA memory";
1303 res->flags = IORESOURCE_MEM;
1304 res->start = 0xa0000 + offset;
1305 res->end = 0xbffff + offset;
1306 pr_debug("Candidate VGA memory: %pR\n", res);
1307 if (request_resource(pres, res)) {
1308 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1309 pci_domain_nr(bus), bus->number, res);
1314 void __init pcibios_resource_survey(void)
1318 /* Allocate and assign resources. If we re-assign everything, then
1319 * we skip the allocate phase
1321 list_for_each_entry(b, &pci_root_buses, node)
1322 pcibios_allocate_bus_resources(b);
1324 pcibios_allocate_resources(0);
1325 pcibios_allocate_resources(1);
1327 /* Before we start assigning unassigned resource, we try to reserve
1328 * the low IO area and the VGA memory area if they intersect the
1329 * bus available resources to avoid allocating things on top of them
1331 list_for_each_entry(b, &pci_root_buses, node)
1332 pcibios_reserve_legacy_regions(b);
1334 /* Now proceed to assigning things that were left unassigned */
1335 pr_debug("PCI: Assigning unassigned resources...\n");
1336 pci_assign_unassigned_resources();
1339 /* This is used by the PCI hotplug driver to allocate resource
1340 * of newly plugged busses. We can try to consolidate with the
1341 * rest of the code later, for now, keep it as-is as our main
1342 * resource allocation function doesn't deal with sub-trees yet.
1344 void pcibios_claim_one_bus(struct pci_bus *bus)
1346 struct pci_dev *dev;
1347 struct pci_bus *child_bus;
1349 list_for_each_entry(dev, &bus->devices, bus_list) {
1352 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1353 struct resource *r = &dev->resource[i];
1355 if (r->parent || !r->start || !r->flags)
1358 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1359 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1360 i, (unsigned long long)r->start,
1361 (unsigned long long)r->end,
1362 (unsigned int)r->flags);
1364 pci_claim_resource(dev, i);
1368 list_for_each_entry(child_bus, &bus->children, node)
1369 pcibios_claim_one_bus(child_bus);
1371 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1374 /* pcibios_finish_adding_to_bus
1376 * This is to be called by the hotplug code after devices have been
1377 * added to a bus, this include calling it for a PHB that is just
1380 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1382 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1383 pci_domain_nr(bus), bus->number);
1385 /* Allocate bus and devices resources */
1386 pcibios_allocate_bus_resources(bus);
1387 pcibios_claim_one_bus(bus);
1389 /* Add new devices to global lists. Register in proc, sysfs. */
1390 pci_bus_add_devices(bus);
1393 /* eeh_add_device_tree_late(bus); */
1395 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1397 int pcibios_enable_device(struct pci_dev *dev, int mask)
1399 return pci_enable_resources(dev, mask);
1402 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1403 struct list_head *resources)
1405 unsigned long io_offset;
1406 struct resource *res;
1409 /* Hookup PHB IO resource */
1410 res = &hose->io_resource;
1412 /* Fixup IO space offset */
1413 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1414 res->start = (res->start + io_offset) & 0xffffffffu;
1415 res->end = (res->end + io_offset) & 0xffffffffu;
1418 pr_warn("PCI: I/O resource not set for host ");
1419 pr_cont("bridge %s (domain %d)\n",
1420 hose->dn->full_name, hose->global_number);
1421 /* Workaround for lack of IO resource only on 32-bit */
1422 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1423 res->end = res->start + IO_SPACE_LIMIT;
1424 res->flags = IORESOURCE_IO;
1426 pci_add_resource_offset(resources, res,
1427 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1429 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1430 (unsigned long long)res->start,
1431 (unsigned long long)res->end,
1432 (unsigned long)res->flags);
1434 /* Hookup PHB Memory resources */
1435 for (i = 0; i < 3; ++i) {
1436 res = &hose->mem_resources[i];
1440 pr_err("PCI: Memory resource 0 not set for ");
1441 pr_cont("host bridge %s (domain %d)\n",
1442 hose->dn->full_name, hose->global_number);
1444 /* Workaround for lack of MEM resource only on 32-bit */
1445 res->start = hose->pci_mem_offset;
1446 res->end = (resource_size_t)-1LL;
1447 res->flags = IORESOURCE_MEM;
1450 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1452 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1453 i, (unsigned long long)res->start,
1454 (unsigned long long)res->end,
1455 (unsigned long)res->flags);
1458 pr_debug("PCI: PHB MEM offset = %016llx\n",
1459 (unsigned long long)hose->pci_mem_offset);
1460 pr_debug("PCI: PHB IO offset = %08lx\n",
1461 (unsigned long)hose->io_base_virt - _IO_BASE);
1464 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1466 struct pci_controller *hose = bus->sysdata;
1468 return of_node_get(hose->dn);
1471 static void pcibios_scan_phb(struct pci_controller *hose)
1473 LIST_HEAD(resources);
1474 struct pci_bus *bus;
1475 struct device_node *node = hose->dn;
1477 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1479 pcibios_setup_phb_resources(hose, &resources);
1481 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1482 hose->ops, hose, &resources);
1484 pr_err("Failed to create bus for PCI domain %04x\n",
1485 hose->global_number);
1486 pci_free_resource_list(&resources);
1489 bus->busn_res.start = hose->first_busno;
1492 hose->last_busno = bus->busn_res.end;
1495 static int __init pcibios_init(void)
1497 struct pci_controller *hose, *tmp;
1500 pr_info("PCI: Probing PCI hardware\n");
1502 /* Scan all of the recorded PCI controllers. */
1503 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1504 hose->last_busno = 0xff;
1505 pcibios_scan_phb(hose);
1506 if (next_busno <= hose->last_busno)
1507 next_busno = hose->last_busno + 1;
1509 pci_bus_count = next_busno;
1511 /* Call common code to handle resource allocation */
1512 pcibios_resource_survey();
1517 subsys_initcall(pcibios_init);
1519 static struct pci_controller *pci_bus_to_hose(int bus)
1521 struct pci_controller *hose, *tmp;
1523 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1524 if (bus >= hose->first_busno && bus <= hose->last_busno)
1529 /* Provide information on locations of various I/O regions in physical
1530 * memory. Do this on a per-card basis so that we choose the right
1532 * Note that the returned IO or memory base is a physical address
1535 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1537 struct pci_controller *hose;
1538 long result = -EOPNOTSUPP;
1540 hose = pci_bus_to_hose(bus);
1545 case IOBASE_BRIDGE_NUMBER:
1546 return (long)hose->first_busno;
1548 return (long)hose->pci_mem_offset;
1550 return (long)hose->io_base_phys;
1552 return (long)isa_io_base;
1553 case IOBASE_ISA_MEM:
1554 return (long)isa_mem_base;
1561 * Null PCI config access functions, for the case when we can't
1564 #define NULL_PCI_OP(rw, size, type) \
1566 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1568 return PCIBIOS_DEVICE_NOT_FOUND; \
1572 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1575 return PCIBIOS_DEVICE_NOT_FOUND;
1579 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1582 return PCIBIOS_DEVICE_NOT_FOUND;
1585 static struct pci_ops null_pci_ops = {
1586 .read = null_read_config,
1587 .write = null_write_config,
1591 * These functions are used early on before PCI scanning is done
1592 * and all of the pci_dev and pci_bus structures have been created.
1594 static struct pci_bus *
1595 fake_pci_bus(struct pci_controller *hose, int busnr)
1597 static struct pci_bus bus;
1600 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1604 bus.ops = hose ? hose->ops : &null_pci_ops;
1608 #define EARLY_PCI_OP(rw, size, type) \
1609 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1610 int devfn, int offset, type value) \
1612 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1613 devfn, offset, value); \
1616 EARLY_PCI_OP(read, byte, u8 *)
1617 EARLY_PCI_OP(read, word, u16 *)
1618 EARLY_PCI_OP(read, dword, u32 *)
1619 EARLY_PCI_OP(write, byte, u8)
1620 EARLY_PCI_OP(write, word, u16)
1621 EARLY_PCI_OP(write, dword, u32)
1623 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1626 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);