arch/mips/include/asm/kvm_host.h

   1 /*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
   8 */
   9
  10 #ifndef __MIPS_KVM_HOST_H__
  11 #define __MIPS_KVM_HOST_H__
  12
  13 #include <linux/mutex.h>
  14 #include <linux/hrtimer.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/types.h>
  17 #include <linux/kvm.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/threads.h>
  20 #include <linux/spinlock.h>
  21
  22
  23 #define KVM_MAX_VCPUS           1
  24 #define KVM_USER_MEM_SLOTS      8
  25 /* memory slots that does not exposed to userspace */
  26 #define KVM_PRIVATE_MEM_SLOTS   0
  27
  28 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  29
  30
  31
  32 /* Special address that contains the comm page, used for reducing # of traps */
  33 #define KVM_GUEST_COMMPAGE_ADDR     0x0
  34
  35 #define KVM_GUEST_KERNEL_MODE(vcpu)     ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
  36                                         ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
  37
  38 #define KVM_GUEST_KUSEG             0x00000000UL
  39 #define KVM_GUEST_KSEG0             0x40000000UL
  40 #define KVM_GUEST_KSEG23            0x60000000UL
  41 #define KVM_GUEST_KSEGX(a)          ((_ACAST32_(a)) & 0x60000000)
  42 #define KVM_GUEST_CPHYSADDR(a)      ((_ACAST32_(a)) & 0x1fffffff)
  43
  44 #define KVM_GUEST_CKSEG0ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  45 #define KVM_GUEST_CKSEG1ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  46 #define KVM_GUEST_CKSEG23ADDR(a)        (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  47
  48 /*
  49  * Map an address to a certain kernel segment
  50  */
  51 #define KVM_GUEST_KSEG0ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  52 #define KVM_GUEST_KSEG1ADDR(a)          (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  53 #define KVM_GUEST_KSEG23ADDR(a)         (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  54
  55 #define KVM_INVALID_PAGE            0xdeadbeef
  56 #define KVM_INVALID_INST            0xdeadbeef
  57 #define KVM_INVALID_ADDR            0xdeadbeef
  58
  59 #define KVM_MALTA_GUEST_RTC_ADDR    0xb8000070UL
  60
  61 #define GUEST_TICKS_PER_JIFFY (40000000/HZ)
  62 #define MS_TO_NS(x) (x * 1E6L)
  63
  64 #define CAUSEB_DC       27
  65 #define CAUSEF_DC       (_ULCAST_(1)   << 27)
  66
  67 struct kvm;
  68 struct kvm_run;
  69 struct kvm_vcpu;
  70 struct kvm_interrupt;
  71
  72 extern atomic_t kvm_mips_instance;
  73 extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
  74 extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
  75 extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
  76
  77 struct kvm_vm_stat {
  78         u32 remote_tlb_flush;
  79 };
  80
  81 struct kvm_vcpu_stat {
  82         u32 wait_exits;
  83         u32 cache_exits;
  84         u32 signal_exits;
  85         u32 int_exits;
  86         u32 cop_unusable_exits;
  87         u32 tlbmod_exits;
  88         u32 tlbmiss_ld_exits;
  89         u32 tlbmiss_st_exits;
  90         u32 addrerr_st_exits;
  91         u32 addrerr_ld_exits;
  92         u32 syscall_exits;
  93         u32 resvd_inst_exits;
  94         u32 break_inst_exits;
  95         u32 flush_dcache_exits;
  96         u32 halt_wakeup;
  97 };
  98
  99 enum kvm_mips_exit_types {
 100         WAIT_EXITS,
 101         CACHE_EXITS,
 102         SIGNAL_EXITS,
 103         INT_EXITS,
 104         COP_UNUSABLE_EXITS,
 105         TLBMOD_EXITS,
 106         TLBMISS_LD_EXITS,
 107         TLBMISS_ST_EXITS,
 108         ADDRERR_ST_EXITS,
 109         ADDRERR_LD_EXITS,
 110         SYSCALL_EXITS,
 111         RESVD_INST_EXITS,
 112         BREAK_INST_EXITS,
 113         FLUSH_DCACHE_EXITS,
 114         MAX_KVM_MIPS_EXIT_TYPES
 115 };
 116
 117 struct kvm_arch_memory_slot {
 118 };
 119
 120 struct kvm_arch {
 121         /* Guest GVA->HPA page table */
 122         unsigned long *guest_pmap;
 123         unsigned long guest_pmap_npages;
 124
 125         /* Wired host TLB used for the commpage */
 126         int commpage_tlb;
 127 };
 128
 129 #define N_MIPS_COPROC_REGS      32
 130 #define N_MIPS_COPROC_SEL       8
 131
 132 struct mips_coproc {
 133         unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 134 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
 135         unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
 136 #endif
 137 };
 138
 139 /*
 140  * Coprocessor 0 register names
 141  */
 142 #define MIPS_CP0_TLB_INDEX          0
 143 #define MIPS_CP0_TLB_RANDOM         1
 144 #define MIPS_CP0_TLB_LOW            2
 145 #define MIPS_CP0_TLB_LO0            2
 146 #define MIPS_CP0_TLB_LO1            3
 147 #define MIPS_CP0_TLB_CONTEXT    4
 148 #define MIPS_CP0_TLB_PG_MASK    5
 149 #define MIPS_CP0_TLB_WIRED          6
 150 #define MIPS_CP0_HWRENA             7
 151 #define MIPS_CP0_BAD_VADDR          8
 152 #define MIPS_CP0_COUNT          9
 153 #define MIPS_CP0_TLB_HI         10
 154 #define MIPS_CP0_COMPARE            11
 155 #define MIPS_CP0_STATUS         12
 156 #define MIPS_CP0_CAUSE          13
 157 #define MIPS_CP0_EXC_PC         14
 158 #define MIPS_CP0_PRID               15
 159 #define MIPS_CP0_CONFIG         16
 160 #define MIPS_CP0_LLADDR         17
 161 #define MIPS_CP0_WATCH_LO           18
 162 #define MIPS_CP0_WATCH_HI           19
 163 #define MIPS_CP0_TLB_XCONTEXT   20
 164 #define MIPS_CP0_ECC                26
 165 #define MIPS_CP0_CACHE_ERR          27
 166 #define MIPS_CP0_TAG_LO         28
 167 #define MIPS_CP0_TAG_HI         29
 168 #define MIPS_CP0_ERROR_PC           30
 169 #define MIPS_CP0_DEBUG          23
 170 #define MIPS_CP0_DEPC               24
 171 #define MIPS_CP0_PERFCNT            25
 172 #define MIPS_CP0_ERRCTL         26
 173 #define MIPS_CP0_DATA_LO            28
 174 #define MIPS_CP0_DATA_HI            29
 175 #define MIPS_CP0_DESAVE         31
 176
 177 #define MIPS_CP0_CONFIG_SEL         0
 178 #define MIPS_CP0_CONFIG1_SEL    1
 179 #define MIPS_CP0_CONFIG2_SEL    2
 180 #define MIPS_CP0_CONFIG3_SEL    3
 181
 182 /* Config0 register bits */
 183 #define CP0C0_M    31
 184 #define CP0C0_K23  28
 185 #define CP0C0_KU   25
 186 #define CP0C0_MDU  20
 187 #define CP0C0_MM   17
 188 #define CP0C0_BM   16
 189 #define CP0C0_BE   15
 190 #define CP0C0_AT   13
 191 #define CP0C0_AR   10
 192 #define CP0C0_MT   7
 193 #define CP0C0_VI   3
 194 #define CP0C0_K0   0
 195
 196 /* Config1 register bits */
 197 #define CP0C1_M    31
 198 #define CP0C1_MMU  25
 199 #define CP0C1_IS   22
 200 #define CP0C1_IL   19
 201 #define CP0C1_IA   16
 202 #define CP0C1_DS   13
 203 #define CP0C1_DL   10
 204 #define CP0C1_DA   7
 205 #define CP0C1_C2   6
 206 #define CP0C1_MD   5
 207 #define CP0C1_PC   4
 208 #define CP0C1_WR   3
 209 #define CP0C1_CA   2
 210 #define CP0C1_EP   1
 211 #define CP0C1_FP   0
 212
 213 /* Config2 Register bits */
 214 #define CP0C2_M    31
 215 #define CP0C2_TU   28
 216 #define CP0C2_TS   24
 217 #define CP0C2_TL   20
 218 #define CP0C2_TA   16
 219 #define CP0C2_SU   12
 220 #define CP0C2_SS   8
 221 #define CP0C2_SL   4
 222 #define CP0C2_SA   0
 223
 224 /* Config3 Register bits */
 225 #define CP0C3_M    31
 226 #define CP0C3_ISA_ON_EXC 16
 227 #define CP0C3_ULRI  13
 228 #define CP0C3_DSPP 10
 229 #define CP0C3_LPA  7
 230 #define CP0C3_VEIC 6
 231 #define CP0C3_VInt 5
 232 #define CP0C3_SP   4
 233 #define CP0C3_MT   2
 234 #define CP0C3_SM   1
 235 #define CP0C3_TL   0
 236
 237 /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
 238 #define MIPS_CONFIG0                                              \
 239   ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
 240
 241 /* Have config2, no coprocessor2 attached, no MDMX support attached,
 242    no performance counters, watch registers present,
 243    no code compression, EJTAG present, no FPU, no watch registers */
 244 #define MIPS_CONFIG1                                              \
 245 ((1 << CP0C1_M) |                                                 \
 246  (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
 247  (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
 248  (0 << CP0C1_FP))
 249
 250 /* Have config3, no tertiary/secondary caches implemented */
 251 #define MIPS_CONFIG2                                              \
 252 ((1 << CP0C2_M))
 253
 254 /* No config4, no DSP ASE, no large physaddr (PABITS),
 255    no external interrupt controller, no vectored interrupts,
 256    no 1kb pages, no SmartMIPS ASE, no trace logic */
 257 #define MIPS_CONFIG3                                              \
 258 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
 259  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
 260  (0 << CP0C3_SM) | (0 << CP0C3_TL))
 261
 262 /* MMU types, the first four entries have the same layout as the
 263    CP0C0_MT field.  */
 264 enum mips_mmu_types {
 265         MMU_TYPE_NONE,
 266         MMU_TYPE_R4000,
 267         MMU_TYPE_RESERVED,
 268         MMU_TYPE_FMT,
 269         MMU_TYPE_R3000,
 270         MMU_TYPE_R6000,
 271         MMU_TYPE_R8000
 272 };
 273
 274 /*
 275  * Trap codes
 276  */
 277 #define T_INT           0       /* Interrupt pending */
 278 #define T_TLB_MOD       1       /* TLB modified fault */
 279 #define T_TLB_LD_MISS       2   /* TLB miss on load or ifetch */
 280 #define T_TLB_ST_MISS       3   /* TLB miss on a store */
 281 #define T_ADDR_ERR_LD       4   /* Address error on a load or ifetch */
 282 #define T_ADDR_ERR_ST       5   /* Address error on a store */
 283 #define T_BUS_ERR_IFETCH    6   /* Bus error on an ifetch */
 284 #define T_BUS_ERR_LD_ST     7   /* Bus error on a load or store */
 285 #define T_SYSCALL       8       /* System call */
 286 #define T_BREAK         9       /* Breakpoint */
 287 #define T_RES_INST      10      /* Reserved instruction exception */
 288 #define T_COP_UNUSABLE      11  /* Coprocessor unusable */
 289 #define T_OVFLOW        12      /* Arithmetic overflow */
 290
 291 /*
 292  * Trap definitions added for r4000 port.
 293  */
 294 #define T_TRAP          13      /* Trap instruction */
 295 #define T_VCEI          14      /* Virtual coherency exception */
 296 #define T_FPE           15      /* Floating point exception */
 297 #define T_WATCH         23      /* Watch address reference */
 298 #define T_VCED          31      /* Virtual coherency data */
 299
 300 /* Resume Flags */
 301 #define RESUME_FLAG_DR          (1<<0)  /* Reload guest nonvolatile state? */
 302 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
 303
 304 #define RESUME_GUEST            0
 305 #define RESUME_GUEST_DR         RESUME_FLAG_DR
 306 #define RESUME_HOST             RESUME_FLAG_HOST
 307
 308 enum emulation_result {
 309         EMULATE_DONE,           /* no further processing */
 310         EMULATE_DO_MMIO,        /* kvm_run filled with MMIO request */
 311         EMULATE_FAIL,           /* can't emulate this instruction */
 312         EMULATE_WAIT,           /* WAIT instruction */
 313         EMULATE_PRIV_FAIL,
 314 };
 315
 316 #define MIPS3_PG_G  0x00000001  /* Global; ignore ASID if in lo0 & lo1 */
 317 #define MIPS3_PG_V  0x00000002  /* Valid */
 318 #define MIPS3_PG_NV 0x00000000
 319 #define MIPS3_PG_D  0x00000004  /* Dirty */
 320
 321 #define mips3_paddr_to_tlbpfn(x) \
 322     (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
 323 #define mips3_tlbpfn_to_paddr(x) \
 324     ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
 325
 326 #define MIPS3_PG_SHIFT      6
 327 #define MIPS3_PG_FRAME      0x3fffffc0
 328
 329 #define VPN2_MASK           0xffffe000
 330 #define TLB_IS_GLOBAL(x)    (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
 331 #define TLB_VPN2(x)         ((x).tlb_hi & VPN2_MASK)
 332 #define TLB_ASID(x)         ((x).tlb_hi & ASID_MASK)
 333 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
 334
 335 struct kvm_mips_tlb {
 336         long tlb_mask;
 337         long tlb_hi;
 338         long tlb_lo0;
 339         long tlb_lo1;
 340 };
 341
 342 #define KVM_MIPS_GUEST_TLB_SIZE     64
 343 struct kvm_vcpu_arch {
 344         void *host_ebase, *guest_ebase;
 345         unsigned long host_stack;
 346         unsigned long host_gp;
 347
 348         /* Host CP0 registers used when handling exits from guest */
 349         unsigned long host_cp0_badvaddr;
 350         unsigned long host_cp0_cause;
 351         unsigned long host_cp0_epc;
 352         unsigned long host_cp0_entryhi;
 353         uint32_t guest_inst;
 354
 355         /* GPRS */
 356         unsigned long gprs[32];
 357         unsigned long hi;
 358         unsigned long lo;
 359         unsigned long pc;
 360
 361         /* FPU State */
 362         struct mips_fpu_struct fpu;
 363
 364         /* COP0 State */
 365         struct mips_coproc *cop0;
 366
 367         /* Host KSEG0 address of the EI/DI offset */
 368         void *kseg0_commpage;
 369
 370         u32 io_gpr;             /* GPR used as IO source/target */
 371
 372         /* Used to calibrate the virutal count register for the guest */
 373         int32_t host_cp0_count;
 374
 375         /* Bitmask of exceptions that are pending */
 376         unsigned long pending_exceptions;
 377
 378         /* Bitmask of pending exceptions to be cleared */
 379         unsigned long pending_exceptions_clr;
 380
 381         unsigned long pending_load_cause;
 382
 383         /* Save/Restore the entryhi register when are are preempted/scheduled back in */
 384         unsigned long preempt_entryhi;
 385
 386         /* S/W Based TLB for guest */
 387         struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
 388
 389         /* Cached guest kernel/user ASIDs */
 390         uint32_t guest_user_asid[NR_CPUS];
 391         uint32_t guest_kernel_asid[NR_CPUS];
 392         struct mm_struct guest_kernel_mm, guest_user_mm;
 393
 394         struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
 395
 396
 397         struct hrtimer comparecount_timer;
 398
 399         int last_sched_cpu;
 400
 401         /* WAIT executed */
 402         int wait;
 403 };
 404
 405
 406 #define kvm_read_c0_guest_index(cop0)               (cop0->reg[MIPS_CP0_TLB_INDEX][0])
 407 #define kvm_write_c0_guest_index(cop0, val)         (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
 408 #define kvm_read_c0_guest_entrylo0(cop0)            (cop0->reg[MIPS_CP0_TLB_LO0][0])
 409 #define kvm_read_c0_guest_entrylo1(cop0)            (cop0->reg[MIPS_CP0_TLB_LO1][0])
 410 #define kvm_read_c0_guest_context(cop0)             (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
 411 #define kvm_write_c0_guest_context(cop0, val)       (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
 412 #define kvm_read_c0_guest_userlocal(cop0)           (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
 413 #define kvm_read_c0_guest_pagemask(cop0)            (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
 414 #define kvm_write_c0_guest_pagemask(cop0, val)      (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
 415 #define kvm_read_c0_guest_wired(cop0)               (cop0->reg[MIPS_CP0_TLB_WIRED][0])
 416 #define kvm_write_c0_guest_wired(cop0, val)         (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
 417 #define kvm_read_c0_guest_badvaddr(cop0)            (cop0->reg[MIPS_CP0_BAD_VADDR][0])
 418 #define kvm_write_c0_guest_badvaddr(cop0, val)      (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
 419 #define kvm_read_c0_guest_count(cop0)               (cop0->reg[MIPS_CP0_COUNT][0])
 420 #define kvm_write_c0_guest_count(cop0, val)         (cop0->reg[MIPS_CP0_COUNT][0] = (val))
 421 #define kvm_read_c0_guest_entryhi(cop0)             (cop0->reg[MIPS_CP0_TLB_HI][0])
 422 #define kvm_write_c0_guest_entryhi(cop0, val)       (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
 423 #define kvm_read_c0_guest_compare(cop0)             (cop0->reg[MIPS_CP0_COMPARE][0])
 424 #define kvm_write_c0_guest_compare(cop0, val)       (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
 425 #define kvm_read_c0_guest_status(cop0)              (cop0->reg[MIPS_CP0_STATUS][0])
 426 #define kvm_write_c0_guest_status(cop0, val)        (cop0->reg[MIPS_CP0_STATUS][0] = (val))
 427 #define kvm_read_c0_guest_intctl(cop0)              (cop0->reg[MIPS_CP0_STATUS][1])
 428 #define kvm_write_c0_guest_intctl(cop0, val)        (cop0->reg[MIPS_CP0_STATUS][1] = (val))
 429 #define kvm_read_c0_guest_cause(cop0)               (cop0->reg[MIPS_CP0_CAUSE][0])
 430 #define kvm_write_c0_guest_cause(cop0, val)         (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
 431 #define kvm_read_c0_guest_epc(cop0)                 (cop0->reg[MIPS_CP0_EXC_PC][0])
 432 #define kvm_write_c0_guest_epc(cop0, val)           (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
 433 #define kvm_read_c0_guest_prid(cop0)                (cop0->reg[MIPS_CP0_PRID][0])
 434 #define kvm_write_c0_guest_prid(cop0, val)          (cop0->reg[MIPS_CP0_PRID][0] = (val))
 435 #define kvm_read_c0_guest_ebase(cop0)               (cop0->reg[MIPS_CP0_PRID][1])
 436 #define kvm_write_c0_guest_ebase(cop0, val)         (cop0->reg[MIPS_CP0_PRID][1] = (val))
 437 #define kvm_read_c0_guest_config(cop0)              (cop0->reg[MIPS_CP0_CONFIG][0])
 438 #define kvm_read_c0_guest_config1(cop0)             (cop0->reg[MIPS_CP0_CONFIG][1])
 439 #define kvm_read_c0_guest_config2(cop0)             (cop0->reg[MIPS_CP0_CONFIG][2])
 440 #define kvm_read_c0_guest_config3(cop0)             (cop0->reg[MIPS_CP0_CONFIG][3])
 441 #define kvm_read_c0_guest_config7(cop0)             (cop0->reg[MIPS_CP0_CONFIG][7])
 442 #define kvm_write_c0_guest_config(cop0, val)        (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
 443 #define kvm_write_c0_guest_config1(cop0, val)       (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
 444 #define kvm_write_c0_guest_config2(cop0, val)       (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
 445 #define kvm_write_c0_guest_config3(cop0, val)       (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
 446 #define kvm_write_c0_guest_config7(cop0, val)       (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
 447 #define kvm_read_c0_guest_errorepc(cop0)            (cop0->reg[MIPS_CP0_ERROR_PC][0])
 448 #define kvm_write_c0_guest_errorepc(cop0, val)      (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
 449
 450 #define kvm_set_c0_guest_status(cop0, val)          (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
 451 #define kvm_clear_c0_guest_status(cop0, val)        (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
 452 #define kvm_set_c0_guest_cause(cop0, val)           (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
 453 #define kvm_clear_c0_guest_cause(cop0, val)         (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
 454 #define kvm_change_c0_guest_cause(cop0, change, val)  \
 455 {                                                     \
 456     kvm_clear_c0_guest_cause(cop0, change);           \
 457     kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
 458 }
 459 #define kvm_set_c0_guest_ebase(cop0, val)           (cop0->reg[MIPS_CP0_PRID][1] |= (val))
 460 #define kvm_clear_c0_guest_ebase(cop0, val)         (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
 461 #define kvm_change_c0_guest_ebase(cop0, change, val)  \
 462 {                                                     \
 463     kvm_clear_c0_guest_ebase(cop0, change);           \
 464     kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
 465 }
 466
 467
 468 struct kvm_mips_callbacks {
 469         int (*handle_cop_unusable) (struct kvm_vcpu *vcpu);
 470         int (*handle_tlb_mod) (struct kvm_vcpu *vcpu);
 471         int (*handle_tlb_ld_miss) (struct kvm_vcpu *vcpu);
 472         int (*handle_tlb_st_miss) (struct kvm_vcpu *vcpu);
 473         int (*handle_addr_err_st) (struct kvm_vcpu *vcpu);
 474         int (*handle_addr_err_ld) (struct kvm_vcpu *vcpu);
 475         int (*handle_syscall) (struct kvm_vcpu *vcpu);
 476         int (*handle_res_inst) (struct kvm_vcpu *vcpu);
 477         int (*handle_break) (struct kvm_vcpu *vcpu);
 478         int (*vm_init) (struct kvm *kvm);
 479         int (*vcpu_init) (struct kvm_vcpu *vcpu);
 480         int (*vcpu_setup) (struct kvm_vcpu *vcpu);
 481          gpa_t(*gva_to_gpa) (gva_t gva);
 482         void (*queue_timer_int) (struct kvm_vcpu *vcpu);
 483         void (*dequeue_timer_int) (struct kvm_vcpu *vcpu);
 484         void (*queue_io_int) (struct kvm_vcpu *vcpu,
 485                               struct kvm_mips_interrupt *irq);
 486         void (*dequeue_io_int) (struct kvm_vcpu *vcpu,
 487                                 struct kvm_mips_interrupt *irq);
 488         int (*irq_deliver) (struct kvm_vcpu *vcpu, unsigned int priority,
 489                             uint32_t cause);
 490         int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
 491                           uint32_t cause);
 492 };
 493 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
 494 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
 495
 496 /* Debug: dump vcpu state */
 497 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 498
 499 /* Trampoline ASM routine to start running in "Guest" context */
 500 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
 501
 502 /* TLB handling */
 503 uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
 504
 505 uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
 506
 507 uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
 508
 509 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
 510                                            struct kvm_vcpu *vcpu);
 511
 512 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
 513                                               struct kvm_vcpu *vcpu);
 514
 515 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
 516                                                 struct kvm_mips_tlb *tlb,
 517                                                 unsigned long *hpa0,
 518                                                 unsigned long *hpa1);
 519
 520 extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
 521                                                      uint32_t *opc,
 522                                                      struct kvm_run *run,
 523                                                      struct kvm_vcpu *vcpu);
 524
 525 extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
 526                                                     uint32_t *opc,
 527                                                     struct kvm_run *run,
 528                                                     struct kvm_vcpu *vcpu);
 529
 530 extern void kvm_mips_dump_host_tlbs(void);
 531 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
 532 extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
 533 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
 534 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
 535 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
 536
 537 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
 538                                      unsigned long entryhi);
 539 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
 540 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
 541                                                    unsigned long gva);
 542 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
 543                                     struct kvm_vcpu *vcpu);
 544 extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
 545 extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
 546 extern void kvm_local_flush_tlb_all(void);
 547 extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
 548 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
 549 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 550 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
 551
 552 /* Emulation */
 553 uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
 554 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
 555
 556 extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
 557                                                    uint32_t *opc,
 558                                                    struct kvm_run *run,
 559                                                    struct kvm_vcpu *vcpu);
 560
 561 extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
 562                                                       uint32_t *opc,
 563                                                       struct kvm_run *run,
 564                                                       struct kvm_vcpu *vcpu);
 565
 566 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
 567                                                          uint32_t *opc,
 568                                                          struct kvm_run *run,
 569                                                          struct kvm_vcpu *vcpu);
 570
 571 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
 572                                                         uint32_t *opc,
 573                                                         struct kvm_run *run,
 574                                                         struct kvm_vcpu *vcpu);
 575
 576 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
 577                                                          uint32_t *opc,
 578                                                          struct kvm_run *run,
 579                                                          struct kvm_vcpu *vcpu);
 580
 581 extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
 582                                                         uint32_t *opc,
 583                                                         struct kvm_run *run,
 584                                                         struct kvm_vcpu *vcpu);
 585
 586 extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
 587                                                      uint32_t *opc,
 588                                                      struct kvm_run *run,
 589                                                      struct kvm_vcpu *vcpu);
 590
 591 extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
 592                                                       uint32_t *opc,
 593                                                       struct kvm_run *run,
 594                                                       struct kvm_vcpu *vcpu);
 595
 596 extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
 597                                                 uint32_t *opc,
 598                                                 struct kvm_run *run,
 599                                                 struct kvm_vcpu *vcpu);
 600
 601 extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
 602                                                      uint32_t *opc,
 603                                                      struct kvm_run *run,
 604                                                      struct kvm_vcpu *vcpu);
 605
 606 extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
 607                                                      uint32_t *opc,
 608                                                      struct kvm_run *run,
 609                                                      struct kvm_vcpu *vcpu);
 610
 611 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
 612                                                          struct kvm_run *run);
 613
 614 enum emulation_result kvm_mips_emulate_count(struct kvm_vcpu *vcpu);
 615
 616 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
 617                                                uint32_t *opc,
 618                                                struct kvm_run *run,
 619                                                struct kvm_vcpu *vcpu);
 620
 621 enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
 622                                              uint32_t *opc,
 623                                              uint32_t cause,
 624                                              struct kvm_run *run,
 625                                              struct kvm_vcpu *vcpu);
 626 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
 627                                            uint32_t *opc,
 628                                            uint32_t cause,
 629                                            struct kvm_run *run,
 630                                            struct kvm_vcpu *vcpu);
 631 enum emulation_result kvm_mips_emulate_store(uint32_t inst,
 632                                              uint32_t cause,
 633                                              struct kvm_run *run,
 634                                              struct kvm_vcpu *vcpu);
 635 enum emulation_result kvm_mips_emulate_load(uint32_t inst,
 636                                             uint32_t cause,
 637                                             struct kvm_run *run,
 638                                             struct kvm_vcpu *vcpu);
 639
 640 /* Dynamic binary translation */
 641 extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
 642                                       struct kvm_vcpu *vcpu);
 643 extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
 644                                    struct kvm_vcpu *vcpu);
 645 extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
 646                                struct kvm_vcpu *vcpu);
 647 extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
 648                                struct kvm_vcpu *vcpu);
 649
 650 /* Misc */
 651 extern void mips32_SyncICache(unsigned long addr, unsigned long size);
 652 extern int kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
 653 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
 654
 655
 656 #endif /* __MIPS_KVM_HOST_H__ */