2 * Atheros AR724X PCI host controller driver
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/spinlock.h>
13 #include <linux/irq.h>
14 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <asm/mach-ath79/ath79.h>
18 #include <asm/mach-ath79/ar71xx_regs.h>
20 #define AR724X_PCI_REG_RESET 0x18
21 #define AR724X_PCI_REG_INT_STATUS 0x4c
22 #define AR724X_PCI_REG_INT_MASK 0x50
24 #define AR724X_PCI_RESET_LINK_UP BIT(0)
26 #define AR724X_PCI_INT_DEV0 BIT(14)
28 #define AR724X_PCI_IRQ_COUNT 1
30 #define AR7240_BAR0_WAR_VALUE 0xffff
32 #define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
33 PCI_COMMAND_MASTER | \
34 PCI_COMMAND_INVALIDATE | \
35 PCI_COMMAND_PARITY | \
37 PCI_COMMAND_FAST_BACK)
39 struct ar724x_pci_controller {
40 void __iomem *devcfg_base;
41 void __iomem *ctrl_base;
42 void __iomem *crp_base;
53 struct pci_controller pci_controller;
54 struct resource io_res;
55 struct resource mem_res;
58 static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
62 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
63 return reset & AR724X_PCI_RESET_LINK_UP;
66 static inline struct ar724x_pci_controller *
67 pci_bus_to_ar724x_controller(struct pci_bus *bus)
69 struct pci_controller *hose;
71 hose = (struct pci_controller *) bus->sysdata;
72 return container_of(hose, struct ar724x_pci_controller, pci_controller);
75 static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
76 int where, int size, u32 value)
83 WARN_ON(where & (size - 1));
86 return PCIBIOS_DEVICE_NOT_FOUND;
90 spin_lock_irqsave(&apc->lock, flags);
91 data = __raw_readl(base + (where & ~3));
95 s = ((where & 3) * 8);
97 data |= ((value & 0xff) << s);
100 s = ((where & 2) * 8);
101 data &= ~(0xffff << s);
102 data |= ((value & 0xffff) << s);
108 spin_unlock_irqrestore(&apc->lock, flags);
109 return PCIBIOS_BAD_REGISTER_NUMBER;
112 __raw_writel(data, base + (where & ~3));
114 __raw_readl(base + (where & ~3));
115 spin_unlock_irqrestore(&apc->lock, flags);
117 return PCIBIOS_SUCCESSFUL;
120 static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
121 int size, uint32_t *value)
123 struct ar724x_pci_controller *apc;
128 apc = pci_bus_to_ar724x_controller(bus);
130 return PCIBIOS_DEVICE_NOT_FOUND;
133 return PCIBIOS_DEVICE_NOT_FOUND;
135 base = apc->devcfg_base;
137 spin_lock_irqsave(&apc->lock, flags);
138 data = __raw_readl(base + (where & ~3));
156 spin_unlock_irqrestore(&apc->lock, flags);
158 return PCIBIOS_BAD_REGISTER_NUMBER;
161 spin_unlock_irqrestore(&apc->lock, flags);
163 if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
164 apc->bar0_is_cached) {
165 /* use the cached value */
166 *value = apc->bar0_value;
171 return PCIBIOS_SUCCESSFUL;
174 static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
175 int size, uint32_t value)
177 struct ar724x_pci_controller *apc;
183 apc = pci_bus_to_ar724x_controller(bus);
185 return PCIBIOS_DEVICE_NOT_FOUND;
188 return PCIBIOS_DEVICE_NOT_FOUND;
190 if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
191 if (value != 0xffffffff) {
193 * WAR for a hw issue. If the BAR0 register of the
194 * device is set to the proper base address, the
195 * memory space of the device is not accessible.
197 * Cache the intended value so it can be read back,
198 * and write a SoC specific constant value to the
199 * BAR0 register in order to make the device memory
202 apc->bar0_is_cached = true;
203 apc->bar0_value = value;
205 value = AR7240_BAR0_WAR_VALUE;
207 apc->bar0_is_cached = false;
211 base = apc->devcfg_base;
213 spin_lock_irqsave(&apc->lock, flags);
214 data = __raw_readl(base + (where & ~3));
218 s = ((where & 3) * 8);
219 data &= ~(0xff << s);
220 data |= ((value & 0xff) << s);
223 s = ((where & 2) * 8);
224 data &= ~(0xffff << s);
225 data |= ((value & 0xffff) << s);
231 spin_unlock_irqrestore(&apc->lock, flags);
233 return PCIBIOS_BAD_REGISTER_NUMBER;
236 __raw_writel(data, base + (where & ~3));
238 __raw_readl(base + (where & ~3));
239 spin_unlock_irqrestore(&apc->lock, flags);
241 return PCIBIOS_SUCCESSFUL;
244 static struct pci_ops ar724x_pci_ops = {
245 .read = ar724x_pci_read,
246 .write = ar724x_pci_write,
249 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
251 struct ar724x_pci_controller *apc;
255 apc = irq_get_handler_data(irq);
256 base = apc->ctrl_base;
258 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
259 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
261 if (pending & AR724X_PCI_INT_DEV0)
262 generic_handle_irq(apc->irq_base + 0);
265 spurious_interrupt();
268 static void ar724x_pci_irq_unmask(struct irq_data *d)
270 struct ar724x_pci_controller *apc;
275 apc = irq_data_get_irq_chip_data(d);
276 base = apc->ctrl_base;
277 offset = apc->irq_base - d->irq;
281 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
282 __raw_writel(t | AR724X_PCI_INT_DEV0,
283 base + AR724X_PCI_REG_INT_MASK);
285 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
289 static void ar724x_pci_irq_mask(struct irq_data *d)
291 struct ar724x_pci_controller *apc;
296 apc = irq_data_get_irq_chip_data(d);
297 base = apc->ctrl_base;
298 offset = apc->irq_base - d->irq;
302 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
303 __raw_writel(t & ~AR724X_PCI_INT_DEV0,
304 base + AR724X_PCI_REG_INT_MASK);
307 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
309 t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
310 __raw_writel(t | AR724X_PCI_INT_DEV0,
311 base + AR724X_PCI_REG_INT_STATUS);
314 __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
318 static struct irq_chip ar724x_pci_irq_chip = {
319 .name = "AR724X PCI ",
320 .irq_mask = ar724x_pci_irq_mask,
321 .irq_unmask = ar724x_pci_irq_unmask,
322 .irq_mask_ack = ar724x_pci_irq_mask,
325 static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
331 base = apc->ctrl_base;
333 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
334 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
336 apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
338 for (i = apc->irq_base;
339 i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
340 irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
342 irq_set_chip_data(i, apc);
345 irq_set_handler_data(apc->irq, apc);
346 irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
349 static int ar724x_pci_probe(struct platform_device *pdev)
351 struct ar724x_pci_controller *apc;
352 struct resource *res;
359 apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
364 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
365 apc->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
366 if (IS_ERR(apc->ctrl_base))
367 return PTR_ERR(apc->ctrl_base);
369 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
370 apc->devcfg_base = devm_ioremap_resource(&pdev->dev, res);
371 if (IS_ERR(apc->devcfg_base))
372 return PTR_ERR(apc->devcfg_base);
374 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
375 apc->crp_base = devm_ioremap_resource(&pdev->dev, res);
376 if (IS_ERR(apc->crp_base))
377 return PTR_ERR(apc->crp_base);
379 apc->irq = platform_get_irq(pdev, 0);
383 spin_lock_init(&apc->lock);
385 res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
389 apc->io_res.parent = res;
390 apc->io_res.name = "PCI IO space";
391 apc->io_res.start = res->start;
392 apc->io_res.end = res->end;
393 apc->io_res.flags = IORESOURCE_IO;
395 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
399 apc->mem_res.parent = res;
400 apc->mem_res.name = "PCI memory space";
401 apc->mem_res.start = res->start;
402 apc->mem_res.end = res->end;
403 apc->mem_res.flags = IORESOURCE_MEM;
405 apc->pci_controller.pci_ops = &ar724x_pci_ops;
406 apc->pci_controller.io_resource = &apc->io_res;
407 apc->pci_controller.mem_resource = &apc->mem_res;
409 apc->link_up = ar724x_pci_check_link(apc);
411 dev_warn(&pdev->dev, "PCIe link is down\n");
413 ar724x_pci_irq_init(apc, id);
415 ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
417 register_pci_controller(&apc->pci_controller);
422 static struct platform_driver ar724x_pci_driver = {
423 .probe = ar724x_pci_probe,
425 .name = "ar724x-pci",
426 .owner = THIS_MODULE,
430 static int __init ar724x_pci_init(void)
432 return platform_driver_register(&ar724x_pci_driver);
435 postcore_initcall(ar724x_pci_init);