arch/openrisc/kernel/entry.S

   1 /*
   2  * OpenRISC entry.S
   3  *
   4  * Linux architectural port borrowing liberally from similar works of
   5  * others.  All original copyrights apply as per the original source
   6  * declaration.
   7  *
   8  * Modifications for the OpenRISC architecture:
   9  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
  10  * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com>
  11  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  12  *
  13  *      This program is free software; you can redistribute it and/or
  14  *      modify it under the terms of the GNU General Public License
  15  *      as published by the Free Software Foundation; either version
  16  *      2 of the License, or (at your option) any later version.
  17  */
  18
  19 #include <linux/linkage.h>
  20
  21 #include <asm/processor.h>
  22 #include <asm/unistd.h>
  23 #include <asm/thread_info.h>
  24 #include <asm/errno.h>
  25 #include <asm/spr_defs.h>
  26 #include <asm/page.h>
  27 #include <asm/mmu.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/asm-offsets.h>
  30
  31 #define DISABLE_INTERRUPTS(t1,t2)                       \
  32         l.mfspr t2,r0,SPR_SR                            ;\
  33         l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE))         ;\
  34         l.ori   t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE))      ;\
  35         l.and   t2,t2,t1                                ;\
  36         l.mtspr r0,t2,SPR_SR
  37
  38 #define ENABLE_INTERRUPTS(t1)                           \
  39         l.mfspr t1,r0,SPR_SR                            ;\
  40         l.ori   t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE)         ;\
  41         l.mtspr r0,t1,SPR_SR
  42
  43 /* =========================================================[ macros ]=== */
  44
  45 /*
  46  * We need to disable interrupts at beginning of RESTORE_ALL
  47  * since interrupt might come in after we've loaded EPC return address
  48  * and overwrite EPC with address somewhere in RESTORE_ALL
  49  * which is of course wrong!
  50  */
  51
  52 #define RESTORE_ALL                                             \
  53         DISABLE_INTERRUPTS(r3,r4)                               ;\
  54         l.lwz   r3,PT_PC(r1)                                    ;\
  55         l.mtspr r0,r3,SPR_EPCR_BASE                             ;\
  56         l.lwz   r3,PT_SR(r1)                                    ;\
  57         l.mtspr r0,r3,SPR_ESR_BASE                              ;\
  58         l.lwz   r2,PT_GPR2(r1)                                  ;\
  59         l.lwz   r3,PT_GPR3(r1)                                  ;\
  60         l.lwz   r4,PT_GPR4(r1)                                  ;\
  61         l.lwz   r5,PT_GPR5(r1)                                  ;\
  62         l.lwz   r6,PT_GPR6(r1)                                  ;\
  63         l.lwz   r7,PT_GPR7(r1)                                  ;\
  64         l.lwz   r8,PT_GPR8(r1)                                  ;\
  65         l.lwz   r9,PT_GPR9(r1)                                  ;\
  66         l.lwz   r10,PT_GPR10(r1)                                        ;\
  67         l.lwz   r11,PT_GPR11(r1)                                        ;\
  68         l.lwz   r12,PT_GPR12(r1)                                        ;\
  69         l.lwz   r13,PT_GPR13(r1)                                        ;\
  70         l.lwz   r14,PT_GPR14(r1)                                        ;\
  71         l.lwz   r15,PT_GPR15(r1)                                        ;\
  72         l.lwz   r16,PT_GPR16(r1)                                        ;\
  73         l.lwz   r17,PT_GPR17(r1)                                        ;\
  74         l.lwz   r18,PT_GPR18(r1)                                        ;\
  75         l.lwz   r19,PT_GPR19(r1)                                        ;\
  76         l.lwz   r20,PT_GPR20(r1)                                        ;\
  77         l.lwz   r21,PT_GPR21(r1)                                        ;\
  78         l.lwz   r22,PT_GPR22(r1)                                        ;\
  79         l.lwz   r23,PT_GPR23(r1)                                        ;\
  80         l.lwz   r24,PT_GPR24(r1)                                        ;\
  81         l.lwz   r25,PT_GPR25(r1)                                        ;\
  82         l.lwz   r26,PT_GPR26(r1)                                        ;\
  83         l.lwz   r27,PT_GPR27(r1)                                        ;\
  84         l.lwz   r28,PT_GPR28(r1)                                        ;\
  85         l.lwz   r29,PT_GPR29(r1)                                        ;\
  86         l.lwz   r30,PT_GPR30(r1)                                        ;\
  87         l.lwz   r31,PT_GPR31(r1)                                        ;\
  88         l.lwz   r1,PT_SP(r1)                                    ;\
  89         l.rfe
  90
  91
  92 #define EXCEPTION_ENTRY(handler)                                \
  93         .global handler                                         ;\
  94 handler:                                                        ;\
  95         /* r1, EPCR, ESR a already saved */                     ;\
  96         l.sw    PT_GPR2(r1),r2                                  ;\
  97         l.sw    PT_GPR3(r1),r3                                  ;\
  98         /* r4 already save */                                   ;\
  99         l.sw    PT_GPR5(r1),r5                                  ;\
 100         l.sw    PT_GPR6(r1),r6                                  ;\
 101         l.sw    PT_GPR7(r1),r7                                  ;\
 102         l.sw    PT_GPR8(r1),r8                                  ;\
 103         l.sw    PT_GPR9(r1),r9                                  ;\
 104         /* r10 already saved */                                 ;\
 105         l.sw    PT_GPR11(r1),r11                                        ;\
 106         /* r12 already saved */                                 ;\
 107         l.sw    PT_GPR13(r1),r13                                        ;\
 108         l.sw    PT_GPR14(r1),r14                                        ;\
 109         l.sw    PT_GPR15(r1),r15                                        ;\
 110         l.sw    PT_GPR16(r1),r16                                        ;\
 111         l.sw    PT_GPR17(r1),r17                                        ;\
 112         l.sw    PT_GPR18(r1),r18                                        ;\
 113         l.sw    PT_GPR19(r1),r19                                        ;\
 114         l.sw    PT_GPR20(r1),r20                                        ;\
 115         l.sw    PT_GPR21(r1),r21                                        ;\
 116         l.sw    PT_GPR22(r1),r22                                        ;\
 117         l.sw    PT_GPR23(r1),r23                                        ;\
 118         l.sw    PT_GPR24(r1),r24                                        ;\
 119         l.sw    PT_GPR25(r1),r25                                        ;\
 120         l.sw    PT_GPR26(r1),r26                                        ;\
 121         l.sw    PT_GPR27(r1),r27                                        ;\
 122         l.sw    PT_GPR28(r1),r28                                        ;\
 123         l.sw    PT_GPR29(r1),r29                                        ;\
 124         /* r30 already save */                                  ;\
 125 /*        l.sw    PT_GPR30(r1),r30*/                                    ;\
 126         l.sw    PT_GPR31(r1),r31                                        ;\
 127         /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
 128         l.addi  r30,r0,-1                                       ;\
 129         l.sw    PT_ORIG_GPR11(r1),r30
 130
 131 #define UNHANDLED_EXCEPTION(handler,vector)                     \
 132         .global handler                                         ;\
 133 handler:                                                        ;\
 134         /* r1, EPCR, ESR already saved */                       ;\
 135         l.sw    PT_GPR2(r1),r2                                  ;\
 136         l.sw    PT_GPR3(r1),r3                                  ;\
 137         l.sw    PT_GPR5(r1),r5                                  ;\
 138         l.sw    PT_GPR6(r1),r6                                  ;\
 139         l.sw    PT_GPR7(r1),r7                                  ;\
 140         l.sw    PT_GPR8(r1),r8                                  ;\
 141         l.sw    PT_GPR9(r1),r9                                  ;\
 142         /* r10 already saved */                                 ;\
 143         l.sw    PT_GPR11(r1),r11                                        ;\
 144         /* r12 already saved */                                 ;\
 145         l.sw    PT_GPR13(r1),r13                                        ;\
 146         l.sw    PT_GPR14(r1),r14                                        ;\
 147         l.sw    PT_GPR15(r1),r15                                        ;\
 148         l.sw    PT_GPR16(r1),r16                                        ;\
 149         l.sw    PT_GPR17(r1),r17                                        ;\
 150         l.sw    PT_GPR18(r1),r18                                        ;\
 151         l.sw    PT_GPR19(r1),r19                                        ;\
 152         l.sw    PT_GPR20(r1),r20                                        ;\
 153         l.sw    PT_GPR21(r1),r21                                        ;\
 154         l.sw    PT_GPR22(r1),r22                                        ;\
 155         l.sw    PT_GPR23(r1),r23                                        ;\
 156         l.sw    PT_GPR24(r1),r24                                        ;\
 157         l.sw    PT_GPR25(r1),r25                                        ;\
 158         l.sw    PT_GPR26(r1),r26                                        ;\
 159         l.sw    PT_GPR27(r1),r27                                        ;\
 160         l.sw    PT_GPR28(r1),r28                                        ;\
 161         l.sw    PT_GPR29(r1),r29                                        ;\
 162         /* r31 already saved */                                 ;\
 163         l.sw    PT_GPR30(r1),r30                                        ;\
 164 /*        l.sw    PT_GPR31(r1),r31      */                              ;\
 165         /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
 166         l.addi  r30,r0,-1                                       ;\
 167         l.sw    PT_ORIG_GPR11(r1),r30                           ;\
 168         l.addi  r3,r1,0                                         ;\
 169         /* r4 is exception EA */                                ;\
 170         l.addi  r5,r0,vector                                    ;\
 171         l.jal   unhandled_exception                             ;\
 172          l.nop                                                  ;\
 173         l.j     _ret_from_exception                             ;\
 174          l.nop
 175
 176 /* clobbers 'reg' */
 177 #define CLEAR_LWA_FLAG(reg)             \
 178         l.movhi reg,hi(lwa_flag)        ;\
 179         l.ori   reg,reg,lo(lwa_flag)    ;\
 180         l.sw    0(reg),r0
 181 /*
 182  * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR
 183  *       contain the same values as when exception we're handling
 184  *       occured. in fact they never do. if you need them use
 185  *       values saved on stack (for SPR_EPC, SPR_ESR) or content
 186  *       of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE()
 187  *       in 'arch/or32/kernel/head.S'
 188  */
 189
 190 /* =====================================================[ exceptions] === */
 191
 192 /* ---[ 0x100: RESET exception ]----------------------------------------- */
 193
 194 EXCEPTION_ENTRY(_tng_kernel_start)
 195         l.jal   _start
 196          l.andi r0,r0,0
 197
 198 /* ---[ 0x200: BUS exception ]------------------------------------------- */
 199
 200 EXCEPTION_ENTRY(_bus_fault_handler)
 201         CLEAR_LWA_FLAG(r3)
 202         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 203         l.jal   do_bus_fault
 204          l.addi  r3,r1,0 /* pt_regs */
 205
 206         l.j     _ret_from_exception
 207          l.nop
 208
 209 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
 210 EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler)
 211         CLEAR_LWA_FLAG(r3)
 212         l.and   r5,r5,r0
 213         l.j     1f
 214          l.nop
 215
 216 EXCEPTION_ENTRY(_data_page_fault_handler)
 217         CLEAR_LWA_FLAG(r3)
 218         /* set up parameters for do_page_fault */
 219         l.ori   r5,r0,0x300                // exception vector
 220 1:
 221         l.addi  r3,r1,0                    // pt_regs
 222         /* r4 set be EXCEPTION_HANDLE */   // effective address of fault
 223
 224         /*
 225          * __PHX__: TODO
 226          *
 227          * all this can be written much simpler. look at
 228          * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
 229          */
 230 #ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX
 231         l.lwz   r6,PT_PC(r3)               // address of an offending insn
 232         l.lwz   r6,0(r6)                   // instruction that caused pf
 233
 234         l.srli  r6,r6,26                   // check opcode for jump insn
 235         l.sfeqi r6,0                       // l.j
 236         l.bf    8f
 237         l.sfeqi r6,1                       // l.jal
 238         l.bf    8f
 239         l.sfeqi r6,3                       // l.bnf
 240         l.bf    8f
 241         l.sfeqi r6,4                       // l.bf
 242         l.bf    8f
 243         l.sfeqi r6,0x11                    // l.jr
 244         l.bf    8f
 245         l.sfeqi r6,0x12                    // l.jalr
 246         l.bf    8f
 247          l.nop
 248
 249         l.j     9f
 250          l.nop
 251
 252 8: // offending insn is in delay slot
 253         l.lwz   r6,PT_PC(r3)               // address of an offending insn
 254         l.addi  r6,r6,4
 255         l.lwz   r6,0(r6)                   // instruction that caused pf
 256         l.srli  r6,r6,26                   // get opcode
 257 9: // offending instruction opcode loaded in r6
 258
 259 #else
 260
 261         l.lwz   r6,PT_SR(r3)               // SR
 262         l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception
 263         l.sfne  r6,r0                      // exception happened in delay slot
 264         l.bnf   7f
 265          l.lwz  r6,PT_PC(r3)               // address of an offending insn
 266
 267         l.addi  r6,r6,4                    // offending insn is in delay slot
 268 7:
 269         l.lwz   r6,0(r6)                   // instruction that caused pf
 270         l.srli  r6,r6,26                   // check opcode for write access
 271 #endif
 272
 273         l.sfgeui r6,0x33                   // check opcode for write access
 274         l.bnf   1f
 275         l.sfleui r6,0x37
 276         l.bnf   1f
 277         l.ori   r6,r0,0x1                  // write access
 278         l.j     2f
 279          l.nop
 280 1:      l.ori   r6,r0,0x0                  // !write access
 281 2:
 282
 283         /* call fault.c handler in or32/mm/fault.c */
 284         l.jal   do_page_fault
 285          l.nop
 286         l.j     _ret_from_exception
 287          l.nop
 288
 289 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
 290 EXCEPTION_ENTRY(_itlb_miss_page_fault_handler)
 291         CLEAR_LWA_FLAG(r3)
 292         l.and   r5,r5,r0
 293         l.j     1f
 294          l.nop
 295
 296 EXCEPTION_ENTRY(_insn_page_fault_handler)
 297         CLEAR_LWA_FLAG(r3)
 298         /* set up parameters for do_page_fault */
 299         l.ori   r5,r0,0x400                // exception vector
 300 1:
 301         l.addi  r3,r1,0                    // pt_regs
 302         /* r4 set be EXCEPTION_HANDLE */   // effective address of fault
 303         l.ori   r6,r0,0x0                  // !write access
 304
 305         /* call fault.c handler in or32/mm/fault.c */
 306         l.jal   do_page_fault
 307          l.nop
 308         l.j     _ret_from_exception
 309          l.nop
 310
 311
 312 /* ---[ 0x500: Timer exception ]----------------------------------------- */
 313
 314 EXCEPTION_ENTRY(_timer_handler)
 315         CLEAR_LWA_FLAG(r3)
 316         l.jal   timer_interrupt
 317          l.addi r3,r1,0 /* pt_regs */
 318
 319         l.j    _ret_from_intr
 320          l.nop
 321
 322 /* ---[ 0x600: Aligment exception ]-------------------------------------- */
 323
 324 EXCEPTION_ENTRY(_alignment_handler)
 325         CLEAR_LWA_FLAG(r3)
 326         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 327         l.jal   do_unaligned_access
 328          l.addi  r3,r1,0 /* pt_regs */
 329
 330         l.j     _ret_from_exception
 331          l.nop
 332
 333 #if 0
 334 EXCEPTION_ENTRY(_aligment_handler)
 335 //        l.mfspr r2,r0,SPR_EEAR_BASE     /* Load the efective addres */
 336         l.addi  r2,r4,0
 337 //        l.mfspr r5,r0,SPR_EPCR_BASE     /* Load the insn address */
 338         l.lwz   r5,PT_PC(r1)
 339
 340         l.lwz   r3,0(r5)                /* Load insn */
 341         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 342
 343         l.sfeqi r4,0x00                 /* Check if the load/store insn is in delay slot */
 344         l.bf    jmp
 345         l.sfeqi r4,0x01
 346         l.bf    jmp
 347         l.sfeqi r4,0x03
 348         l.bf    jmp
 349         l.sfeqi r4,0x04
 350         l.bf    jmp
 351         l.sfeqi r4,0x11
 352         l.bf    jr
 353         l.sfeqi r4,0x12
 354         l.bf    jr
 355         l.nop
 356         l.j     1f
 357         l.addi  r5,r5,4                 /* Increment PC to get return insn address */
 358
 359 jmp:
 360         l.slli  r4,r3,6                 /* Get the signed extended jump length */
 361         l.srai  r4,r4,4
 362
 363         l.lwz   r3,4(r5)                /* Load the real load/store insn */
 364
 365         l.add   r5,r5,r4                /* Calculate jump target address */
 366
 367         l.j     1f
 368         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 369
 370 jr:
 371         l.slli  r4,r3,9                 /* Shift to get the reg nb */
 372         l.andi  r4,r4,0x7c
 373
 374         l.lwz   r3,4(r5)                /* Load the real load/store insn */
 375
 376         l.add   r4,r4,r1                /* Load the jump register value from the stack */
 377         l.lwz   r5,0(r4)
 378
 379         l.srli  r4,r3,26                /* Shift left to get the insn opcode */
 380
 381
 382 1:
 383 //        l.mtspr r0,r5,SPR_EPCR_BASE
 384         l.sw    PT_PC(r1),r5
 385
 386         l.sfeqi r4,0x26
 387         l.bf    lhs
 388         l.sfeqi r4,0x25
 389         l.bf    lhz
 390         l.sfeqi r4,0x22
 391         l.bf    lws
 392         l.sfeqi r4,0x21
 393         l.bf    lwz
 394         l.sfeqi r4,0x37
 395         l.bf    sh
 396         l.sfeqi r4,0x35
 397         l.bf    sw
 398         l.nop
 399
 400 1:      l.j     1b                      /* I don't know what to do */
 401         l.nop
 402
 403 lhs:    l.lbs   r5,0(r2)
 404         l.slli  r5,r5,8
 405         l.lbz   r6,1(r2)
 406         l.or    r5,r5,r6
 407         l.srli  r4,r3,19
 408         l.andi  r4,r4,0x7c
 409         l.add   r4,r4,r1
 410         l.j     align_end
 411         l.sw    0(r4),r5
 412
 413 lhz:    l.lbz   r5,0(r2)
 414         l.slli  r5,r5,8
 415         l.lbz   r6,1(r2)
 416         l.or    r5,r5,r6
 417         l.srli  r4,r3,19
 418         l.andi  r4,r4,0x7c
 419         l.add   r4,r4,r1
 420         l.j     align_end
 421         l.sw    0(r4),r5
 422
 423 lws:    l.lbs   r5,0(r2)
 424         l.slli  r5,r5,24
 425         l.lbz   r6,1(r2)
 426         l.slli  r6,r6,16
 427         l.or    r5,r5,r6
 428         l.lbz   r6,2(r2)
 429         l.slli  r6,r6,8
 430         l.or    r5,r5,r6
 431         l.lbz   r6,3(r2)
 432         l.or    r5,r5,r6
 433         l.srli  r4,r3,19
 434         l.andi  r4,r4,0x7c
 435         l.add   r4,r4,r1
 436         l.j     align_end
 437         l.sw    0(r4),r5
 438
 439 lwz:    l.lbz   r5,0(r2)
 440         l.slli  r5,r5,24
 441         l.lbz   r6,1(r2)
 442         l.slli  r6,r6,16
 443         l.or    r5,r5,r6
 444         l.lbz   r6,2(r2)
 445         l.slli  r6,r6,8
 446         l.or    r5,r5,r6
 447         l.lbz   r6,3(r2)
 448         l.or    r5,r5,r6
 449         l.srli  r4,r3,19
 450         l.andi  r4,r4,0x7c
 451         l.add   r4,r4,r1
 452         l.j     align_end
 453         l.sw    0(r4),r5
 454
 455 sh:
 456         l.srli  r4,r3,9
 457         l.andi  r4,r4,0x7c
 458         l.add   r4,r4,r1
 459         l.lwz   r5,0(r4)
 460         l.sb    1(r2),r5
 461         l.srli  r5,r5,8
 462         l.j     align_end
 463         l.sb    0(r2),r5
 464
 465 sw:
 466         l.srli  r4,r3,9
 467         l.andi  r4,r4,0x7c
 468         l.add   r4,r4,r1
 469         l.lwz   r5,0(r4)
 470         l.sb    3(r2),r5
 471         l.srli  r5,r5,8
 472         l.sb    2(r2),r5
 473         l.srli  r5,r5,8
 474         l.sb    1(r2),r5
 475         l.srli  r5,r5,8
 476         l.j     align_end
 477         l.sb    0(r2),r5
 478
 479 align_end:
 480         l.j    _ret_from_intr
 481         l.nop
 482 #endif
 483
 484 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
 485
 486 EXCEPTION_ENTRY(_illegal_instruction_handler)
 487         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 488         l.jal   do_illegal_instruction
 489          l.addi  r3,r1,0 /* pt_regs */
 490
 491         l.j     _ret_from_exception
 492          l.nop
 493
 494 /* ---[ 0x800: External interrupt exception ]---------------------------- */
 495
 496 EXCEPTION_ENTRY(_external_irq_handler)
 497 #ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK
 498         l.lwz   r4,PT_SR(r1)            // were interrupts enabled ?
 499         l.andi  r4,r4,SPR_SR_IEE
 500         l.sfeqi r4,0
 501         l.bnf   1f                      // ext irq enabled, all ok.
 502         l.nop
 503
 504         l.addi  r1,r1,-0x8
 505         l.movhi r3,hi(42f)
 506         l.ori   r3,r3,lo(42f)
 507         l.sw    0x0(r1),r3
 508         l.jal   printk
 509         l.sw    0x4(r1),r4
 510         l.addi  r1,r1,0x8
 511
 512         .section .rodata, "a"
 513 42:
 514                 .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
 515                 .align 4
 516         .previous
 517
 518         l.ori   r4,r4,SPR_SR_IEE        // fix the bug
 519 //      l.sw    PT_SR(r1),r4
 520 1:
 521 #endif
 522         CLEAR_LWA_FLAG(r3)
 523         l.addi  r3,r1,0
 524         l.movhi r8,hi(do_IRQ)
 525         l.ori   r8,r8,lo(do_IRQ)
 526         l.jalr r8
 527         l.nop
 528         l.j    _ret_from_intr
 529         l.nop
 530
 531 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
 532
 533
 534 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
 535
 536
 537 /* ---[ 0xb00: Range exception ]----------------------------------------- */
 538
 539 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
 540
 541 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
 542
 543 /*
 544  * Syscalls are a special type of exception in that they are
 545  * _explicitly_ invoked by userspace and can therefore be
 546  * held to conform to the same ABI as normal functions with
 547  * respect to whether registers are preserved across the call
 548  * or not.
 549  */
 550
 551 /* Upon syscall entry we just save the callee-saved registers
 552  * and not the call-clobbered ones.
 553  */
 554
 555 _string_syscall_return:
 556         .string "syscall return %ld \n\r\0"
 557         .align 4
 558
 559 ENTRY(_sys_call_handler)
 560         /* syscalls run with interrupts enabled */
 561         ENABLE_INTERRUPTS(r29)          // enable interrupts, r29 is temp
 562
 563         /* r1, EPCR, ESR a already saved */
 564         l.sw    PT_GPR2(r1),r2
 565         /* r3-r8 must be saved because syscall restart relies
 566          * on us being able to restart the syscall args... technically
 567          * they should be clobbered, otherwise
 568          */
 569         l.sw    PT_GPR3(r1),r3
 570         /*
 571          * r4 already saved
 572          * r4 holds the EEAR address of the fault, use it as screatch reg and
 573          * then load the original r4
 574          */
 575         CLEAR_LWA_FLAG(r4)
 576         l.lwz   r4,PT_GPR4(r1)
 577         l.sw    PT_GPR5(r1),r5
 578         l.sw    PT_GPR6(r1),r6
 579         l.sw    PT_GPR7(r1),r7
 580         l.sw    PT_GPR8(r1),r8
 581         l.sw    PT_GPR9(r1),r9
 582         /* r10 already saved */
 583         l.sw    PT_GPR11(r1),r11
 584         /* orig_gpr11 must be set for syscalls */
 585         l.sw    PT_ORIG_GPR11(r1),r11
 586         /* r12,r13 already saved */
 587
 588         /* r14-r28 (even) aren't touched by the syscall fast path below
 589          * so we don't need to save them.  However, the functions that return
 590          * to userspace via a call to switch() DO need to save these because
 591          * switch() effectively clobbers them... saving these registers for
 592          * such functions is handled in their syscall wrappers (see fork, vfork,
 593          * and clone, below).
 594
 595         /* r30 is the only register we clobber in the fast path */
 596         /* r30 already saved */
 597 /*      l.sw    PT_GPR30(r1),r30 */
 598
 599 _syscall_check_trace_enter:
 600         /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
 601         l.lwz   r30,TI_FLAGS(r10)
 602         l.andi  r30,r30,_TIF_SYSCALL_TRACE
 603         l.sfne  r30,r0
 604         l.bf    _syscall_trace_enter
 605          l.nop
 606
 607 _syscall_check:
 608         /* Ensure that the syscall number is reasonable */
 609         l.sfgeui r11,__NR_syscalls
 610         l.bf    _syscall_badsys
 611          l.nop
 612
 613 _syscall_call:
 614         l.movhi r29,hi(sys_call_table)
 615         l.ori   r29,r29,lo(sys_call_table)
 616         l.slli  r11,r11,2
 617         l.add   r29,r29,r11
 618         l.lwz   r29,0(r29)
 619
 620         l.jalr  r29
 621          l.nop
 622
 623 _syscall_return:
 624         /* All syscalls return here... just pay attention to ret_from_fork
 625          * which does it in a round-about way.
 626          */
 627         l.sw    PT_GPR11(r1),r11           // save return value
 628
 629 #if 0
 630 _syscall_debug:
 631         l.movhi r3,hi(_string_syscall_return)
 632         l.ori   r3,r3,lo(_string_syscall_return)
 633         l.ori   r27,r0,1
 634         l.sw    -4(r1),r27
 635         l.sw    -8(r1),r11
 636         l.addi  r1,r1,-8
 637         l.movhi r27,hi(printk)
 638         l.ori   r27,r27,lo(printk)
 639         l.jalr  r27
 640          l.nop
 641         l.addi  r1,r1,8
 642 #endif
 643
 644 _syscall_check_trace_leave:
 645         /* r30 is a callee-saved register so this should still hold the
 646          * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above...
 647          * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
 648          */
 649         l.sfne  r30,r0
 650         l.bf    _syscall_trace_leave
 651          l.nop
 652
 653 /* This is where the exception-return code begins... interrupts need to be
 654  * disabled the rest of the way here because we can't afford to miss any
 655  * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */
 656
 657 _syscall_check_work:
 658         /* Here we need to disable interrupts */
 659         DISABLE_INTERRUPTS(r27,r29)
 660         l.lwz   r30,TI_FLAGS(r10)
 661         l.andi  r30,r30,_TIF_WORK_MASK
 662         l.sfne  r30,r0
 663
 664         l.bnf   _syscall_resume_userspace
 665          l.nop
 666
 667         /* Work pending follows a different return path, so we need to
 668          * make sure that all the call-saved registers get into pt_regs
 669          * before branching...
 670          */
 671         l.sw    PT_GPR14(r1),r14
 672         l.sw    PT_GPR16(r1),r16
 673         l.sw    PT_GPR18(r1),r18
 674         l.sw    PT_GPR20(r1),r20
 675         l.sw    PT_GPR22(r1),r22
 676         l.sw    PT_GPR24(r1),r24
 677         l.sw    PT_GPR26(r1),r26
 678         l.sw    PT_GPR28(r1),r28
 679
 680         /* _work_pending needs to be called with interrupts disabled */
 681         l.j     _work_pending
 682          l.nop
 683
 684 _syscall_resume_userspace:
 685 //      ENABLE_INTERRUPTS(r29)
 686
 687
 688 /* This is the hot path for returning to userspace from a syscall.  If there's
 689  * work to be done and the branch to _work_pending was taken above, then the
 690  * return to userspace will be done via the normal exception return path...
 691  * that path restores _all_ registers and will overwrite the "clobbered"
 692  * registers with whatever garbage is in pt_regs -- that's OK because those
 693  * registers are clobbered anyway and because the extra work is insignificant
 694  * in the context of the extra work that _work_pending is doing.
 695
 696 /* Once again, syscalls are special and only guarantee to preserve the
 697  * same registers as a normal function call */
 698
 699 /* The assumption here is that the registers r14-r28 (even) are untouched and
 700  * don't need to be restored... be sure that that's really the case!
 701  */
 702
 703 /* This is still too much... we should only be restoring what we actually
 704  * clobbered... we should even be using 'scratch' (odd) regs above so that
 705  * we don't need to restore anything, hardly...
 706  */
 707
 708         l.lwz   r2,PT_GPR2(r1)
 709
 710         /* Restore args */
 711         /* r3-r8 are technically clobbered, but syscall restart needs these
 712          * to be restored...
 713          */
 714         l.lwz   r3,PT_GPR3(r1)
 715         l.lwz   r4,PT_GPR4(r1)
 716         l.lwz   r5,PT_GPR5(r1)
 717         l.lwz   r6,PT_GPR6(r1)
 718         l.lwz   r7,PT_GPR7(r1)
 719         l.lwz   r8,PT_GPR8(r1)
 720
 721         l.lwz   r9,PT_GPR9(r1)
 722         l.lwz   r10,PT_GPR10(r1)
 723         l.lwz   r11,PT_GPR11(r1)
 724
 725         /* r30 is the only register we clobber in the fast path */
 726         l.lwz   r30,PT_GPR30(r1)
 727
 728         /* Here we use r13-r19 (odd) as scratch regs */
 729         l.lwz   r13,PT_PC(r1)
 730         l.lwz   r15,PT_SR(r1)
 731         l.lwz   r1,PT_SP(r1)
 732         /* Interrupts need to be disabled for setting EPCR and ESR
 733          * so that another interrupt doesn't come in here and clobber
 734          * them before we can use them for our l.rfe */
 735         DISABLE_INTERRUPTS(r17,r19)
 736         l.mtspr r0,r13,SPR_EPCR_BASE
 737         l.mtspr r0,r15,SPR_ESR_BASE
 738         l.rfe
 739
 740 /* End of hot path!
 741  * Keep the below tracing and error handling out of the hot path...
 742 */
 743
 744 _syscall_trace_enter:
 745         /* Here we pass pt_regs to do_syscall_trace_enter.  Make sure
 746          * that function is really getting all the info it needs as
 747          * pt_regs isn't a complete set of userspace regs, just the
 748          * ones relevant to the syscall...
 749          *
 750          * Note use of delay slot for setting argument.
 751          */
 752         l.jal   do_syscall_trace_enter
 753          l.addi r3,r1,0
 754
 755         /* Restore arguments (not preserved across do_syscall_trace_enter)
 756          * so that we can do the syscall for real and return to the syscall
 757          * hot path.
 758          */
 759         l.lwz   r11,PT_GPR11(r1)
 760         l.lwz   r3,PT_GPR3(r1)
 761         l.lwz   r4,PT_GPR4(r1)
 762         l.lwz   r5,PT_GPR5(r1)
 763         l.lwz   r6,PT_GPR6(r1)
 764         l.lwz   r7,PT_GPR7(r1)
 765
 766         l.j     _syscall_check
 767          l.lwz  r8,PT_GPR8(r1)
 768
 769 _syscall_trace_leave:
 770         l.jal   do_syscall_trace_leave
 771          l.addi r3,r1,0
 772
 773         l.j     _syscall_check_work
 774          l.nop
 775
 776 _syscall_badsys:
 777         /* Here we effectively pretend to have executed an imaginary
 778          * syscall that returns -ENOSYS and then return to the regular
 779          * syscall hot path.
 780          * Note that "return value" is set in the delay slot...
 781          */
 782         l.j     _syscall_return
 783          l.addi r11,r0,-ENOSYS
 784
 785 /******* END SYSCALL HANDLING *******/
 786
 787 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
 788
 789 UNHANDLED_EXCEPTION(_vector_0xd00,0xd00)
 790
 791 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
 792
 793 EXCEPTION_ENTRY(_trap_handler)
 794         CLEAR_LWA_FLAG(r3)
 795         /* r4: EA of fault (set by EXCEPTION_HANDLE) */
 796         l.jal   do_trap
 797          l.addi  r3,r1,0 /* pt_regs */
 798
 799         l.j     _ret_from_exception
 800          l.nop
 801
 802 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
 803
 804 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
 805
 806 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
 807
 808 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
 809
 810 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
 811
 812 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
 813
 814 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
 815
 816 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
 817
 818 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
 819
 820 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
 821
 822 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
 823
 824 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
 825
 826 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
 827
 828 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
 829
 830 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
 831
 832 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
 833
 834 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
 835
 836 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
 837
 838 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
 839
 840 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
 841
 842 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
 843
 844 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
 845
 846 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
 847
 848 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
 849
 850 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
 851
 852 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
 853
 854 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
 855
 856 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
 857
 858 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
 859
 860 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
 861
 862 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
 863
 864 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
 865
 866 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
 867
 868 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
 869
 870 /* ========================================================[ return ] === */
 871
 872 _resume_userspace:
 873         DISABLE_INTERRUPTS(r3,r4)
 874         l.lwz   r4,TI_FLAGS(r10)
 875         l.andi  r13,r4,_TIF_WORK_MASK
 876         l.sfeqi r13,0
 877         l.bf    _restore_all
 878          l.nop
 879
 880 _work_pending:
 881         l.lwz   r5,PT_ORIG_GPR11(r1)
 882         l.sfltsi r5,0
 883         l.bnf   1f
 884          l.nop
 885         l.andi  r5,r5,0
 886 1:
 887         l.jal   do_work_pending
 888          l.ori  r3,r1,0                 /* pt_regs */
 889
 890         l.sfeqi r11,0
 891         l.bf    _restore_all
 892          l.nop
 893         l.sfltsi r11,0
 894         l.bnf   1f
 895          l.nop
 896         l.and   r11,r11,r0
 897         l.ori   r11,r11,__NR_restart_syscall
 898         l.j     _syscall_check_trace_enter
 899          l.nop
 900 1:
 901         l.lwz   r11,PT_ORIG_GPR11(r1)
 902         /* Restore arg registers */
 903         l.lwz   r3,PT_GPR3(r1)
 904         l.lwz   r4,PT_GPR4(r1)
 905         l.lwz   r5,PT_GPR5(r1)
 906         l.lwz   r6,PT_GPR6(r1)
 907         l.lwz   r7,PT_GPR7(r1)
 908         l.j     _syscall_check_trace_enter
 909          l.lwz  r8,PT_GPR8(r1)
 910
 911 _restore_all:
 912         RESTORE_ALL
 913         /* This returns to userspace code */
 914
 915
 916 ENTRY(_ret_from_intr)
 917 ENTRY(_ret_from_exception)
 918         l.lwz   r4,PT_SR(r1)
 919         l.andi  r3,r4,SPR_SR_SM
 920         l.sfeqi r3,0
 921         l.bnf   _restore_all
 922          l.nop
 923         l.j     _resume_userspace
 924          l.nop
 925
 926 ENTRY(ret_from_fork)
 927         l.jal   schedule_tail
 928          l.nop
 929
 930         /* Check if we are a kernel thread */
 931         l.sfeqi r20,0
 932         l.bf    1f
 933          l.nop
 934
 935         /* ...we are a kernel thread so invoke the requested callback */
 936         l.jalr  r20
 937          l.or   r3,r22,r0
 938
 939 1:
 940         /* _syscall_returns expect r11 to contain return value */
 941         l.lwz   r11,PT_GPR11(r1)
 942
 943         /* The syscall fast path return expects call-saved registers
 944          * r12-r28 to be untouched, so we restore them here as they
 945          * will have been effectively clobbered when arriving here
 946          * via the call to switch()
 947          */
 948         l.lwz   r12,PT_GPR12(r1)
 949         l.lwz   r14,PT_GPR14(r1)
 950         l.lwz   r16,PT_GPR16(r1)
 951         l.lwz   r18,PT_GPR18(r1)
 952         l.lwz   r20,PT_GPR20(r1)
 953         l.lwz   r22,PT_GPR22(r1)
 954         l.lwz   r24,PT_GPR24(r1)
 955         l.lwz   r26,PT_GPR26(r1)
 956         l.lwz   r28,PT_GPR28(r1)
 957
 958         l.j     _syscall_return
 959          l.nop
 960
 961 /* ========================================================[ switch ] === */
 962
 963 /*
 964  * This routine switches between two different tasks.  The process
 965  * state of one is saved on its kernel stack.  Then the state
 966  * of the other is restored from its kernel stack.  The memory
 967  * management hardware is updated to the second process's state.
 968  * Finally, we can return to the second process, via the 'return'.
 969  *
 970  * Note: there are two ways to get to the "going out" portion
 971  * of this code; either by coming in via the entry (_switch)
 972  * or via "fork" which must set up an environment equivalent
 973  * to the "_switch" path.  If you change this (or in particular, the
 974  * SAVE_REGS macro), you'll have to change the fork code also.
 975  */
 976
 977
 978 /* _switch MUST never lay on page boundry, cause it runs from
 979  * effective addresses and beeing interrupted by iTLB miss would kill it.
 980  * dTLB miss seams to never accour in the bad place since data accesses
 981  * are from task structures which are always page aligned.
 982  *
 983  * The problem happens in RESTORE_ALL_NO_R11 where we first set the EPCR
 984  * register, then load the previous register values and only at the end call
 985  * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
 986  * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
 987  * holds for ESR)
 988  *
 989  * To avoid this problems it is sufficient to align _switch to
 990  * some nice round number smaller than it's size...
 991  */
 992
 993 /* ABI rules apply here... we either enter _switch via schedule() or via
 994  * an imaginary call to which we shall return at return_from_fork.  Either
 995  * way, we are a function call and only need to preserve the callee-saved
 996  * registers when we return.  As such, we don't need to save the registers
 997  * on the stack that we won't be returning as they were...
 998  */
 999
1000         .align 0x400
1001 ENTRY(_switch)
1002         /* We don't store SR as _switch only gets called in a context where
1003          * the SR will be the same going in and coming out... */
1004
1005         /* Set up new pt_regs struct for saving task state */
1006         l.addi  r1,r1,-(INT_FRAME_SIZE)
1007
1008         /* No need to store r1/PT_SP as it goes into KSP below */
1009         l.sw    PT_GPR2(r1),r2
1010         l.sw    PT_GPR9(r1),r9
1011         /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1012          * and expects r12 to be callee-saved... */
1013         l.sw    PT_GPR12(r1),r12
1014         l.sw    PT_GPR14(r1),r14
1015         l.sw    PT_GPR16(r1),r16
1016         l.sw    PT_GPR18(r1),r18
1017         l.sw    PT_GPR20(r1),r20
1018         l.sw    PT_GPR22(r1),r22
1019         l.sw    PT_GPR24(r1),r24
1020         l.sw    PT_GPR26(r1),r26
1021         l.sw    PT_GPR28(r1),r28
1022         l.sw    PT_GPR30(r1),r30
1023
1024         l.addi  r11,r10,0                       /* Save old 'current' to 'last' return value*/
1025
1026         /* We use thread_info->ksp for storing the address of the above
1027          * structure so that we can get back to it later... we don't want
1028          * to lose the value of thread_info->ksp, though, so store it as
1029          * pt_regs->sp so that we can easily restore it when we are made
1030          * live again...
1031          */
1032
1033         /* Save the old value of thread_info->ksp as pt_regs->sp */
1034         l.lwz   r29,TI_KSP(r10)
1035         l.sw    PT_SP(r1),r29
1036
1037         /* Swap kernel stack pointers */
1038         l.sw    TI_KSP(r10),r1                  /* Save old stack pointer */
1039         l.or    r10,r4,r0                       /* Set up new current_thread_info */
1040         l.lwz   r1,TI_KSP(r10)                  /* Load new stack pointer */
1041
1042         /* Restore the old value of thread_info->ksp */
1043         l.lwz   r29,PT_SP(r1)
1044         l.sw    TI_KSP(r10),r29
1045
1046         /* ...and restore the registers, except r11 because the return value
1047          * has already been set above.
1048          */
1049         l.lwz   r2,PT_GPR2(r1)
1050         l.lwz   r9,PT_GPR9(r1)
1051         /* No need to restore r10 */
1052         /* ...and do not restore r11 */
1053
1054         /* This is wrong, r12 shouldn't be here... but GCC is broken for the time being
1055          * and expects r12 to be callee-saved... */
1056         l.lwz   r12,PT_GPR12(r1)
1057         l.lwz   r14,PT_GPR14(r1)
1058         l.lwz   r16,PT_GPR16(r1)
1059         l.lwz   r18,PT_GPR18(r1)
1060         l.lwz   r20,PT_GPR20(r1)
1061         l.lwz   r22,PT_GPR22(r1)
1062         l.lwz   r24,PT_GPR24(r1)
1063         l.lwz   r26,PT_GPR26(r1)
1064         l.lwz   r28,PT_GPR28(r1)
1065         l.lwz   r30,PT_GPR30(r1)
1066
1067         /* Unwind stack to pre-switch state */
1068         l.addi  r1,r1,(INT_FRAME_SIZE)
1069
1070         /* Return via the link-register back to where we 'came from', where
1071          * that may be either schedule(), ret_from_fork(), or
1072          * ret_from_kernel_thread().  If we are returning to a new thread,
1073          * we are expected to have set up the arg to schedule_tail already,
1074          * hence we do so here unconditionally:
1075          */
1076         l.lwz   r3,TI_TASK(r3)          /* Load 'prev' as schedule_tail arg */
1077         l.jr    r9
1078          l.nop
1079
1080 /* ==================================================================== */
1081
1082 /* These all use the delay slot for setting the argument register, so the
1083  * jump is always happening after the l.addi instruction.
1084  *
1085  * These are all just wrappers that don't touch the link-register r9, so the
1086  * return from the "real" syscall function will return back to the syscall
1087  * code that did the l.jal that brought us here.
1088  */
1089
1090 /* fork requires that we save all the callee-saved registers because they
1091  * are all effectively clobbered by the call to _switch.  Here we store
1092  * all the registers that aren't touched by the syscall fast path and thus
1093  * weren't saved there.
1094  */
1095
1096 _fork_save_extra_regs_and_call:
1097         l.sw    PT_GPR14(r1),r14
1098         l.sw    PT_GPR16(r1),r16
1099         l.sw    PT_GPR18(r1),r18
1100         l.sw    PT_GPR20(r1),r20
1101         l.sw    PT_GPR22(r1),r22
1102         l.sw    PT_GPR24(r1),r24
1103         l.sw    PT_GPR26(r1),r26
1104         l.jr    r29
1105          l.sw    PT_GPR28(r1),r28
1106
1107 ENTRY(__sys_clone)
1108         l.movhi r29,hi(sys_clone)
1109         l.ori   r29,r29,lo(sys_clone)
1110         l.j     _fork_save_extra_regs_and_call
1111          l.addi r7,r1,0
1112
1113 ENTRY(__sys_fork)
1114         l.movhi r29,hi(sys_fork)
1115         l.ori   r29,r29,lo(sys_fork)
1116         l.j     _fork_save_extra_regs_and_call
1117          l.addi r3,r1,0
1118
1119 ENTRY(sys_rt_sigreturn)
1120         l.jal   _sys_rt_sigreturn
1121          l.addi r3,r1,0
1122         l.sfne  r30,r0
1123         l.bnf   _no_syscall_trace
1124          l.nop
1125         l.jal   do_syscall_trace_leave
1126          l.addi r3,r1,0
1127 _no_syscall_trace:
1128         l.j     _resume_userspace
1129          l.nop
1130
1131 /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1132  * The functions takes a variable number of parameters depending on which
1133  * particular flavour of atomic you want... parameter 1 is a flag identifying
1134  * the atomic in question.  Currently, this function implements the
1135  * following variants:
1136  *
1137  * XCHG:
1138  *  @flag: 1
1139  *  @ptr1:
1140  *  @ptr2:
1141  * Atomically exchange the values in pointers 1 and 2.
1142  *
1143  */
1144
1145 ENTRY(sys_or1k_atomic)
1146         /* FIXME: This ignores r3 and always does an XCHG */
1147         DISABLE_INTERRUPTS(r17,r19)
1148         l.lwz   r29,0(r4)
1149         l.lwz   r27,0(r5)
1150         l.sw    0(r4),r27
1151         l.sw    0(r5),r29
1152         ENABLE_INTERRUPTS(r17)
1153         l.jr    r9
1154          l.or   r11,r0,r0
1155
1156 /* ============================================================[ EOF ]=== */