]> git.kernelconcepts.de Git - karo-tx-linux.git/blob - arch/powerpc/boot/dts/xpedite5330.dts
arm: imx6: defconfig: update tx6 defconfigs
[karo-tx-linux.git] / arch / powerpc / boot / dts / xpedite5330.dts
1 /*
2  * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
3  * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
4  *
5  * XPedite5330 3U CompactPCI module based on MPC8572E
6  *
7  * This is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 /dts-v1/;
13 / {
14         model = "xes,xpedite5330";
15         compatible = "xes,xpedite5330", "xes,MPC8572";
16         #address-cells = <2>;
17         #size-cells = <2>;
18         form-factor = "3U CompactPCI";
19         boot-bank = <0x0>;      /* 0: Primary flash, 1: Secondary flash */
20
21         aliases {
22                 ethernet0 = &enet0;
23                 ethernet1 = &enet1;
24                 serial0 = &serial0;
25                 serial1 = &serial1;
26                 pci0 = &pci0;
27                 pci1 = &pci1;
28                 pci2 = &pci2;
29         };
30
31         pmcslots {
32                 #address-cells = <1>;
33                 #size-cells = <0>;
34
35                 pmcslot@0 {
36                         cell-index = <0>;
37                         /*
38                          * boolean properties (true if defined):
39                          *     monarch;
40                          *     module-present;
41                          */
42                 };
43         };
44
45         xmcslots {
46                 #address-cells = <1>;
47                 #size-cells = <0>;
48
49                 xmcslot@0 {
50                         cell-index = <0>;
51                         /*
52                          * boolean properties (true if defined):
53                          *     module-present;
54                          */
55                 };
56         };
57
58         cpci {
59                 /*
60                  * boolean properties (true if defined):
61                  *     system-controller;
62                  */
63                 system-controller;
64         };
65
66         cpus {
67                 #address-cells = <1>;
68                 #size-cells = <0>;
69
70                 PowerPC,8572@0 {
71                         device_type = "cpu";
72                         reg = <0x0>;
73                         d-cache-line-size = <32>;       // 32 bytes
74                         i-cache-line-size = <32>;       // 32 bytes
75                         d-cache-size = <0x8000>;                // L1, 32K
76                         i-cache-size = <0x8000>;                // L1, 32K
77                         timebase-frequency = <0>;
78                         bus-frequency = <0>;
79                         clock-frequency = <0>;
80                         next-level-cache = <&L2>;
81                 };
82
83                 PowerPC,8572@1 {
84                         device_type = "cpu";
85                         reg = <0x1>;
86                         d-cache-line-size = <32>;       // 32 bytes
87                         i-cache-line-size = <32>;       // 32 bytes
88                         d-cache-size = <0x8000>;                // L1, 32K
89                         i-cache-size = <0x8000>;                // L1, 32K
90                         timebase-frequency = <0>;
91                         bus-frequency = <0>;
92                         clock-frequency = <0>;
93                         next-level-cache = <&L2>;
94                 };
95         };
96
97         memory {
98                 device_type = "memory";
99                 reg = <0x0 0x0 0x0 0x0>;        // Filled in by U-Boot
100         };
101
102         localbus@ef005000 {
103                 #address-cells = <2>;
104                 #size-cells = <1>;
105                 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
106                 reg = <0 0xef005000 0 0x1000>;
107                 interrupts = <19 2>;
108                 interrupt-parent = <&mpic>;
109                 /* Local bus region mappings */
110                 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
111                           1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
112                           2 0 0 0xef800000 0x40000   /* CS2: NAND CE1 */
113                           3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
114
115                 nor-boot@0,0 {
116                         compatible = "amd,s29gl01gp", "cfi-flash";
117                         bank-width = <2>;
118                         reg = <0 0 0x8000000>; /* 128MB */
119                         #address-cells = <1>;
120                         #size-cells = <1>;
121                         partition@0 {
122                                 label = "Primary user space";
123                                 reg = <0x00000000 0x6f00000>; /* 111 MB */
124                         };
125                         partition@6f00000 {
126                                 label = "Primary kernel";
127                                 reg = <0x6f00000 0x1000000>; /* 16 MB */
128                         };
129                         partition@7f00000 {
130                                 label = "Primary DTB";
131                                 reg = <0x7f00000 0x40000>; /* 256 KB */
132                         };
133                         partition@7f40000 {
134                                 label = "Primary U-Boot environment";
135                                 reg = <0x7f40000 0x40000>; /* 256 KB */
136                         };
137                         partition@7f80000 {
138                                 label = "Primary U-Boot";
139                                 reg = <0x7f80000 0x80000>; /* 512 KB */
140                                 read-only;
141                         };
142                 };
143
144                 nor-alternate@1,0 {
145                         compatible = "amd,s29gl01gp", "cfi-flash";
146                         bank-width = <2>;
147                         //reg = <0xf0000000 0x08000000>; /* 128MB */
148                         reg = <1 0 0x8000000>; /* 128MB */
149                         #address-cells = <1>;
150                         #size-cells = <1>;
151                         partition@0 {
152                                 label = "Secondary user space";
153                                 reg = <0x00000000 0x6f00000>; /* 111 MB */
154                         };
155                         partition@6f00000 {
156                                 label = "Secondary kernel";
157                                 reg = <0x6f00000 0x1000000>; /* 16 MB */
158                         };
159                         partition@7f00000 {
160                                 label = "Secondary DTB";
161                                 reg = <0x7f00000 0x40000>; /* 256 KB */
162                         };
163                         partition@7f40000 {
164                                 label = "Secondary U-Boot environment";
165                                 reg = <0x7f40000 0x40000>; /* 256 KB */
166                         };
167                         partition@7f80000 {
168                                 label = "Secondary U-Boot";
169                                 reg = <0x7f80000 0x80000>; /* 512 KB */
170                                 read-only;
171                         };
172                 };
173
174                 nand@2,0 {
175                         #address-cells = <1>;
176                         #size-cells = <1>;
177                         /*
178                          * Actual part could be ST Micro NAND08GW3B2A (1 GB),
179                          * Micron MT29F8G08DAA (2x 512 MB), or Micron
180                          * MT29F16G08FAA (2x 1 GB), depending on the build
181                          * configuration
182                          */
183                         compatible = "fsl,mpc8572-fcm-nand",
184                                      "fsl,elbc-fcm-nand";
185                         reg = <2 0 0x40000>;
186                         /* U-Boot should fix this up if chip size > 1 GB */
187                         partition@0 {
188                                 label = "NAND Filesystem";
189                                 reg = <0 0x40000000>;
190                         };
191                 };
192
193         };
194
195         soc8572@ef000000 {
196                 #address-cells = <1>;
197                 #size-cells = <1>;
198                 device_type = "soc";
199                 compatible = "fsl,mpc8572-immr", "simple-bus";
200                 ranges = <0x0 0 0xef000000 0x100000>;
201                 bus-frequency = <0>;            // Filled out by uboot.
202
203                 ecm-law@0 {
204                         compatible = "fsl,ecm-law";
205                         reg = <0x0 0x1000>;
206                         fsl,num-laws = <12>;
207                 };
208
209                 ecm@1000 {
210                         compatible = "fsl,mpc8572-ecm", "fsl,ecm";
211                         reg = <0x1000 0x1000>;
212                         interrupts = <17 2>;
213                         interrupt-parent = <&mpic>;
214                 };
215
216                 memory-controller@2000 {
217                         compatible = "fsl,mpc8572-memory-controller";
218                         reg = <0x2000 0x1000>;
219                         interrupt-parent = <&mpic>;
220                         interrupts = <18 2>;
221                 };
222
223                 memory-controller@6000 {
224                         compatible = "fsl,mpc8572-memory-controller";
225                         reg = <0x6000 0x1000>;
226                         interrupt-parent = <&mpic>;
227                         interrupts = <18 2>;
228                 };
229
230                 L2: l2-cache-controller@20000 {
231                         compatible = "fsl,mpc8572-l2-cache-controller";
232                         reg = <0x20000 0x1000>;
233                         cache-line-size = <32>; // 32 bytes
234                         cache-size = <0x100000>; // L2, 1M
235                         interrupt-parent = <&mpic>;
236                         interrupts = <16 2>;
237                 };
238
239                 i2c@3000 {
240                         #address-cells = <1>;
241                         #size-cells = <0>;
242                         cell-index = <0>;
243                         compatible = "fsl-i2c";
244                         reg = <0x3000 0x100>;
245                         interrupts = <43 2>;
246                         interrupt-parent = <&mpic>;
247                         dfsrr;
248
249                         temp-sensor@48 {
250                                 compatible = "dallas,ds1631", "dallas,ds1621";
251                                 reg = <0x48>;
252                         };
253
254                         temp-sensor@4c {
255                                 compatible = "adi,adt7461";
256                                 reg = <0x4c>;
257                         };
258
259                         cpu-supervisor@51 {
260                                 compatible = "dallas,ds4510";
261                                 reg = <0x51>;
262                         };
263
264                         eeprom@54 {
265                                 compatible = "atmel,at24c128b";
266                                 reg = <0x54>;
267                         };
268
269                         rtc@68 {
270                                 compatible = "stm,m41t00",
271                                              "dallas,ds1338";
272                                 reg = <0x68>;
273                         };
274
275                         pcie-switch@70 {
276                                 compatible = "plx,pex8518";
277                                 reg = <0x70>;
278                         };
279
280                         gpio1: gpio@18 {
281                                 compatible = "nxp,pca9557";
282                                 reg = <0x18>;
283                                 #gpio-cells = <2>;
284                                 gpio-controller;
285                                 polarity = <0x00>;
286                         };
287
288                         gpio2: gpio@1c {
289                                 compatible = "nxp,pca9557";
290                                 reg = <0x1c>;
291                                 #gpio-cells = <2>;
292                                 gpio-controller;
293                                 polarity = <0x00>;
294                         };
295
296                         gpio3: gpio@1e {
297                                 compatible = "nxp,pca9557";
298                                 reg = <0x1e>;
299                                 #gpio-cells = <2>;
300                                 gpio-controller;
301                                 polarity = <0x00>;
302                         };
303
304                         gpio4: gpio@1f {
305                                 compatible = "nxp,pca9557";
306                                 reg = <0x1f>;
307                                 #gpio-cells = <2>;
308                                 gpio-controller;
309                                 polarity = <0x00>;
310                         };
311                 };
312
313                 i2c@3100 {
314                         #address-cells = <1>;
315                         #size-cells = <0>;
316                         cell-index = <1>;
317                         compatible = "fsl-i2c";
318                         reg = <0x3100 0x100>;
319                         interrupts = <43 2>;
320                         interrupt-parent = <&mpic>;
321                         dfsrr;
322                 };
323
324                 dma@c300 {
325                         #address-cells = <1>;
326                         #size-cells = <1>;
327                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
328                         reg = <0xc300 0x4>;
329                         ranges = <0x0 0xc100 0x200>;
330                         cell-index = <1>;
331                         dma-channel@0 {
332                                 compatible = "fsl,mpc8572-dma-channel",
333                                                 "fsl,eloplus-dma-channel";
334                                 reg = <0x0 0x80>;
335                                 cell-index = <0>;
336                                 interrupt-parent = <&mpic>;
337                                 interrupts = <76 2>;
338                         };
339                         dma-channel@80 {
340                                 compatible = "fsl,mpc8572-dma-channel",
341                                                 "fsl,eloplus-dma-channel";
342                                 reg = <0x80 0x80>;
343                                 cell-index = <1>;
344                                 interrupt-parent = <&mpic>;
345                                 interrupts = <77 2>;
346                         };
347                         dma-channel@100 {
348                                 compatible = "fsl,mpc8572-dma-channel",
349                                                 "fsl,eloplus-dma-channel";
350                                 reg = <0x100 0x80>;
351                                 cell-index = <2>;
352                                 interrupt-parent = <&mpic>;
353                                 interrupts = <78 2>;
354                         };
355                         dma-channel@180 {
356                                 compatible = "fsl,mpc8572-dma-channel",
357                                                 "fsl,eloplus-dma-channel";
358                                 reg = <0x180 0x80>;
359                                 cell-index = <3>;
360                                 interrupt-parent = <&mpic>;
361                                 interrupts = <79 2>;
362                         };
363                 };
364
365                 dma@21300 {
366                         #address-cells = <1>;
367                         #size-cells = <1>;
368                         compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
369                         reg = <0x21300 0x4>;
370                         ranges = <0x0 0x21100 0x200>;
371                         cell-index = <0>;
372                         dma-channel@0 {
373                                 compatible = "fsl,mpc8572-dma-channel",
374                                                 "fsl,eloplus-dma-channel";
375                                 reg = <0x0 0x80>;
376                                 cell-index = <0>;
377                                 interrupt-parent = <&mpic>;
378                                 interrupts = <20 2>;
379                         };
380                         dma-channel@80 {
381                                 compatible = "fsl,mpc8572-dma-channel",
382                                                 "fsl,eloplus-dma-channel";
383                                 reg = <0x80 0x80>;
384                                 cell-index = <1>;
385                                 interrupt-parent = <&mpic>;
386                                 interrupts = <21 2>;
387                         };
388                         dma-channel@100 {
389                                 compatible = "fsl,mpc8572-dma-channel",
390                                                 "fsl,eloplus-dma-channel";
391                                 reg = <0x100 0x80>;
392                                 cell-index = <2>;
393                                 interrupt-parent = <&mpic>;
394                                 interrupts = <22 2>;
395                         };
396                         dma-channel@180 {
397                                 compatible = "fsl,mpc8572-dma-channel",
398                                                 "fsl,eloplus-dma-channel";
399                                 reg = <0x180 0x80>;
400                                 cell-index = <3>;
401                                 interrupt-parent = <&mpic>;
402                                 interrupts = <23 2>;
403                         };
404                 };
405
406                 /* eTSEC 1 */
407                 enet0: ethernet@24000 {
408                         #address-cells = <1>;
409                         #size-cells = <1>;
410                         cell-index = <0>;
411                         device_type = "network";
412                         model = "eTSEC";
413                         compatible = "gianfar";
414                         reg = <0x24000 0x1000>;
415                         ranges = <0x0 0x24000 0x1000>;
416                         local-mac-address = [ 00 00 00 00 00 00 ];
417                         interrupts = <29 2 30 2 34 2>;
418                         interrupt-parent = <&mpic>;
419                         tbi-handle = <&tbi0>;
420                         phy-handle = <&phy0>;
421                         phy-connection-type = "sgmii";
422
423                         mdio@520 {
424                                 #address-cells = <1>;
425                                 #size-cells = <0>;
426                                 compatible = "fsl,gianfar-mdio";
427                                 reg = <0x520 0x20>;
428
429                                 phy0: ethernet-phy@1 {
430                                         interrupt-parent = <&mpic>;
431                                         interrupts = <8 1>;
432                                         reg = <0x1>;
433                                 };
434                                 phy1: ethernet-phy@2 {
435                                         interrupt-parent = <&mpic>;
436                                         interrupts = <8 1>;
437                                         reg = <0x2>;
438                                 };
439                                 tbi0: tbi-phy@11 {
440                                         reg = <0x11>;
441                                         device_type = "tbi-phy";
442                                 };
443                         };
444                 };
445
446                 /* eTSEC 2 */
447                 enet1: ethernet@25000 {
448                         #address-cells = <1>;
449                         #size-cells = <1>;
450                         cell-index = <1>;
451                         device_type = "network";
452                         model = "eTSEC";
453                         compatible = "gianfar";
454                         reg = <0x25000 0x1000>;
455                         ranges = <0x0 0x25000 0x1000>;
456                         local-mac-address = [ 00 00 00 00 00 00 ];
457                         interrupts = <35 2 36 2 40 2>;
458                         interrupt-parent = <&mpic>;
459                         tbi-handle = <&tbi1>;
460                         phy-handle = <&phy1>;
461                         phy-connection-type = "sgmii";
462
463                         mdio@520 {
464                                 #address-cells = <1>;
465                                 #size-cells = <0>;
466                                 compatible = "fsl,gianfar-tbi";
467                                 reg = <0x520 0x20>;
468
469                                 tbi1: tbi-phy@11 {
470                                         reg = <0x11>;
471                                         device_type = "tbi-phy";
472                                 };
473                         };
474                 };
475
476                 /* UART0 */
477                 serial0: serial@4500 {
478                         cell-index = <0>;
479                         device_type = "serial";
480                         compatible = "fsl,ns16550", "ns16550";
481                         reg = <0x4500 0x100>;
482                         clock-frequency = <0>;
483                         interrupts = <42 2>;
484                         interrupt-parent = <&mpic>;
485                 };
486
487                 /* UART1 */
488                 serial1: serial@4600 {
489                         cell-index = <1>;
490                         device_type = "serial";
491                         compatible = "fsl,ns16550", "ns16550";
492                         reg = <0x4600 0x100>;
493                         clock-frequency = <0>;
494                         interrupts = <42 2>;
495                         interrupt-parent = <&mpic>;
496                 };
497
498                 global-utilities@e0000 {        //global utilities block
499                         compatible = "fsl,mpc8572-guts";
500                         reg = <0xe0000 0x1000>;
501                         fsl,has-rstcr;
502                 };
503
504                 msi@41600 {
505                         compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
506                         reg = <0x41600 0x80>;
507                         msi-available-ranges = <0 0x100>;
508                         interrupts = <
509                                 0xe0 0
510                                 0xe1 0
511                                 0xe2 0
512                                 0xe3 0
513                                 0xe4 0
514                                 0xe5 0
515                                 0xe6 0
516                                 0xe7 0>;
517                         interrupt-parent = <&mpic>;
518                 };
519
520                 crypto@30000 {
521                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
522                                      "fsl,sec2.1", "fsl,sec2.0";
523                         reg = <0x30000 0x10000>;
524                         interrupts = <45 2 58 2>;
525                         interrupt-parent = <&mpic>;
526                         fsl,num-channels = <4>;
527                         fsl,channel-fifo-len = <24>;
528                         fsl,exec-units-mask = <0x9fe>;
529                         fsl,descriptor-types-mask = <0x3ab0ebf>;
530                 };
531
532                 mpic: pic@40000 {
533                         interrupt-controller;
534                         #address-cells = <0>;
535                         #interrupt-cells = <2>;
536                         reg = <0x40000 0x40000>;
537                         compatible = "chrp,open-pic";
538                         device_type = "open-pic";
539                 };
540
541                 gpio0: gpio@f000 {
542                         compatible = "fsl,mpc8572-gpio";
543                         reg = <0xf000 0x1000>;
544                         interrupts = <47 2>;
545                         interrupt-parent = <&mpic>;
546                         #gpio-cells = <2>;
547                         gpio-controller;
548                 };
549
550                 gpio-leds {
551                         compatible = "gpio-leds";
552
553                         heartbeat {
554                                 label = "Heartbeat";
555                                 gpios = <&gpio0 4 1>;
556                                 linux,default-trigger = "heartbeat";
557                         };
558
559                         yellow {
560                                 label = "Yellow";
561                                 gpios = <&gpio0 5 1>;
562                         };
563
564                         red {
565                                 label = "Red";
566                                 gpios = <&gpio0 6 1>;
567                         };
568
569                         green {
570                                 label = "Green";
571                                 gpios = <&gpio0 7 1>;
572                         };
573                 };
574
575                 /* PME (pattern-matcher) */
576                 pme@10000 {
577                         compatible = "fsl,mpc8572-pme", "pme8572";
578                         reg = <0x10000 0x5000>;
579                         interrupts = <57 2 64 2 65 2 66 2 67 2>;
580                         interrupt-parent = <&mpic>;
581                 };
582
583                 tlu@2f000 {
584                         compatible = "fsl,mpc8572-tlu", "fsl_tlu";
585                         reg = <0x2f000 0x1000>;
586                         interupts = <61 2 >;
587                         interrupt-parent = <&mpic>;
588                 };
589
590                 tlu@15000 {
591                         compatible = "fsl,mpc8572-tlu", "fsl_tlu";
592                         reg = <0x15000 0x1000>;
593                         interupts = <75 2>;
594                         interrupt-parent = <&mpic>;
595                 };
596         };
597
598         /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
599         pci0: pcie@ef008000 {
600                 compatible = "fsl,mpc8548-pcie";
601                 device_type = "pci";
602                 #interrupt-cells = <1>;
603                 #size-cells = <2>;
604                 #address-cells = <3>;
605                 reg = <0 0xef008000 0 0x1000>;
606                 bus-range = <0 255>;
607                 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
608                           0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
609                 clock-frequency = <33333333>;
610                 interrupt-parent = <&mpic>;
611                 interrupts = <24 2>;
612                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
613                 interrupt-map = <
614                         0x0 0x0 0x0 0x1 &mpic 0x0 0x1
615                         0x0 0x0 0x0 0x2 &mpic 0x1 0x1
616                         0x0 0x0 0x0 0x3 &mpic 0x2 0x1
617                         0x0 0x0 0x0 0x4 &mpic 0x3 0x1
618                         >;
619                 pcie@0 {
620                         reg = <0x0 0x0 0x0 0x0 0x0>;
621                         #size-cells = <2>;
622                         #address-cells = <3>;
623                         device_type = "pci";
624                         ranges = <0x02000000 0x0 0xe0000000
625                                   0x02000000 0x0 0xe0000000
626                                   0x0 0x10000000
627
628                                   0x01000000 0x0 0x0
629                                   0x01000000 0x0 0x0
630                                   0x0 0x100000>;
631                 };
632         };
633
634         /* PCI Express controller 2, PMC module via PEX8112 bridge */
635         pci1: pcie@ef009000 {
636                 compatible = "fsl,mpc8548-pcie";
637                 device_type = "pci";
638                 #interrupt-cells = <1>;
639                 #size-cells = <2>;
640                 #address-cells = <3>;
641                 reg = <0 0xef009000 0 0x1000>;
642                 bus-range = <0 255>;
643                 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
644                           0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
645                 clock-frequency = <33333333>;
646                 interrupt-parent = <&mpic>;
647                 interrupts = <25 2>;
648                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
649                 interrupt-map = <
650                         /* IDSEL 0x0 */
651                         0x0 0x0 0x0 0x1 &mpic 0x4 0x1
652                         0x0 0x0 0x0 0x2 &mpic 0x5 0x1
653                         0x0 0x0 0x0 0x3 &mpic 0x6 0x1
654                         0x0 0x0 0x0 0x4 &mpic 0x7 0x1
655                         >;
656                 pcie@0 {
657                         reg = <0x0 0x0 0x0 0x0 0x0>;
658                         #size-cells = <2>;
659                         #address-cells = <3>;
660                         device_type = "pci";
661                         ranges = <0x2000000 0x0 0xc0000000
662                                   0x2000000 0x0 0xc0000000
663                                   0x0 0x10000000
664
665                                   0x1000000 0x0 0x0
666                                   0x1000000 0x0 0x0
667                                   0x0 0x100000>;
668                 };
669         };
670
671         /* PCI Express controller 1, XMC P15 */
672         pci2: pcie@ef00a000 {
673                 compatible = "fsl,mpc8548-pcie";
674                 device_type = "pci";
675                 #interrupt-cells = <1>;
676                 #size-cells = <2>;
677                 #address-cells = <3>;
678                 reg = <0 0xef00a000 0 0x1000>;
679                 bus-range = <0 255>;
680                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
681                           0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
682                 clock-frequency = <33333333>;
683                 interrupt-parent = <&mpic>;
684                 interrupts = <26 2>;
685                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
686                 interrupt-map = <
687                         /* IDSEL 0x0 */
688                         0x0 0x0 0x0 0x1 &mpic 0x0 0x1
689                         0x0 0x0 0x0 0x2 &mpic 0x1 0x1
690                         0x0 0x0 0x0 0x3 &mpic 0x2 0x1
691                         0x0 0x0 0x0 0x4 &mpic 0x3 0x1
692                         >;
693                 pcie@0 {
694                         reg = <0x0 0x0 0x0 0x0 0x0>;
695                         #size-cells = <2>;
696                         #address-cells = <3>;
697                         device_type = "pci";
698                         ranges = <0x2000000 0x0 0x80000000
699                                   0x2000000 0x0 0x80000000
700                                   0x0 0x40000000
701
702                                   0x1000000 0x0 0x0
703                                   0x1000000 0x0 0x0
704                                   0x0 0x100000>;
705                 };
706         };
707 };