2 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
3 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
5 * XPedite5330 3U CompactPCI module based on MPC8572E
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 model = "xes,xpedite5330";
15 compatible = "xes,xpedite5330", "xes,MPC8572";
18 form-factor = "3U CompactPCI";
19 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
38 * boolean properties (true if defined):
52 * boolean properties (true if defined):
60 * boolean properties (true if defined):
73 d-cache-line-size = <32>; // 32 bytes
74 i-cache-line-size = <32>; // 32 bytes
75 d-cache-size = <0x8000>; // L1, 32K
76 i-cache-size = <0x8000>; // L1, 32K
77 timebase-frequency = <0>;
79 clock-frequency = <0>;
80 next-level-cache = <&L2>;
86 d-cache-line-size = <32>; // 32 bytes
87 i-cache-line-size = <32>; // 32 bytes
88 d-cache-size = <0x8000>; // L1, 32K
89 i-cache-size = <0x8000>; // L1, 32K
90 timebase-frequency = <0>;
92 clock-frequency = <0>;
93 next-level-cache = <&L2>;
98 device_type = "memory";
99 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
103 #address-cells = <2>;
105 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
106 reg = <0 0xef005000 0 0x1000>;
108 interrupt-parent = <&mpic>;
109 /* Local bus region mappings */
110 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
111 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
112 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
113 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
116 compatible = "amd,s29gl01gp", "cfi-flash";
118 reg = <0 0 0x8000000>; /* 128MB */
119 #address-cells = <1>;
122 label = "Primary user space";
123 reg = <0x00000000 0x6f00000>; /* 111 MB */
126 label = "Primary kernel";
127 reg = <0x6f00000 0x1000000>; /* 16 MB */
130 label = "Primary DTB";
131 reg = <0x7f00000 0x40000>; /* 256 KB */
134 label = "Primary U-Boot environment";
135 reg = <0x7f40000 0x40000>; /* 256 KB */
138 label = "Primary U-Boot";
139 reg = <0x7f80000 0x80000>; /* 512 KB */
145 compatible = "amd,s29gl01gp", "cfi-flash";
147 //reg = <0xf0000000 0x08000000>; /* 128MB */
148 reg = <1 0 0x8000000>; /* 128MB */
149 #address-cells = <1>;
152 label = "Secondary user space";
153 reg = <0x00000000 0x6f00000>; /* 111 MB */
156 label = "Secondary kernel";
157 reg = <0x6f00000 0x1000000>; /* 16 MB */
160 label = "Secondary DTB";
161 reg = <0x7f00000 0x40000>; /* 256 KB */
164 label = "Secondary U-Boot environment";
165 reg = <0x7f40000 0x40000>; /* 256 KB */
168 label = "Secondary U-Boot";
169 reg = <0x7f80000 0x80000>; /* 512 KB */
175 #address-cells = <1>;
178 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
179 * Micron MT29F8G08DAA (2x 512 MB), or Micron
180 * MT29F16G08FAA (2x 1 GB), depending on the build
183 compatible = "fsl,mpc8572-fcm-nand",
186 /* U-Boot should fix this up if chip size > 1 GB */
188 label = "NAND Filesystem";
189 reg = <0 0x40000000>;
196 #address-cells = <1>;
199 compatible = "fsl,mpc8572-immr", "simple-bus";
200 ranges = <0x0 0 0xef000000 0x100000>;
201 bus-frequency = <0>; // Filled out by uboot.
204 compatible = "fsl,ecm-law";
210 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
211 reg = <0x1000 0x1000>;
213 interrupt-parent = <&mpic>;
216 memory-controller@2000 {
217 compatible = "fsl,mpc8572-memory-controller";
218 reg = <0x2000 0x1000>;
219 interrupt-parent = <&mpic>;
223 memory-controller@6000 {
224 compatible = "fsl,mpc8572-memory-controller";
225 reg = <0x6000 0x1000>;
226 interrupt-parent = <&mpic>;
230 L2: l2-cache-controller@20000 {
231 compatible = "fsl,mpc8572-l2-cache-controller";
232 reg = <0x20000 0x1000>;
233 cache-line-size = <32>; // 32 bytes
234 cache-size = <0x100000>; // L2, 1M
235 interrupt-parent = <&mpic>;
240 #address-cells = <1>;
243 compatible = "fsl-i2c";
244 reg = <0x3000 0x100>;
246 interrupt-parent = <&mpic>;
250 compatible = "dallas,ds1631", "dallas,ds1621";
255 compatible = "adi,adt7461";
260 compatible = "dallas,ds4510";
265 compatible = "atmel,at24c128b";
270 compatible = "stm,m41t00",
276 compatible = "plx,pex8518";
281 compatible = "nxp,pca9557";
289 compatible = "nxp,pca9557";
297 compatible = "nxp,pca9557";
305 compatible = "nxp,pca9557";
314 #address-cells = <1>;
317 compatible = "fsl-i2c";
318 reg = <0x3100 0x100>;
320 interrupt-parent = <&mpic>;
325 #address-cells = <1>;
327 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
329 ranges = <0x0 0xc100 0x200>;
332 compatible = "fsl,mpc8572-dma-channel",
333 "fsl,eloplus-dma-channel";
336 interrupt-parent = <&mpic>;
340 compatible = "fsl,mpc8572-dma-channel",
341 "fsl,eloplus-dma-channel";
344 interrupt-parent = <&mpic>;
348 compatible = "fsl,mpc8572-dma-channel",
349 "fsl,eloplus-dma-channel";
352 interrupt-parent = <&mpic>;
356 compatible = "fsl,mpc8572-dma-channel",
357 "fsl,eloplus-dma-channel";
360 interrupt-parent = <&mpic>;
366 #address-cells = <1>;
368 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
370 ranges = <0x0 0x21100 0x200>;
373 compatible = "fsl,mpc8572-dma-channel",
374 "fsl,eloplus-dma-channel";
377 interrupt-parent = <&mpic>;
381 compatible = "fsl,mpc8572-dma-channel",
382 "fsl,eloplus-dma-channel";
385 interrupt-parent = <&mpic>;
389 compatible = "fsl,mpc8572-dma-channel",
390 "fsl,eloplus-dma-channel";
393 interrupt-parent = <&mpic>;
397 compatible = "fsl,mpc8572-dma-channel",
398 "fsl,eloplus-dma-channel";
401 interrupt-parent = <&mpic>;
407 enet0: ethernet@24000 {
408 #address-cells = <1>;
411 device_type = "network";
413 compatible = "gianfar";
414 reg = <0x24000 0x1000>;
415 ranges = <0x0 0x24000 0x1000>;
416 local-mac-address = [ 00 00 00 00 00 00 ];
417 interrupts = <29 2 30 2 34 2>;
418 interrupt-parent = <&mpic>;
419 tbi-handle = <&tbi0>;
420 phy-handle = <&phy0>;
421 phy-connection-type = "sgmii";
424 #address-cells = <1>;
426 compatible = "fsl,gianfar-mdio";
429 phy0: ethernet-phy@1 {
430 interrupt-parent = <&mpic>;
434 phy1: ethernet-phy@2 {
435 interrupt-parent = <&mpic>;
441 device_type = "tbi-phy";
447 enet1: ethernet@25000 {
448 #address-cells = <1>;
451 device_type = "network";
453 compatible = "gianfar";
454 reg = <0x25000 0x1000>;
455 ranges = <0x0 0x25000 0x1000>;
456 local-mac-address = [ 00 00 00 00 00 00 ];
457 interrupts = <35 2 36 2 40 2>;
458 interrupt-parent = <&mpic>;
459 tbi-handle = <&tbi1>;
460 phy-handle = <&phy1>;
461 phy-connection-type = "sgmii";
464 #address-cells = <1>;
466 compatible = "fsl,gianfar-tbi";
471 device_type = "tbi-phy";
477 serial0: serial@4500 {
479 device_type = "serial";
480 compatible = "fsl,ns16550", "ns16550";
481 reg = <0x4500 0x100>;
482 clock-frequency = <0>;
484 interrupt-parent = <&mpic>;
488 serial1: serial@4600 {
490 device_type = "serial";
491 compatible = "fsl,ns16550", "ns16550";
492 reg = <0x4600 0x100>;
493 clock-frequency = <0>;
495 interrupt-parent = <&mpic>;
498 global-utilities@e0000 { //global utilities block
499 compatible = "fsl,mpc8572-guts";
500 reg = <0xe0000 0x1000>;
505 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
506 reg = <0x41600 0x80>;
507 msi-available-ranges = <0 0x100>;
517 interrupt-parent = <&mpic>;
521 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
522 "fsl,sec2.1", "fsl,sec2.0";
523 reg = <0x30000 0x10000>;
524 interrupts = <45 2 58 2>;
525 interrupt-parent = <&mpic>;
526 fsl,num-channels = <4>;
527 fsl,channel-fifo-len = <24>;
528 fsl,exec-units-mask = <0x9fe>;
529 fsl,descriptor-types-mask = <0x3ab0ebf>;
533 interrupt-controller;
534 #address-cells = <0>;
535 #interrupt-cells = <2>;
536 reg = <0x40000 0x40000>;
537 compatible = "chrp,open-pic";
538 device_type = "open-pic";
542 compatible = "fsl,mpc8572-gpio";
543 reg = <0xf000 0x1000>;
545 interrupt-parent = <&mpic>;
551 compatible = "gpio-leds";
555 gpios = <&gpio0 4 1>;
556 linux,default-trigger = "heartbeat";
561 gpios = <&gpio0 5 1>;
566 gpios = <&gpio0 6 1>;
571 gpios = <&gpio0 7 1>;
575 /* PME (pattern-matcher) */
577 compatible = "fsl,mpc8572-pme", "pme8572";
578 reg = <0x10000 0x5000>;
579 interrupts = <57 2 64 2 65 2 66 2 67 2>;
580 interrupt-parent = <&mpic>;
584 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
585 reg = <0x2f000 0x1000>;
587 interrupt-parent = <&mpic>;
591 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
592 reg = <0x15000 0x1000>;
594 interrupt-parent = <&mpic>;
598 /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
599 pci0: pcie@ef008000 {
600 compatible = "fsl,mpc8548-pcie";
602 #interrupt-cells = <1>;
604 #address-cells = <3>;
605 reg = <0 0xef008000 0 0x1000>;
607 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
608 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
609 clock-frequency = <33333333>;
610 interrupt-parent = <&mpic>;
612 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
614 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
615 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
616 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
617 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
620 reg = <0x0 0x0 0x0 0x0 0x0>;
622 #address-cells = <3>;
624 ranges = <0x02000000 0x0 0xe0000000
625 0x02000000 0x0 0xe0000000
634 /* PCI Express controller 2, PMC module via PEX8112 bridge */
635 pci1: pcie@ef009000 {
636 compatible = "fsl,mpc8548-pcie";
638 #interrupt-cells = <1>;
640 #address-cells = <3>;
641 reg = <0 0xef009000 0 0x1000>;
643 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
644 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
645 clock-frequency = <33333333>;
646 interrupt-parent = <&mpic>;
648 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
651 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
652 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
653 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
654 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
657 reg = <0x0 0x0 0x0 0x0 0x0>;
659 #address-cells = <3>;
661 ranges = <0x2000000 0x0 0xc0000000
662 0x2000000 0x0 0xc0000000
671 /* PCI Express controller 1, XMC P15 */
672 pci2: pcie@ef00a000 {
673 compatible = "fsl,mpc8548-pcie";
675 #interrupt-cells = <1>;
677 #address-cells = <3>;
678 reg = <0 0xef00a000 0 0x1000>;
680 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
681 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
682 clock-frequency = <33333333>;
683 interrupt-parent = <&mpic>;
685 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
688 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
689 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
690 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
691 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
694 reg = <0x0 0x0 0x0 0x0 0x0>;
696 #address-cells = <3>;
698 ranges = <0x2000000 0x0 0x80000000
699 0x2000000 0x0 0x80000000