arch/powerpc/include/asm/opal.h

   1 /*
   2  * PowerNV OPAL definitions.
   3  *
   4  * Copyright 2011 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef __OPAL_H
  13 #define __OPAL_H
  14
  15 /****** Takeover interface ********/
  16
  17 /* PAPR H-Call used to querty the HAL existence and/or instanciate
  18  * it from within pHyp (tech preview only).
  19  *
  20  * This is exclusively used in prom_init.c
  21  */
  22
  23 #ifndef __ASSEMBLY__
  24
  25 struct opal_takeover_args {
  26         u64     k_image;                /* r4 */
  27         u64     k_size;                 /* r5 */
  28         u64     k_entry;                /* r6 */
  29         u64     k_entry2;               /* r7 */
  30         u64     hal_addr;               /* r8 */
  31         u64     rd_image;               /* r9 */
  32         u64     rd_size;                /* r10 */
  33         u64     rd_loc;                 /* r11 */
  34 };
  35
  36 extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
  37
  38 extern long opal_do_takeover(struct opal_takeover_args *args);
  39
  40 struct rtas_args;
  41 extern int opal_enter_rtas(struct rtas_args *args,
  42                            unsigned long data,
  43                            unsigned long entry);
  44
  45 #endif /* __ASSEMBLY__ */
  46
  47 /****** OPAL APIs ******/
  48
  49 /* Return codes */
  50 #define OPAL_SUCCESS            0
  51 #define OPAL_PARAMETER          -1
  52 #define OPAL_BUSY               -2
  53 #define OPAL_PARTIAL            -3
  54 #define OPAL_CONSTRAINED        -4
  55 #define OPAL_CLOSED             -5
  56 #define OPAL_HARDWARE           -6
  57 #define OPAL_UNSUPPORTED        -7
  58 #define OPAL_PERMISSION         -8
  59 #define OPAL_NO_MEM             -9
  60 #define OPAL_RESOURCE           -10
  61 #define OPAL_INTERNAL_ERROR     -11
  62 #define OPAL_BUSY_EVENT         -12
  63 #define OPAL_HARDWARE_FROZEN    -13
  64
  65 /* API Tokens (in r0) */
  66 #define OPAL_CONSOLE_WRITE                      1
  67 #define OPAL_CONSOLE_READ                       2
  68 #define OPAL_RTC_READ                           3
  69 #define OPAL_RTC_WRITE                          4
  70 #define OPAL_CEC_POWER_DOWN                     5
  71 #define OPAL_CEC_REBOOT                         6
  72 #define OPAL_READ_NVRAM                         7
  73 #define OPAL_WRITE_NVRAM                        8
  74 #define OPAL_HANDLE_INTERRUPT                   9
  75 #define OPAL_POLL_EVENTS                        10
  76 #define OPAL_PCI_SET_HUB_TCE_MEMORY             11
  77 #define OPAL_PCI_SET_PHB_TCE_MEMORY             12
  78 #define OPAL_PCI_CONFIG_READ_BYTE               13
  79 #define OPAL_PCI_CONFIG_READ_HALF_WORD          14
  80 #define OPAL_PCI_CONFIG_READ_WORD               15
  81 #define OPAL_PCI_CONFIG_WRITE_BYTE              16
  82 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD         17
  83 #define OPAL_PCI_CONFIG_WRITE_WORD              18
  84 #define OPAL_SET_XIVE                           19
  85 #define OPAL_GET_XIVE                           20
  86 #define OPAL_GET_COMPLETION_TOKEN_STATUS        21 /* obsolete */
  87 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER    22
  88 #define OPAL_PCI_EEH_FREEZE_STATUS              23
  89 #define OPAL_PCI_SHPC                           24
  90 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE         25
  91 #define OPAL_PCI_EEH_FREEZE_CLEAR               26
  92 #define OPAL_PCI_PHB_MMIO_ENABLE                27
  93 #define OPAL_PCI_SET_PHB_MEM_WINDOW             28
  94 #define OPAL_PCI_MAP_PE_MMIO_WINDOW             29
  95 #define OPAL_PCI_SET_PHB_TABLE_MEMORY           30
  96 #define OPAL_PCI_SET_PE                         31
  97 #define OPAL_PCI_SET_PELTV                      32
  98 #define OPAL_PCI_SET_MVE                        33
  99 #define OPAL_PCI_SET_MVE_ENABLE                 34
 100 #define OPAL_PCI_GET_XIVE_REISSUE               35
 101 #define OPAL_PCI_SET_XIVE_REISSUE               36
 102 #define OPAL_PCI_SET_XIVE_PE                    37
 103 #define OPAL_GET_XIVE_SOURCE                    38
 104 #define OPAL_GET_MSI_32                         39
 105 #define OPAL_GET_MSI_64                         40
 106 #define OPAL_START_CPU                          41
 107 #define OPAL_QUERY_CPU_STATUS                   42
 108 #define OPAL_WRITE_OPPANEL                      43
 109 #define OPAL_PCI_MAP_PE_DMA_WINDOW              44
 110 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL         45
 111 #define OPAL_PCI_RESET                          49
 112 #define OPAL_PCI_GET_HUB_DIAG_DATA              50
 113 #define OPAL_PCI_GET_PHB_DIAG_DATA              51
 114 #define OPAL_PCI_FENCE_PHB                      52
 115 #define OPAL_PCI_REINIT                         53
 116 #define OPAL_PCI_MASK_PE_ERROR                  54
 117 #define OPAL_SET_SLOT_LED_STATUS                55
 118 #define OPAL_GET_EPOW_STATUS                    56
 119 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
 120 #define OPAL_PCI_MSI_EOI                        63
 121
 122 #ifndef __ASSEMBLY__
 123
 124 /* Other enums */
 125 enum OpalVendorApiTokens {
 126         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 127 };
 128 enum OpalFreezeState {
 129         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
 130         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
 131         OPAL_EEH_STOPPED_DMA_FREEZE = 2,
 132         OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
 133         OPAL_EEH_STOPPED_RESET = 4,
 134         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
 135         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 136 };
 137 enum OpalEehFreezeActionToken {
 138         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
 139         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
 140         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
 141 };
 142 enum OpalPciStatusToken {
 143         OPAL_EEH_PHB_NO_ERROR = 0,
 144         OPAL_EEH_PHB_FATAL = 1,
 145         OPAL_EEH_PHB_RECOVERABLE = 2,
 146         OPAL_EEH_PHB_BUS_ERROR = 3,
 147         OPAL_EEH_PCI_NO_DEVSEL = 4,
 148         OPAL_EEH_PCI_TA = 5,
 149         OPAL_EEH_PCIEX_UR = 6,
 150         OPAL_EEH_PCIEX_CA = 7,
 151         OPAL_EEH_PCI_MMIO_ERROR = 8,
 152         OPAL_EEH_PCI_DMA_ERROR = 9
 153 };
 154 enum OpalShpcAction {
 155         OPAL_SHPC_GET_LINK_STATE = 0,
 156         OPAL_SHPC_GET_SLOT_STATE = 1
 157 };
 158 enum OpalShpcLinkState {
 159         OPAL_SHPC_LINK_DOWN = 0,
 160         OPAL_SHPC_LINK_UP = 1
 161 };
 162 enum OpalMmioWindowType {
 163         OPAL_M32_WINDOW_TYPE = 1,
 164         OPAL_M64_WINDOW_TYPE = 2,
 165         OPAL_IO_WINDOW_TYPE = 3
 166 };
 167 enum OpalShpcSlotState {
 168         OPAL_SHPC_DEV_NOT_PRESENT = 0,
 169         OPAL_SHPC_DEV_PRESENT = 1
 170 };
 171 enum OpalExceptionHandler {
 172         OPAL_MACHINE_CHECK_HANDLER = 1,
 173         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
 174         OPAL_SOFTPATCH_HANDLER = 3
 175 };
 176 enum OpalPendingState {
 177         OPAL_EVENT_OPAL_INTERNAL = 0x1,
 178         OPAL_EVENT_NVRAM = 0x2,
 179         OPAL_EVENT_RTC = 0x4,
 180         OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
 181         OPAL_EVENT_CONSOLE_INPUT = 0x10,
 182         OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
 183         OPAL_EVENT_ERROR_LOG = 0x40,
 184         OPAL_EVENT_EPOW = 0x80,
 185         OPAL_EVENT_LED_STATUS = 0x100
 186 };
 187
 188 /* Machine check related definitions */
 189 enum OpalMCE_Version {
 190         OpalMCE_V1 = 1,
 191 };
 192
 193 enum OpalMCE_Severity {
 194         OpalMCE_SEV_NO_ERROR = 0,
 195         OpalMCE_SEV_WARNING = 1,
 196         OpalMCE_SEV_ERROR_SYNC = 2,
 197         OpalMCE_SEV_FATAL = 3,
 198 };
 199
 200 enum OpalMCE_Disposition {
 201         OpalMCE_DISPOSITION_RECOVERED = 0,
 202         OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
 203 };
 204
 205 enum OpalMCE_Initiator {
 206         OpalMCE_INITIATOR_UNKNOWN = 0,
 207         OpalMCE_INITIATOR_CPU = 1,
 208 };
 209
 210 enum OpalMCE_ErrorType {
 211         OpalMCE_ERROR_TYPE_UNKNOWN = 0,
 212         OpalMCE_ERROR_TYPE_UE = 1,
 213         OpalMCE_ERROR_TYPE_SLB = 2,
 214         OpalMCE_ERROR_TYPE_ERAT = 3,
 215         OpalMCE_ERROR_TYPE_TLB = 4,
 216 };
 217
 218 enum OpalMCE_UeErrorType {
 219         OpalMCE_UE_ERROR_INDETERMINATE = 0,
 220         OpalMCE_UE_ERROR_IFETCH = 1,
 221         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
 222         OpalMCE_UE_ERROR_LOAD_STORE = 3,
 223         OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
 224 };
 225
 226 enum OpalMCE_SlbErrorType {
 227         OpalMCE_SLB_ERROR_INDETERMINATE = 0,
 228         OpalMCE_SLB_ERROR_PARITY = 1,
 229         OpalMCE_SLB_ERROR_MULTIHIT = 2,
 230 };
 231
 232 enum OpalMCE_EratErrorType {
 233         OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
 234         OpalMCE_ERAT_ERROR_PARITY = 1,
 235         OpalMCE_ERAT_ERROR_MULTIHIT = 2,
 236 };
 237
 238 enum OpalMCE_TlbErrorType {
 239         OpalMCE_TLB_ERROR_INDETERMINATE = 0,
 240         OpalMCE_TLB_ERROR_PARITY = 1,
 241         OpalMCE_TLB_ERROR_MULTIHIT = 2,
 242 };
 243
 244 enum OpalThreadStatus {
 245         OPAL_THREAD_INACTIVE = 0x0,
 246         OPAL_THREAD_STARTED = 0x1,
 247         OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
 248 };
 249
 250 enum OpalPciBusCompare {
 251         OpalPciBusAny   = 0,    /* Any bus number match */
 252         OpalPciBus3Bits = 2,    /* Match top 3 bits of bus number */
 253         OpalPciBus4Bits = 3,    /* Match top 4 bits of bus number */
 254         OpalPciBus5Bits = 4,    /* Match top 5 bits of bus number */
 255         OpalPciBus6Bits = 5,    /* Match top 6 bits of bus number */
 256         OpalPciBus7Bits = 6,    /* Match top 7 bits of bus number */
 257         OpalPciBusAll   = 7,    /* Match bus number exactly */
 258 };
 259
 260 enum OpalDeviceCompare {
 261         OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
 262         OPAL_COMPARE_RID_DEVICE_NUMBER = 1
 263 };
 264
 265 enum OpalFuncCompare {
 266         OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
 267         OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
 268 };
 269
 270 enum OpalPeAction {
 271         OPAL_UNMAP_PE = 0,
 272         OPAL_MAP_PE = 1
 273 };
 274
 275 enum OpalPeltvAction {
 276         OPAL_REMOVE_PE_FROM_DOMAIN = 0,
 277         OPAL_ADD_PE_TO_DOMAIN = 1
 278 };
 279
 280 enum OpalMveEnableAction {
 281         OPAL_DISABLE_MVE = 0,
 282         OPAL_ENABLE_MVE = 1
 283 };
 284
 285 enum OpalPciResetAndReinitScope {
 286         OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
 287         OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
 288         OPAL_PCI_IODA_TABLE_RESET = 6,
 289 };
 290
 291 enum OpalPciResetState {
 292         OPAL_DEASSERT_RESET = 0,
 293         OPAL_ASSERT_RESET = 1
 294 };
 295
 296 enum OpalPciMaskAction {
 297         OPAL_UNMASK_ERROR_TYPE = 0,
 298         OPAL_MASK_ERROR_TYPE = 1
 299 };
 300
 301 enum OpalSlotLedType {
 302         OPAL_SLOT_LED_ID_TYPE = 0,
 303         OPAL_SLOT_LED_FAULT_TYPE = 1
 304 };
 305
 306 enum OpalLedAction {
 307         OPAL_TURN_OFF_LED = 0,
 308         OPAL_TURN_ON_LED = 1,
 309         OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
 310 };
 311
 312 enum OpalEpowStatus {
 313         OPAL_EPOW_NONE = 0,
 314         OPAL_EPOW_UPS = 1,
 315         OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
 316         OPAL_EPOW_OVER_INTERNAL_TEMP = 3
 317 };
 318
 319 struct opal_machine_check_event {
 320         enum OpalMCE_Version    version:8;      /* 0x00 */
 321         uint8_t                 in_use;         /* 0x01 */
 322         enum OpalMCE_Severity   severity:8;     /* 0x02 */
 323         enum OpalMCE_Initiator  initiator:8;    /* 0x03 */
 324         enum OpalMCE_ErrorType  error_type:8;   /* 0x04 */
 325         enum OpalMCE_Disposition disposition:8; /* 0x05 */
 326         uint8_t                 reserved_1[2];  /* 0x06 */
 327         uint64_t                gpr3;           /* 0x08 */
 328         uint64_t                srr0;           /* 0x10 */
 329         uint64_t                srr1;           /* 0x18 */
 330         union {                                 /* 0x20 */
 331                 struct {
 332                         enum OpalMCE_UeErrorType ue_error_type:8;
 333                         uint8_t         effective_address_provided;
 334                         uint8_t         physical_address_provided;
 335                         uint8_t         reserved_1[5];
 336                         uint64_t        effective_address;
 337                         uint64_t        physical_address;
 338                         uint8_t         reserved_2[8];
 339                 } ue_error;
 340
 341                 struct {
 342                         enum OpalMCE_SlbErrorType slb_error_type:8;
 343                         uint8_t         effective_address_provided;
 344                         uint8_t         reserved_1[6];
 345                         uint64_t        effective_address;
 346                         uint8_t         reserved_2[16];
 347                 } slb_error;
 348
 349                 struct {
 350                         enum OpalMCE_EratErrorType erat_error_type:8;
 351                         uint8_t         effective_address_provided;
 352                         uint8_t         reserved_1[6];
 353                         uint64_t        effective_address;
 354                         uint8_t         reserved_2[16];
 355                 } erat_error;
 356
 357                 struct {
 358                         enum OpalMCE_TlbErrorType tlb_error_type:8;
 359                         uint8_t         effective_address_provided;
 360                         uint8_t         reserved_1[6];
 361                         uint64_t        effective_address;
 362                         uint8_t         reserved_2[16];
 363                 } tlb_error;
 364         } u;
 365 };
 366
 367 /**
 368  * This structure defines the overlay which will be used to store PHB error
 369  * data upon request.
 370  */
 371 enum {
 372         OPAL_P7IOC_NUM_PEST_REGS = 128,
 373 };
 374
 375 struct OpalIoP7IOCPhbErrorData {
 376         uint32_t brdgCtl;
 377
 378         // P7IOC utl regs
 379         uint32_t portStatusReg;
 380         uint32_t rootCmplxStatus;
 381         uint32_t busAgentStatus;
 382
 383         // P7IOC cfg regs
 384         uint32_t deviceStatus;
 385         uint32_t slotStatus;
 386         uint32_t linkStatus;
 387         uint32_t devCmdStatus;
 388         uint32_t devSecStatus;
 389
 390         // cfg AER regs
 391         uint32_t rootErrorStatus;
 392         uint32_t uncorrErrorStatus;
 393         uint32_t corrErrorStatus;
 394         uint32_t tlpHdr1;
 395         uint32_t tlpHdr2;
 396         uint32_t tlpHdr3;
 397         uint32_t tlpHdr4;
 398         uint32_t sourceId;
 399
 400         uint32_t rsv3;
 401
 402         // Record data about the call to allocate a buffer.
 403         uint64_t errorClass;
 404         uint64_t correlator;
 405
 406         //P7IOC MMIO Error Regs
 407         uint64_t p7iocPlssr;                // n120
 408         uint64_t p7iocCsr;                  // n110
 409         uint64_t lemFir;                    // nC00
 410         uint64_t lemErrorMask;              // nC18
 411         uint64_t lemWOF;                    // nC40
 412         uint64_t phbErrorStatus;            // nC80
 413         uint64_t phbFirstErrorStatus;       // nC88
 414         uint64_t phbErrorLog0;              // nCC0
 415         uint64_t phbErrorLog1;              // nCC8
 416         uint64_t mmioErrorStatus;           // nD00
 417         uint64_t mmioFirstErrorStatus;      // nD08
 418         uint64_t mmioErrorLog0;             // nD40
 419         uint64_t mmioErrorLog1;             // nD48
 420         uint64_t dma0ErrorStatus;           // nD80
 421         uint64_t dma0FirstErrorStatus;      // nD88
 422         uint64_t dma0ErrorLog0;             // nDC0
 423         uint64_t dma0ErrorLog1;             // nDC8
 424         uint64_t dma1ErrorStatus;           // nE00
 425         uint64_t dma1FirstErrorStatus;      // nE08
 426         uint64_t dma1ErrorLog0;             // nE40
 427         uint64_t dma1ErrorLog1;             // nE48
 428         uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
 429         uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
 430 };
 431
 432 typedef struct oppanel_line {
 433         const char *    line;
 434         uint64_t        line_len;
 435 } oppanel_line_t;
 436
 437 /* API functions */
 438 int64_t opal_console_write(int64_t term_number, int64_t *length,
 439                            const uint8_t *buffer);
 440 int64_t opal_console_read(int64_t term_number, int64_t *length,
 441                           uint8_t *buffer);
 442 int64_t opal_console_write_buffer_space(int64_t term_number,
 443                                         int64_t *length);
 444 int64_t opal_rtc_read(uint32_t *year_month_day,
 445                       uint64_t *hour_minute_second_millisecond);
 446 int64_t opal_rtc_write(uint32_t year_month_day,
 447                        uint64_t hour_minute_second_millisecond);
 448 int64_t opal_cec_power_down(uint64_t request);
 449 int64_t opal_cec_reboot(void);
 450 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 451 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
 452 int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
 453 int64_t opal_poll_events(uint64_t *outstanding_event_mask);
 454 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
 455                                     uint64_t tce_mem_size);
 456 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
 457                                     uint64_t tce_mem_size);
 458 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
 459                                   uint64_t offset, uint8_t *data);
 460 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 461                                        uint64_t offset, uint16_t *data);
 462 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
 463                                   uint64_t offset, uint32_t *data);
 464 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
 465                                    uint64_t offset, uint8_t data);
 466 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
 467                                         uint64_t offset, uint16_t data);
 468 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
 469                                    uint64_t offset, uint32_t data);
 470 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
 471 int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
 472 int64_t opal_register_exception_handler(uint64_t opal_exception,
 473                                         uint64_t handler_address,
 474                                         uint64_t glue_cache_line);
 475 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
 476                                    uint8_t *freeze_state,
 477                                    uint16_t *pci_error_type,
 478                                    uint64_t *phb_status);
 479 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
 480                                   uint64_t eeh_action_token);
 481 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
 482
 483
 484
 485 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
 486                                  uint16_t window_num, uint16_t enable);
 487 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
 488                                     uint16_t window_num,
 489                                     uint64_t starting_real_address,
 490                                     uint64_t starting_pci_address,
 491                                     uint16_t segment_size);
 492 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
 493                                     uint16_t window_type, uint16_t window_num,
 494                                     uint16_t segment_num);
 495 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
 496                                       uint64_t ivt_addr, uint64_t ivt_len,
 497                                       uint64_t reject_array_addr,
 498                                       uint64_t peltv_addr);
 499 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
 500                         uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
 501                         uint8_t pe_action);
 502 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
 503                            uint8_t state);
 504 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
 505 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
 506                                 uint32_t state);
 507 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 508                                   uint8_t *p_bit, uint8_t *q_bit);
 509 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
 510                                   uint8_t p_bit, uint8_t q_bit);
 511 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 512 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
 513                              uint32_t xive_num);
 514 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
 515                              int32_t *interrupt_source_number);
 516 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
 517                         uint8_t msi_range, uint32_t *msi_address,
 518                         uint32_t *message_data);
 519 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
 520                         uint32_t xive_num, uint8_t msi_range,
 521                         uint64_t *msi_address, uint32_t *message_data);
 522 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
 523 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
 524 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
 525 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
 526                                    uint16_t tce_levels, uint64_t tce_table_addr,
 527                                    uint64_t tce_table_size, uint64_t tce_page_size);
 528 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
 529                                         uint16_t dma_window_number, uint64_t pci_start_addr,
 530                                         uint64_t pci_mem_size);
 531 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 532
 533 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
 534 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
 535 int64_t opal_pci_fence_phb(uint64_t phb_id);
 536 int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
 537 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 538 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 539 int64_t opal_get_epow_status(uint64_t *status);
 540 int64_t opal_set_system_attention_led(uint8_t led_action);
 541
 542 /* Internal functions */
 543 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
 544
 545 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 546 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 547
 548 extern void hvc_opal_init_early(void);
 549
 550 /* Internal functions */
 551 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
 552                                    int depth, void *data);
 553
 554 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 555 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 556
 557 extern void hvc_opal_init_early(void);
 558
 559 struct rtc_time;
 560 extern int opal_set_rtc_time(struct rtc_time *tm);
 561 extern void opal_get_rtc_time(struct rtc_time *tm);
 562 extern unsigned long opal_get_boot_time(void);
 563 extern void opal_nvram_init(void);
 564
 565 extern int opal_machine_check(struct pt_regs *regs);
 566
 567 extern void opal_shutdown(void);
 568
 569 #endif /* __ASSEMBLY__ */
 570
 571 #endif /* __OPAL_H */