2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
4 * Author: John Rigby <jrigby@freescale.com>
9 * This is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/kernel.h>
17 #include <linux/irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/fsl-diu-fb.h>
20 #include <linux/bootmem.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/cacheflush.h>
24 #include <asm/machdep.h>
28 #include <asm/mpc5121.h>
29 #include <asm/mpc52xx_psc.h>
33 static struct mpc512x_reset_module __iomem *reset_module_base;
35 static void __init mpc512x_restart_init(void)
37 struct device_node *np;
39 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
43 reset_module_base = of_iomap(np, 0);
47 void mpc512x_restart(char *cmd)
49 if (reset_module_base) {
50 /* Enable software reset "RSTE" */
51 out_be32(&reset_module_base->rpr, 0x52535445);
52 /* Set software hard reset */
53 out_be32(&reset_module_base->rcr, 0x2);
55 pr_err("Restart module not mapped.\n");
61 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
63 struct fsl_diu_shared_fb {
64 u8 gamma[0x300]; /* 32-bit aligned! */
65 struct diu_ad ad0; /* 32-bit aligned! */
71 void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port)
75 #define DIU_DIV_MASK 0x000000ff
76 void mpc512x_set_pixel_clock(unsigned int pixclock)
78 unsigned long bestval, bestfreq, speed, busfreq;
79 unsigned long minpixclock, maxpixclock, pixval;
80 struct mpc512x_ccm __iomem *ccm;
81 struct device_node *np;
86 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
88 pr_err("Can't find clock control module.\n");
92 ccm = of_iomap(np, 0);
95 pr_err("Can't map clock control module reg.\n");
99 np = of_find_node_by_type(NULL, "cpu");
101 const unsigned int *prop =
102 of_get_property(np, "bus-frequency", NULL);
108 pr_err("Can't get bus-frequency property\n");
112 pr_err("Can't find 'cpu' node.\n");
116 /* Pixel Clock configuration */
117 pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
118 speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
120 /* Calculate the pixel clock with the smallest error */
121 /* calculate the following in steps to avoid overflow */
122 pr_debug("DIU pixclock in ps - %d\n", pixclock);
123 temp = (1000000000 / pixclock) * 1000;
125 pr_debug("DIU pixclock freq - %u\n", pixclock);
127 temp = temp / 20; /* pixclock * 0.05 */
128 pr_debug("deviation = %d\n", temp);
129 minpixclock = pixclock - temp;
130 maxpixclock = pixclock + temp;
131 pr_debug("DIU minpixclock - %lu\n", minpixclock);
132 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
133 pixval = speed/pixclock;
134 pr_debug("DIU pixval = %lu\n", pixval);
138 pr_debug("DIU bestval = %lu\n", bestval);
141 for (i = -1; i <= 1; i++) {
142 temp = speed / (pixval+i);
143 pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
145 if ((temp < minpixclock) || (temp > maxpixclock))
146 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
147 minpixclock, maxpixclock);
148 else if (abs(temp - pixclock) < err) {
149 pr_debug("Entered the else if block %d\n", i);
150 err = abs(temp - pixclock);
151 bestval = pixval + i;
156 pr_debug("DIU chose = %lx\n", bestval);
157 pr_debug("DIU error = %ld\n NomPixClk ", err);
158 pr_debug("DIU: Best Freq = %lx\n", bestfreq);
159 /* Modify DIU_DIV in CCM SCFR1 */
160 temp = in_be32(&ccm->scfr1);
161 pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
162 temp &= ~DIU_DIV_MASK;
163 temp |= (bestval & DIU_DIV_MASK);
164 out_be32(&ccm->scfr1, temp);
165 pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
169 enum fsl_diu_monitor_port
170 mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port)
172 return FSL_DIU_PORT_DVI;
175 static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
177 static inline void mpc512x_free_bootmem(struct page *page)
179 __ClearPageReserved(page);
180 BUG_ON(PageTail(page));
181 BUG_ON(atomic_read(&page->_count) > 1);
182 atomic_set(&page->_count, 1);
187 void mpc512x_release_bootmem(void)
189 unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK;
190 unsigned long size = diu_shared_fb.fb_len;
191 unsigned long start, end;
193 if (diu_shared_fb.in_use) {
194 start = PFN_UP(addr);
195 end = PFN_DOWN(addr + size);
197 for (; start < end; start++)
198 mpc512x_free_bootmem(pfn_to_page(start));
200 diu_shared_fb.in_use = false;
202 diu_ops.release_bootmem = NULL;
206 * Check if DIU was pre-initialized. If so, perform steps
207 * needed to continue displaying through the whole boot process.
208 * Move area descriptor and gamma table elsewhere, they are
209 * destroyed by bootmem allocator otherwise. The frame buffer
210 * address range will be reserved in setup_arch() after bootmem
213 void __init mpc512x_init_diu(void)
215 struct device_node *np;
216 struct diu __iomem *diu_reg;
219 unsigned long mode, pix_fmt, res, bpp;
222 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
224 pr_err("No DIU node\n");
228 diu_reg = of_iomap(np, 0);
231 pr_err("Can't map DIU\n");
235 mode = in_be32(&diu_reg->diu_mode);
236 if (mode == MFB_MODE0) {
237 pr_info("%s: DIU OFF\n", __func__);
241 desc = in_be32(&diu_reg->desc[0]);
242 vaddr = ioremap(desc, sizeof(struct diu_ad));
244 pr_err("Can't map DIU area desc.\n");
247 memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad));
248 /* flush fb area descriptor */
249 dst = (unsigned long)&diu_shared_fb.ad0;
250 flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1);
252 res = in_be32(&diu_reg->disp_size);
253 pix_fmt = in_le32(vaddr);
254 bpp = ((pix_fmt >> 16) & 0x3) + 1;
255 diu_shared_fb.fb_phys = in_le32(vaddr + 4);
256 diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp;
257 diu_shared_fb.in_use = true;
260 desc = in_be32(&diu_reg->gamma);
261 vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma));
263 pr_err("Can't map DIU area desc.\n");
264 diu_shared_fb.in_use = false;
267 memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma));
268 /* flush gamma table */
269 dst = (unsigned long)&diu_shared_fb.gamma;
270 flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1);
273 out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma));
274 out_be32(&diu_reg->desc[1], 0);
275 out_be32(&diu_reg->desc[2], 0);
276 out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0));
282 void __init mpc512x_setup_diu(void)
287 * We do not allocate and configure new area for bitmap buffer
288 * because it would requere copying bitmap data (splash image)
289 * and so negatively affect boot time. Instead we reserve the
290 * already configured frame buffer area so that it won't be
291 * destroyed. The starting address of the area to reserve and
292 * also it's length is passed to reserve_bootmem(). It will be
293 * freed later on first open of fbdev, when splash image is not
296 if (diu_shared_fb.in_use) {
297 ret = reserve_bootmem(diu_shared_fb.fb_phys,
298 diu_shared_fb.fb_len,
301 pr_err("%s: reserve bootmem failed\n", __func__);
302 diu_shared_fb.in_use = false;
306 diu_ops.set_monitor_port = mpc512x_set_monitor_port;
307 diu_ops.set_pixel_clock = mpc512x_set_pixel_clock;
308 diu_ops.valid_monitor_port = mpc512x_valid_monitor_port;
309 diu_ops.release_bootmem = mpc512x_release_bootmem;
314 void __init mpc512x_init_IRQ(void)
316 struct device_node *np;
318 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ipic");
326 * Initialize the default interrupt mapping priorities,
327 * in case the boot rom changed something on us.
329 ipic_set_default_priority();
333 * Nodes to do bus probe on, soc and localbus
335 static struct of_device_id __initdata of_bus_ids[] = {
336 { .compatible = "fsl,mpc5121-immr", },
337 { .compatible = "fsl,mpc5121-localbus", },
341 void __init mpc512x_declare_of_platform_devices(void)
343 struct device_node *np;
345 if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
346 printk(KERN_ERR __FILE__ ": "
347 "Error while probing of_platform bus\n");
349 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-nfc");
351 of_platform_device_create(np, NULL, NULL);
356 #define DEFAULT_FIFO_SIZE 16
358 static unsigned int __init get_fifo_size(struct device_node *np,
361 const unsigned int *fp;
363 fp = of_get_property(np, prop_name, NULL);
367 pr_warning("no %s property in %s node, defaulting to %d\n",
368 prop_name, np->full_name, DEFAULT_FIFO_SIZE);
370 return DEFAULT_FIFO_SIZE;
373 #define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \
374 ((u32)(_base) + sizeof(struct mpc52xx_psc)))
376 /* Init PSC FIFO space for TX and RX slices */
377 void __init mpc512x_psc_fifo_init(void)
379 struct device_node *np;
381 unsigned int tx_fifo_size;
382 unsigned int rx_fifo_size;
383 int fifobase = 0; /* current fifo address in 32 bit words */
385 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
386 tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size");
387 rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size");
389 /* size in register is in 4 byte units */
397 psc = of_iomap(np, 0);
399 pr_err("%s: Can't map %s device\n",
400 __func__, np->full_name);
404 /* FIFO space is 4KiB, check if requested size is available */
405 if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) {
406 pr_err("%s: no fifo space available for %s\n",
407 __func__, np->full_name);
410 * chances are that another device requests less
411 * fifo space, so we continue.
416 /* set tx and rx fifo size registers */
417 out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size);
418 fifobase += tx_fifo_size;
419 out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size);
420 fifobase += rx_fifo_size;
422 /* reset and enable the slices */
423 out_be32(&FIFOC(psc)->txcmd, 0x80);
424 out_be32(&FIFOC(psc)->txcmd, 0x01);
425 out_be32(&FIFOC(psc)->rxcmd, 0x80);
426 out_be32(&FIFOC(psc)->rxcmd, 0x01);
432 void __init mpc512x_init(void)
434 mpc512x_declare_of_platform_devices();
436 mpc512x_restart_init();
437 mpc512x_psc_fifo_init();