2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/init.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
31 #include <linux/memblock.h>
32 #include <linux/spinlock.h>
33 #include <linux/sched.h> /* for show_stack */
34 #include <linux/string.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/crash_dump.h>
38 #include <linux/memory.h>
43 #include <asm/iommu.h>
44 #include <asm/pci-bridge.h>
45 #include <asm/machdep.h>
46 #include <asm/firmware.h>
48 #include <asm/ppc-pci.h>
50 #include <asm/mmzone.h>
52 #include "plpar_wrappers.h"
55 static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
56 u64 *startp, u64 *endp)
58 u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
59 unsigned long start, end, inc;
63 inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
65 /* If this is non-zero, change the format. We shift the
66 * address and or in the magic from the device tree. */
71 start |= tbl->it_busno;
75 end |= inc - 1; /* round up end to be different than start */
77 mb(); /* Make sure TCEs in memory are written */
78 while (start <= end) {
79 out_be64(invalidate, start);
84 static int tce_build_pSeries(struct iommu_table *tbl, long index,
85 long npages, unsigned long uaddr,
86 enum dma_data_direction direction,
87 struct dma_attrs *attrs)
93 proto_tce = TCE_PCI_READ; // Read allowed
95 if (direction != DMA_TO_DEVICE)
96 proto_tce |= TCE_PCI_WRITE;
98 tces = tcep = ((u64 *)tbl->it_base) + index;
101 /* can't move this out since we might cross MEMBLOCK boundary */
102 rpn = __pa(uaddr) >> TCE_SHIFT;
103 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
105 uaddr += TCE_PAGE_SIZE;
109 if (tbl->it_type & TCE_PCI_SWINV_CREATE)
110 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
115 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
119 tces = tcep = ((u64 *)tbl->it_base) + index;
124 if (tbl->it_type & TCE_PCI_SWINV_FREE)
125 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
128 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
132 tcep = ((u64 *)tbl->it_base) + index;
137 static void tce_free_pSeriesLP(struct iommu_table*, long, long);
138 static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
140 static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
141 long npages, unsigned long uaddr,
142 enum dma_data_direction direction,
143 struct dma_attrs *attrs)
149 long tcenum_start = tcenum, npages_start = npages;
151 rpn = __pa(uaddr) >> TCE_SHIFT;
152 proto_tce = TCE_PCI_READ;
153 if (direction != DMA_TO_DEVICE)
154 proto_tce |= TCE_PCI_WRITE;
157 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
158 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
160 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
162 tce_free_pSeriesLP(tbl, tcenum_start,
163 (npages_start - (npages + 1)));
167 if (rc && printk_ratelimit()) {
168 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
169 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
170 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
171 printk("\ttce val = 0x%llx\n", tce );
172 show_stack(current, (unsigned long *)__get_SP());
181 static DEFINE_PER_CPU(u64 *, tce_page);
183 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
184 long npages, unsigned long uaddr,
185 enum dma_data_direction direction,
186 struct dma_attrs *attrs)
193 long tcenum_start = tcenum, npages_start = npages;
198 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
202 local_irq_save(flags); /* to protect tcep and the page behind it */
204 tcep = __get_cpu_var(tce_page);
206 /* This is safe to do since interrupts are off when we're called
207 * from iommu_alloc{,_sg}()
210 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
211 /* If allocation fails, fall back to the loop implementation */
213 local_irq_restore(flags);
214 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
217 __get_cpu_var(tce_page) = tcep;
220 rpn = __pa(uaddr) >> TCE_SHIFT;
221 proto_tce = TCE_PCI_READ;
222 if (direction != DMA_TO_DEVICE)
223 proto_tce |= TCE_PCI_WRITE;
225 /* We can map max one pageful of TCEs at a time */
228 * Set up the page with TCE data, looping through and setting
231 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
233 for (l = 0; l < limit; l++) {
234 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
238 rc = plpar_tce_put_indirect((u64)tbl->it_index,
245 } while (npages > 0 && !rc);
247 local_irq_restore(flags);
249 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
251 tce_freemulti_pSeriesLP(tbl, tcenum_start,
252 (npages_start - (npages + limit)));
256 if (rc && printk_ratelimit()) {
257 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
258 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
259 printk("\tnpages = 0x%llx\n", (u64)npages);
260 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
261 show_stack(current, (unsigned long *)__get_SP());
266 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
271 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
273 if (rc && printk_ratelimit()) {
274 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
275 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
276 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
277 show_stack(current, (unsigned long *)__get_SP());
285 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
289 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
291 if (rc && printk_ratelimit()) {
292 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
293 printk("\trc = %lld\n", rc);
294 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
295 printk("\tnpages = 0x%llx\n", (u64)npages);
296 show_stack(current, (unsigned long *)__get_SP());
300 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
303 unsigned long tce_ret;
305 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
307 if (rc && printk_ratelimit()) {
308 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
309 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
310 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
311 show_stack(current, (unsigned long *)__get_SP());
317 /* this is compatible with cells for the device tree property */
318 struct dynamic_dma_window_prop {
319 __be32 liobn; /* tce table number */
320 __be64 dma_base; /* address hi,lo */
321 __be32 tce_shift; /* ilog2(tce_page_size) */
322 __be32 window_shift; /* ilog2(tce_window_size) */
325 struct direct_window {
326 struct device_node *device;
327 const struct dynamic_dma_window_prop *prop;
328 struct list_head list;
331 /* Dynamic DMA Window support */
332 struct ddw_query_response {
333 u32 windows_available;
334 u32 largest_available_block;
336 u32 migration_capable;
339 struct ddw_create_response {
345 static LIST_HEAD(direct_window_list);
346 /* prevents races between memory on/offline and window creation */
347 static DEFINE_SPINLOCK(direct_window_list_lock);
348 /* protects initializing window twice for same device */
349 static DEFINE_MUTEX(direct_window_init_mutex);
350 #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
352 static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
353 unsigned long num_pfn, const void *arg)
355 const struct dynamic_dma_window_prop *maprange = arg;
357 u64 tce_size, num_tce, dma_offset, next;
361 tce_shift = be32_to_cpu(maprange->tce_shift);
362 tce_size = 1ULL << tce_shift;
363 next = start_pfn << PAGE_SHIFT;
364 num_tce = num_pfn << PAGE_SHIFT;
366 /* round back to the beginning of the tce page size */
367 num_tce += next & (tce_size - 1);
368 next &= ~(tce_size - 1);
370 /* covert to number of tces */
371 num_tce |= tce_size - 1;
372 num_tce >>= tce_shift;
376 * Set up the page with TCE data, looping through and setting
379 limit = min_t(long, num_tce, 512);
380 dma_offset = next + be64_to_cpu(maprange->dma_base);
382 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
385 next += limit * tce_size;
387 } while (num_tce > 0 && !rc);
392 static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
393 unsigned long num_pfn, const void *arg)
395 const struct dynamic_dma_window_prop *maprange = arg;
396 u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn;
401 local_irq_disable(); /* to protect tcep and the page behind it */
402 tcep = __get_cpu_var(tce_page);
405 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
410 __get_cpu_var(tce_page) = tcep;
413 proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
415 liobn = (u64)be32_to_cpu(maprange->liobn);
416 tce_shift = be32_to_cpu(maprange->tce_shift);
417 tce_size = 1ULL << tce_shift;
418 next = start_pfn << PAGE_SHIFT;
419 num_tce = num_pfn << PAGE_SHIFT;
421 /* round back to the beginning of the tce page size */
422 num_tce += next & (tce_size - 1);
423 next &= ~(tce_size - 1);
425 /* covert to number of tces */
426 num_tce |= tce_size - 1;
427 num_tce >>= tce_shift;
429 /* We can map max one pageful of TCEs at a time */
432 * Set up the page with TCE data, looping through and setting
435 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
436 dma_offset = next + be64_to_cpu(maprange->dma_base);
438 for (l = 0; l < limit; l++) {
439 tcep[l] = proto_tce | next;
443 rc = plpar_tce_put_indirect(liobn,
449 } while (num_tce > 0 && !rc);
451 /* error cleanup: caller will clear whole range */
457 static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
458 unsigned long num_pfn, void *arg)
460 return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
465 static void iommu_table_setparms(struct pci_controller *phb,
466 struct device_node *dn,
467 struct iommu_table *tbl)
469 struct device_node *node;
470 const unsigned long *basep, *sw_inval;
475 basep = of_get_property(node, "linux,tce-base", NULL);
476 sizep = of_get_property(node, "linux,tce-size", NULL);
477 if (basep == NULL || sizep == NULL) {
478 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
479 "missing tce entries !\n", dn->full_name);
483 tbl->it_base = (unsigned long)__va(*basep);
485 if (!is_kdump_kernel())
486 memset((void *)tbl->it_base, 0, *sizep);
488 tbl->it_busno = phb->bus->number;
490 /* Units of tce entries */
491 tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
493 /* Test if we are going over 2GB of DMA space */
494 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
495 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
496 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
499 phb->dma_window_base_cur += phb->dma_window_size;
501 /* Set the tce table size - measured in entries */
502 tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
505 tbl->it_blocksize = 16;
506 tbl->it_type = TCE_PCI;
508 sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
511 * This property contains information on how to
512 * invalidate the TCE entry. The first property is
513 * the base MMIO address used to invalidate entries.
514 * The second property tells us the format of the TCE
515 * invalidate (whether it needs to be shifted) and
516 * some magic routing info to add to our invalidate
519 tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
520 tbl->it_busno = sw_inval[1]; /* overload this with magic */
521 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
526 * iommu_table_setparms_lpar
528 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
530 static void iommu_table_setparms_lpar(struct pci_controller *phb,
531 struct device_node *dn,
532 struct iommu_table *tbl,
533 const void *dma_window)
535 unsigned long offset, size;
537 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
539 tbl->it_busno = phb->bus->number;
541 tbl->it_blocksize = 16;
542 tbl->it_type = TCE_PCI;
543 tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
544 tbl->it_size = size >> IOMMU_PAGE_SHIFT;
547 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
549 struct device_node *dn;
550 struct iommu_table *tbl;
551 struct device_node *isa_dn, *isa_dn_orig;
552 struct device_node *tmp;
556 dn = pci_bus_to_OF_node(bus);
558 pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
561 /* This is not a root bus, any setup will be done for the
562 * device-side of the bridge in iommu_dev_setup_pSeries().
568 /* Check if the ISA bus on the system is under
571 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
573 while (isa_dn && isa_dn != dn)
574 isa_dn = isa_dn->parent;
577 of_node_put(isa_dn_orig);
579 /* Count number of direct PCI children of the PHB. */
580 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
583 pr_debug("Children: %d\n", children);
585 /* Calculate amount of DMA window per slot. Each window must be
586 * a power of two (due to pci_alloc_consistent requirements).
588 * Keep 256MB aside for PHBs with ISA.
592 /* No ISA/IDE - just set window size and return */
593 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
595 while (pci->phb->dma_window_size * children > 0x80000000ul)
596 pci->phb->dma_window_size >>= 1;
597 pr_debug("No ISA/IDE, window size is 0x%llx\n",
598 pci->phb->dma_window_size);
599 pci->phb->dma_window_base_cur = 0;
604 /* If we have ISA, then we probably have an IDE
605 * controller too. Allocate a 128MB table but
606 * skip the first 128MB to avoid stepping on ISA
609 pci->phb->dma_window_size = 0x8000000ul;
610 pci->phb->dma_window_base_cur = 0x8000000ul;
612 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
615 iommu_table_setparms(pci->phb, dn, tbl);
616 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
618 /* Divide the rest (1.75GB) among the children */
619 pci->phb->dma_window_size = 0x80000000ul;
620 while (pci->phb->dma_window_size * children > 0x70000000ul)
621 pci->phb->dma_window_size >>= 1;
623 pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
627 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
629 struct iommu_table *tbl;
630 struct device_node *dn, *pdn;
632 const void *dma_window = NULL;
634 dn = pci_bus_to_OF_node(bus);
636 pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
639 /* Find nearest ibm,dma-window, walking up the device tree */
640 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
641 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
642 if (dma_window != NULL)
646 if (dma_window == NULL) {
647 pr_debug(" no ibm,dma-window property !\n");
653 pr_debug(" parent is %s, iommu_table: 0x%p\n",
654 pdn->full_name, ppci->iommu_table);
656 if (!ppci->iommu_table) {
657 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
659 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
660 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
661 pr_debug(" created table: %p\n", ppci->iommu_table);
666 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
668 struct device_node *dn;
669 struct iommu_table *tbl;
671 pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
673 dn = dev->dev.of_node;
675 /* If we're the direct child of a root bus, then we need to allocate
676 * an iommu table ourselves. The bus setup code should have setup
677 * the window sizes already.
679 if (!dev->bus->self) {
680 struct pci_controller *phb = PCI_DN(dn)->phb;
682 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
683 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
685 iommu_table_setparms(phb, dn, tbl);
686 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
687 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
691 /* If this device is further down the bus tree, search upwards until
692 * an already allocated iommu table is found and use that.
695 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
698 if (dn && PCI_DN(dn))
699 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
701 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
705 static int __read_mostly disable_ddw;
707 static int __init disable_ddw_setup(char *str)
710 printk(KERN_INFO "ppc iommu: disabling ddw.\n");
715 early_param("disable_ddw", disable_ddw_setup);
717 static inline void __remove_ddw(struct device_node *np, const u32 *ddw_avail, u64 liobn)
721 ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
723 pr_warning("%s: failed to remove DMA window: rtas returned "
724 "%d to ibm,remove-pe-dma-window(%x) %llx\n",
725 np->full_name, ret, ddw_avail[2], liobn);
727 pr_debug("%s: successfully removed DMA window: rtas returned "
728 "%d to ibm,remove-pe-dma-window(%x) %llx\n",
729 np->full_name, ret, ddw_avail[2], liobn);
732 static void remove_ddw(struct device_node *np)
734 struct dynamic_dma_window_prop *dwp;
735 struct property *win64;
736 const u32 *ddw_avail;
740 ddw_avail = of_get_property(np, "ibm,ddw-applicable", &len);
741 win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
745 if (!ddw_avail || len < 3 * sizeof(u32) || win64->length < sizeof(*dwp))
749 liobn = (u64)be32_to_cpu(dwp->liobn);
751 /* clear the whole window, note the arg is in kernel pages */
752 ret = tce_clearrange_multi_pSeriesLP(0,
753 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
755 pr_warning("%s failed to clear tces in window.\n",
758 pr_debug("%s successfully cleared tces in window.\n",
761 __remove_ddw(np, ddw_avail, liobn);
764 ret = of_remove_property(np, win64);
766 pr_warning("%s: failed to remove direct window property: %d\n",
770 static u64 find_existing_ddw(struct device_node *pdn)
772 struct direct_window *window;
773 const struct dynamic_dma_window_prop *direct64;
776 spin_lock(&direct_window_list_lock);
777 /* check if we already created a window and dupe that config if so */
778 list_for_each_entry(window, &direct_window_list, list) {
779 if (window->device == pdn) {
780 direct64 = window->prop;
781 dma_addr = direct64->dma_base;
785 spin_unlock(&direct_window_list_lock);
790 static int find_existing_ddw_windows(void)
793 struct device_node *pdn;
794 struct direct_window *window;
795 const struct dynamic_dma_window_prop *direct64;
797 if (!firmware_has_feature(FW_FEATURE_LPAR))
800 for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
801 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
805 window = kzalloc(sizeof(*window), GFP_KERNEL);
806 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
812 window->device = pdn;
813 window->prop = direct64;
814 spin_lock(&direct_window_list_lock);
815 list_add(&window->list, &direct_window_list);
816 spin_unlock(&direct_window_list_lock);
821 machine_arch_initcall(pseries, find_existing_ddw_windows);
823 static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
824 struct ddw_query_response *query)
826 struct eeh_dev *edev;
832 * Get the config address and phb buid of the PE window.
833 * Rely on eeh to retrieve this for us.
834 * Retrieve them from the pci device, not the node with the
835 * dma-window property
837 edev = pci_dev_to_eeh_dev(dev);
838 cfg_addr = edev->config_addr;
839 if (edev->pe_config_addr)
840 cfg_addr = edev->pe_config_addr;
841 buid = edev->phb->buid;
843 ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
844 cfg_addr, BUID_HI(buid), BUID_LO(buid));
845 dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
846 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
851 static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
852 struct ddw_create_response *create, int page_shift,
855 struct eeh_dev *edev;
861 * Get the config address and phb buid of the PE window.
862 * Rely on eeh to retrieve this for us.
863 * Retrieve them from the pci device, not the node with the
864 * dma-window property
866 edev = pci_dev_to_eeh_dev(dev);
867 cfg_addr = edev->config_addr;
868 if (edev->pe_config_addr)
869 cfg_addr = edev->pe_config_addr;
870 buid = edev->phb->buid;
873 /* extra outputs are LIOBN and dma-addr (hi, lo) */
874 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create, cfg_addr,
875 BUID_HI(buid), BUID_LO(buid), page_shift, window_shift);
876 } while (rtas_busy_delay(ret));
878 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
879 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
880 cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
881 window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
886 static void restore_default_window(struct pci_dev *dev,
887 u32 ddw_restore_token)
889 struct eeh_dev *edev;
895 * Get the config address and phb buid of the PE window.
896 * Rely on eeh to retrieve this for us.
897 * Retrieve them from the pci device, not the node with the
898 * dma-window property
900 edev = pci_dev_to_eeh_dev(dev);
901 cfg_addr = edev->config_addr;
902 if (edev->pe_config_addr)
903 cfg_addr = edev->pe_config_addr;
904 buid = edev->phb->buid;
907 ret = rtas_call(ddw_restore_token, 3, 1, NULL, cfg_addr,
908 BUID_HI(buid), BUID_LO(buid));
909 } while (rtas_busy_delay(ret));
911 "ibm,reset-pe-dma-windows(%x) %x %x %x returned %d\n",
912 ddw_restore_token, cfg_addr, BUID_HI(buid), BUID_LO(buid), ret);
916 * If the PE supports dynamic dma windows, and there is space for a table
917 * that can map all pages in a linear offset, then setup such a table,
918 * and record the dma-offset in the struct device.
920 * dev: the pci device we are checking
921 * pdn: the parent pe node with the ibm,dma_window property
922 * Future: also check if we can remap the base window for our base page size
924 * returns the dma offset for use by dma_set_mask
926 static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
929 struct ddw_query_response query;
930 struct ddw_create_response create;
932 u64 dma_addr, max_addr;
933 struct device_node *dn;
934 const u32 *uninitialized_var(ddw_avail);
935 const u32 *uninitialized_var(ddw_extensions);
936 u32 ddw_restore_token = 0;
937 struct direct_window *window;
938 struct property *win64;
939 struct dynamic_dma_window_prop *ddwprop;
940 const void *dma_window = NULL;
941 unsigned long liobn, offset, size;
943 mutex_lock(&direct_window_init_mutex);
945 dma_addr = find_existing_ddw(pdn);
950 * the ibm,ddw-applicable property holds the tokens for:
951 * ibm,query-pe-dma-window
952 * ibm,create-pe-dma-window
953 * ibm,remove-pe-dma-window
954 * for the given node in that order.
955 * the property is actually in the parent, not the PE
957 ddw_avail = of_get_property(pdn, "ibm,ddw-applicable", &len);
958 if (!ddw_avail || len < 3 * sizeof(u32))
962 * the extensions property is only required to exist in certain
963 * levels of firmware and later
964 * the ibm,ddw-extensions property is a list with the first
965 * element containing the number of extensions and each
966 * subsequent entry is a value corresponding to that extension
968 ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions", &len);
969 if (ddw_extensions) {
971 * each new defined extension length should be added to
972 * the top of the switch so the "earlier" entries also
975 switch (ddw_extensions[0]) {
976 /* ibm,reset-pe-dma-windows */
978 ddw_restore_token = ddw_extensions[1];
984 * Only remove the existing DMA window if we can restore back to
985 * the default state. Removing the existing window maximizes the
986 * resources available to firmware for dynamic window creation.
988 if (ddw_restore_token) {
989 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
990 of_parse_dma_window(pdn, dma_window, &liobn, &offset, &size);
991 __remove_ddw(pdn, ddw_avail, liobn);
995 * Query if there is a second window of size to map the
996 * whole partition. Query returns number of windows, largest
997 * block assigned to PE (partition endpoint), and two bitmasks
998 * of page sizes: supported and supported for migrate-dma.
1000 dn = pci_device_to_OF_node(dev);
1001 ret = query_ddw(dev, ddw_avail, &query);
1003 goto out_restore_window;
1005 if (query.windows_available == 0) {
1007 * no additional windows are available for this device.
1008 * We might be able to reallocate the existing window,
1009 * trading in for a larger page size.
1011 dev_dbg(&dev->dev, "no free dynamic windows");
1012 goto out_restore_window;
1014 if (query.page_size & 4) {
1015 page_shift = 24; /* 16MB */
1016 } else if (query.page_size & 2) {
1017 page_shift = 16; /* 64kB */
1018 } else if (query.page_size & 1) {
1019 page_shift = 12; /* 4kB */
1021 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
1023 goto out_restore_window;
1025 /* verify the window * number of ptes will map the partition */
1026 /* check largest block * page size > max memory hotplug addr */
1027 max_addr = memory_hotplug_max();
1028 if (query.largest_available_block < (max_addr >> page_shift)) {
1029 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
1030 "%llu-sized pages\n", max_addr, query.largest_available_block,
1031 1ULL << page_shift);
1032 goto out_restore_window;
1034 len = order_base_2(max_addr);
1035 win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
1038 "couldn't allocate property for 64bit dma window\n");
1039 goto out_restore_window;
1041 win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
1042 win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
1043 win64->length = sizeof(*ddwprop);
1044 if (!win64->name || !win64->value) {
1046 "couldn't allocate property name and value\n");
1050 ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
1054 ddwprop->liobn = cpu_to_be32(create.liobn);
1055 ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2));
1056 ddwprop->tce_shift = cpu_to_be32(page_shift);
1057 ddwprop->window_shift = cpu_to_be32(len);
1059 dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
1060 create.liobn, dn->full_name);
1062 window = kzalloc(sizeof(*window), GFP_KERNEL);
1064 goto out_clear_window;
1066 ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
1067 win64->value, tce_setrange_multi_pSeriesLP_walk);
1069 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
1070 dn->full_name, ret);
1071 goto out_free_window;
1074 ret = of_add_property(pdn, win64);
1076 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
1077 pdn->full_name, ret);
1078 goto out_free_window;
1081 window->device = pdn;
1082 window->prop = ddwprop;
1083 spin_lock(&direct_window_list_lock);
1084 list_add(&window->list, &direct_window_list);
1085 spin_unlock(&direct_window_list_lock);
1087 dma_addr = of_read_number(&create.addr_hi, 2);
1098 kfree(win64->value);
1102 if (ddw_restore_token)
1103 restore_default_window(dev, ddw_restore_token);
1106 mutex_unlock(&direct_window_init_mutex);
1110 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1112 struct device_node *pdn, *dn;
1113 struct iommu_table *tbl;
1114 const void *dma_window = NULL;
1117 pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1119 /* dev setup for LPAR is a little tricky, since the device tree might
1120 * contain the dma-window properties per-device and not necessarily
1121 * for the bus. So we need to search upwards in the tree until we
1122 * either hit a dma-window property, OR find a parent with a table
1123 * already allocated.
1125 dn = pci_device_to_OF_node(dev);
1126 pr_debug(" node is %s\n", dn->full_name);
1128 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1129 pdn = pdn->parent) {
1130 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1135 if (!pdn || !PCI_DN(pdn)) {
1136 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1137 "no DMA window found for pci dev=%s dn=%s\n",
1138 pci_name(dev), of_node_full_name(dn));
1141 pr_debug(" parent is %s\n", pdn->full_name);
1144 if (!pci->iommu_table) {
1145 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
1147 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1148 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
1149 pr_debug(" created table: %p\n", pci->iommu_table);
1151 pr_debug(" found DMA window, table: %p\n", pci->iommu_table);
1154 set_iommu_table_base(&dev->dev, pci->iommu_table);
1157 static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1159 bool ddw_enabled = false;
1160 struct device_node *pdn, *dn;
1161 struct pci_dev *pdev;
1162 const void *dma_window = NULL;
1168 if (!dev_is_pci(dev))
1171 pdev = to_pci_dev(dev);
1173 /* only attempt to use a new window if 64-bit DMA is requested */
1174 if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1175 dn = pci_device_to_OF_node(pdev);
1176 dev_dbg(dev, "node is %s\n", dn->full_name);
1179 * the device tree might contain the dma-window properties
1180 * per-device and not necessarily for the bus. So we need to
1181 * search upwards in the tree until we either hit a dma-window
1182 * property, OR find a parent with a table already allocated.
1184 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1185 pdn = pdn->parent) {
1186 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1190 if (pdn && PCI_DN(pdn)) {
1191 dma_offset = enable_ddw(pdev, pdn);
1192 if (dma_offset != 0) {
1193 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1194 set_dma_offset(dev, dma_offset);
1195 set_dma_ops(dev, &dma_direct_ops);
1201 /* fall back on iommu ops, restore table pointer with ops */
1202 if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1203 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1204 set_dma_ops(dev, &dma_iommu_ops);
1205 pci_dma_dev_setup_pSeriesLP(pdev);
1209 if (!dma_supported(dev, dma_mask))
1212 *dev->dma_mask = dma_mask;
1216 static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1221 if (!disable_ddw && dev_is_pci(dev)) {
1222 struct pci_dev *pdev = to_pci_dev(dev);
1223 struct device_node *dn;
1225 dn = pci_device_to_OF_node(pdev);
1227 /* search upwards for ibm,dma-window */
1228 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->iommu_table;
1230 if (of_get_property(dn, "ibm,dma-window", NULL))
1232 /* if there is a ibm,ddw-applicable property require 64 bits */
1233 if (dn && PCI_DN(dn) &&
1234 of_get_property(dn, "ibm,ddw-applicable", NULL))
1235 return DMA_BIT_MASK(64);
1238 return dma_iommu_ops.get_required_mask(dev);
1241 #else /* CONFIG_PCI */
1242 #define pci_dma_bus_setup_pSeries NULL
1243 #define pci_dma_dev_setup_pSeries NULL
1244 #define pci_dma_bus_setup_pSeriesLP NULL
1245 #define pci_dma_dev_setup_pSeriesLP NULL
1246 #define dma_set_mask_pSeriesLP NULL
1247 #define dma_get_required_mask_pSeriesLP NULL
1248 #endif /* !CONFIG_PCI */
1250 static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1253 struct direct_window *window;
1254 struct memory_notify *arg = data;
1258 case MEM_GOING_ONLINE:
1259 spin_lock(&direct_window_list_lock);
1260 list_for_each_entry(window, &direct_window_list, list) {
1261 ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1262 arg->nr_pages, window->prop);
1265 spin_unlock(&direct_window_list_lock);
1267 case MEM_CANCEL_ONLINE:
1269 spin_lock(&direct_window_list_lock);
1270 list_for_each_entry(window, &direct_window_list, list) {
1271 ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1272 arg->nr_pages, window->prop);
1275 spin_unlock(&direct_window_list_lock);
1280 if (ret && action != MEM_CANCEL_ONLINE)
1286 static struct notifier_block iommu_mem_nb = {
1287 .notifier_call = iommu_mem_notifier,
1290 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
1292 int err = NOTIFY_OK;
1293 struct device_node *np = node;
1294 struct pci_dn *pci = PCI_DN(np);
1295 struct direct_window *window;
1298 case OF_RECONFIG_DETACH_NODE:
1300 if (pci && pci->iommu_table)
1301 iommu_free_table(pci->iommu_table, np->full_name);
1303 spin_lock(&direct_window_list_lock);
1304 list_for_each_entry(window, &direct_window_list, list) {
1305 if (window->device == np) {
1306 list_del(&window->list);
1311 spin_unlock(&direct_window_list_lock);
1320 static struct notifier_block iommu_reconfig_nb = {
1321 .notifier_call = iommu_reconfig_notifier,
1324 /* These are called very early. */
1325 void iommu_init_early_pSeries(void)
1327 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1330 if (firmware_has_feature(FW_FEATURE_LPAR)) {
1331 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
1332 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
1333 ppc_md.tce_free = tce_freemulti_pSeriesLP;
1335 ppc_md.tce_build = tce_build_pSeriesLP;
1336 ppc_md.tce_free = tce_free_pSeriesLP;
1338 ppc_md.tce_get = tce_get_pSeriesLP;
1339 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1340 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1341 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1342 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1344 ppc_md.tce_build = tce_build_pSeries;
1345 ppc_md.tce_free = tce_free_pSeries;
1346 ppc_md.tce_get = tce_get_pseries;
1347 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
1348 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
1352 of_reconfig_notifier_register(&iommu_reconfig_nb);
1353 register_memory_notifier(&iommu_mem_nb);
1355 set_pci_dma_ops(&dma_iommu_ops);
1358 static int __init disable_multitce(char *str)
1360 if (strcmp(str, "off") == 0 &&
1361 firmware_has_feature(FW_FEATURE_LPAR) &&
1362 firmware_has_feature(FW_FEATURE_MULTITCE)) {
1363 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1364 ppc_md.tce_build = tce_build_pSeriesLP;
1365 ppc_md.tce_free = tce_free_pSeriesLP;
1366 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1371 __setup("multitce=", disable_multitce);