2 * Copyright 2011 IBM Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/types.h>
11 #include <linux/threads.h>
12 #include <linux/kernel.h>
13 #include <linux/irq.h>
14 #include <linux/debugfs.h>
15 #include <linux/smp.h>
16 #include <linux/interrupt.h>
17 #include <linux/seq_file.h>
18 #include <linux/init.h>
19 #include <linux/cpu.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
28 #include <asm/machdep.h>
30 #include <asm/errno.h>
33 #include <asm/firmware.h>
35 /* Globals common to all ICP/ICS implementations */
36 const struct icp_ops *icp_ops;
38 unsigned int xics_default_server = 0xff;
39 unsigned int xics_default_distrib_server = 0;
40 unsigned int xics_interrupt_server_size = 8;
42 DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
44 struct irq_domain *xics_host;
46 static LIST_HEAD(ics_list);
48 void xics_update_irq_servers(void)
51 struct device_node *np;
56 /* Find the server numbers for the boot cpu. */
57 np = of_get_cpu_node(boot_cpuid, NULL);
60 hcpuid = get_hard_smp_processor_id(boot_cpuid);
61 xics_default_server = xics_default_distrib_server = hcpuid;
63 pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);
65 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
71 i = ilen / sizeof(int);
73 /* Global interrupt distribution server is specified in the last
74 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
75 * entry fom this property for current boot cpu id and use it as
76 * default distribution server
78 for (j = 0; j < i; j += 2) {
79 if (be32_to_cpu(ireg[j]) == hcpuid) {
80 xics_default_distrib_server = be32_to_cpu(ireg[j+1]);
84 pr_devel("xics: xics_default_distrib_server = 0x%x\n",
85 xics_default_distrib_server);
89 /* GIQ stuff, currently only supported on RTAS setups, will have
90 * to be sorted properly for bare metal
92 void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
94 #ifdef CONFIG_PPC_RTAS
98 if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
101 index = (1UL << xics_interrupt_server_size) - 1 - gserver;
103 status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
105 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
106 GLOBAL_INTERRUPT_QUEUE, index, join, status);
110 void xics_setup_cpu(void)
112 icp_ops->set_priority(LOWEST_PRIORITY);
114 xics_set_cpu_giq(xics_default_distrib_server, 1);
117 void xics_mask_unknown_vec(unsigned int vec)
121 pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);
123 list_for_each_entry(ics, &ics_list, link)
124 ics->mask_unknown(ics, vec);
130 static void xics_request_ipi(void)
134 ipi = irq_create_mapping(xics_host, XICS_IPI);
138 * IPIs are marked IRQF_PERCPU. The handler was set in map.
140 BUG_ON(request_irq(ipi, icp_ops->ipi_action,
141 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
144 void __init xics_smp_probe(void)
146 /* Register all the IPIs */
150 #endif /* CONFIG_SMP */
152 void xics_teardown_cpu(void)
154 struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr);
157 * we have to reset the cppr index to 0 because we're
158 * not going to return from the IPI
161 icp_ops->set_priority(0);
162 icp_ops->teardown_cpu();
165 void xics_kexec_teardown_cpu(int secondary)
169 icp_ops->flush_ipi();
172 * Some machines need to have at least one cpu in the GIQ,
173 * so leave the master cpu in the group.
176 xics_set_cpu_giq(xics_default_distrib_server, 0);
180 #ifdef CONFIG_HOTPLUG_CPU
182 /* Interrupts are disabled. */
183 void xics_migrate_irqs_away(void)
185 int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
186 unsigned int irq, virq;
187 struct irq_desc *desc;
189 /* If we used to be the default server, move to the new "boot_cpuid" */
190 if (hw_cpu == xics_default_server)
191 xics_update_irq_servers();
193 /* Reject any interrupt that was queued to us... */
194 icp_ops->set_priority(0);
196 /* Remove ourselves from the global interrupt queue */
197 xics_set_cpu_giq(xics_default_distrib_server, 0);
199 for_each_irq_desc(virq, desc) {
200 struct irq_chip *chip;
205 /* We can't set affinity on ISA interrupts */
206 if (virq < NUM_ISA_INTERRUPTS)
208 /* We only need to migrate enabled IRQS */
211 if (desc->irq_data.domain != xics_host)
213 irq = desc->irq_data.hwirq;
214 /* We need to get IPIs still. */
215 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
217 chip = irq_desc_get_chip(desc);
218 if (!chip || !chip->irq_set_affinity)
221 raw_spin_lock_irqsave(&desc->lock, flags);
223 /* Locate interrupt server */
225 ics = irq_desc_get_chip_data(desc);
227 server = ics->get_server(ics, irq);
229 printk(KERN_ERR "%s: Can't find server for irq %d\n",
234 /* We only support delivery to all cpus or to one cpu.
235 * The irq has to be migrated only in the single cpu
238 if (server != hw_cpu)
241 /* This is expected during cpu offline. */
243 pr_warning("IRQ %u affinity broken off cpu %u\n",
246 /* Reset affinity to all cpus */
247 raw_spin_unlock_irqrestore(&desc->lock, flags);
248 irq_set_affinity(virq, cpu_all_mask);
251 raw_spin_unlock_irqrestore(&desc->lock, flags);
254 /* Allow "sufficient" time to drop any inflight IRQ's */
258 * Allow IPIs again. This is done at the very end, after migrating all
259 * interrupts, the expectation is that we'll only get woken up by an IPI
260 * interrupt beyond this point, but leave externals masked just to be
261 * safe. If we're using icp-opal this may actually allow all
262 * interrupts anyway, but that should be OK.
264 icp_ops->set_priority(DEFAULT_PRIORITY);
267 #endif /* CONFIG_HOTPLUG_CPU */
271 * For the moment we only implement delivery to all cpus or one cpu.
273 * If the requested affinity is cpu_all_mask, we set global affinity.
274 * If not we set it to the first cpu in the mask, even if multiple cpus
275 * are set. This is so things like irqbalance (which set core and package
276 * wide affinities) do the right thing.
278 * We need to fix this to implement support for the links
280 int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
281 unsigned int strict_check)
284 if (!distribute_irqs)
285 return xics_default_server;
287 if (!cpumask_subset(cpu_possible_mask, cpumask)) {
288 int server = cpumask_first_and(cpu_online_mask, cpumask);
290 if (server < nr_cpu_ids)
291 return get_hard_smp_processor_id(server);
298 * Workaround issue with some versions of JS20 firmware that
299 * deliver interrupts to cpus which haven't been started. This
300 * happens when using the maxcpus= boot option.
302 if (cpumask_equal(cpu_online_mask, cpu_present_mask))
303 return xics_default_distrib_server;
305 return xics_default_server;
307 #endif /* CONFIG_SMP */
309 static int xics_host_match(struct irq_domain *h, struct device_node *node,
310 enum irq_domain_bus_token bus_token)
314 list_for_each_entry(ics, &ics_list, link)
315 if (ics->host_match(ics, node))
322 static void xics_ipi_unmask(struct irq_data *d) { }
323 static void xics_ipi_mask(struct irq_data *d) { }
325 static struct irq_chip xics_ipi_chip = {
327 .irq_eoi = NULL, /* Patched at init time */
328 .irq_mask = xics_ipi_mask,
329 .irq_unmask = xics_ipi_unmask,
332 static int xics_host_map(struct irq_domain *h, unsigned int virq,
337 pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
340 * Mark interrupts as edge sensitive by default so that resend
341 * actually works. The device-tree parsing will turn the LSIs
344 irq_clear_status_flags(virq, IRQ_LEVEL);
346 /* Don't call into ICS for IPIs */
347 if (hw == XICS_IPI) {
348 irq_set_chip_and_handler(virq, &xics_ipi_chip,
353 /* Let the ICS setup the chip data */
354 list_for_each_entry(ics, &ics_list, link)
355 if (ics->map(ics, virq) == 0)
361 static int xics_host_xlate(struct irq_domain *h, struct device_node *ct,
362 const u32 *intspec, unsigned int intsize,
363 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
366 *out_hwirq = intspec[0];
369 * If intsize is at least 2, we look for the type in the second cell,
370 * we assume the LSB indicates a level interrupt.
374 *out_flags = IRQ_TYPE_LEVEL_LOW;
376 *out_flags = IRQ_TYPE_EDGE_RISING;
378 *out_flags = IRQ_TYPE_LEVEL_LOW;
383 int xics_set_irq_type(struct irq_data *d, unsigned int flow_type)
386 * We only support these. This has really no effect other than setting
387 * the corresponding descriptor bits mind you but those will in turn
388 * affect the resend function when re-enabling an edge interrupt.
390 * Set set the default to edge as explained in map().
392 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
393 flow_type = IRQ_TYPE_EDGE_RISING;
395 if (flow_type != IRQ_TYPE_EDGE_RISING &&
396 flow_type != IRQ_TYPE_LEVEL_LOW)
399 irqd_set_trigger_type(d, flow_type);
401 return IRQ_SET_MASK_OK_NOCOPY;
404 int xics_retrigger(struct irq_data *data)
407 * We need to push a dummy CPPR when retriggering, since the subsequent
408 * EOI will try to pop it. Passing 0 works, as the function hard codes
409 * the priority value anyway.
413 /* Tell the core to do a soft retrigger */
417 static const struct irq_domain_ops xics_host_ops = {
418 .match = xics_host_match,
419 .map = xics_host_map,
420 .xlate = xics_host_xlate,
423 static void __init xics_init_host(void)
425 xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
426 BUG_ON(xics_host == NULL);
427 irq_set_default_host(xics_host);
430 void __init xics_register_ics(struct ics *ics)
432 list_add(&ics->link, &ics_list);
435 static void __init xics_get_server_size(void)
437 struct device_node *np;
440 /* We fetch the interrupt server size from the first ICS node
443 np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
446 isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
449 xics_interrupt_server_size = be32_to_cpu(*isize);
453 void __init xics_init(void)
457 /* Fist locate ICP */
458 if (firmware_has_feature(FW_FEATURE_LPAR))
461 rc = icp_native_init();
463 rc = icp_opal_init();
466 pr_warning("XICS: Cannot find a Presentation Controller !\n");
470 /* Copy get_irq callback over to ppc_md */
471 ppc_md.get_irq = icp_ops->get_irq;
473 /* Patch up IPI chip EOI */
474 xics_ipi_chip.irq_eoi = icp_ops->eoi;
477 rc = ics_rtas_init();
479 rc = ics_opal_init();
481 pr_warning("XICS: Cannot find a Source Controller !\n");
483 /* Initialize common bits */
484 xics_get_server_size();
485 xics_update_irq_servers();